[llvm-branch-commits] [llvm] [AArch64][llvm] Armv9.8-A: Add support for FEAT_RLCS (release consistency scoping) (PR #229364)

[Jonathan Thackray via llvm-branch-commits]

https://github.com/jthackray updated https://github.com/llvm/llvm-project/pull/229364

>From 9d0e1c80859bb84638f6284ac5d55479bd358ea3 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray <jonathan.thackray at arm.com>
Date: Mon, 14 Sep 2026 17:39:07 +0100
Subject: [PATCH] [AArch64][llvm] Armv9.8-A: Add support for FEAT_RLCS (release
 consistency scoping)

Add support for FEAT_RLCS (release consistency scoping) instructions:
  - SRLS
  - SLBND
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.td   |  3 ++
 .../AArch64/AsmParser/AArch64AsmParser.cpp    |  4 ++-
 .../MC/AArch64/armv9.8a-rlcs-diagnostics.s    | 31 +++++++++++++++++
 llvm/test/MC/AArch64/armv9.8a-rlcs.s          | 33 +++++++++++++++++++
 4 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/MC/AArch64/armv9.8a-rlcs-diagnostics.s
 create mode 100644 llvm/test/MC/AArch64/armv9.8a-rlcs.s

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 8e64d275f9e354..f96414d84df95d 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -1621,6 +1621,9 @@ def : InstAlias<"stshh strm", (HINT 49), 1>;
 def : InstAlias<"shuh", (HINT 50), 1>;
 def : InstAlias<"shuh ph", (HINT 51), 1>;
 def : InstAlias<"stcph", (HINT 52), 1>;
+def : InstAlias<"srls", (HINT 54)>;
+def : InstAlias<"srls stshstrm", (HINT 55)>;
+def : InstAlias<"slbnd", (HINT 56)>;
 
 // In order to be able to write readable assembly, LLVM should accept assembly
 // inputs that use Branch Target Identification mnemonics, even with BTI disabled.
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index f8724d306b4c5c..3fe6d140974851 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -4933,6 +4933,7 @@ bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
                 .Case("ph", "ph")
                 .Case("r", "r")
                 .Case("sm", "sm")
+                .Case("stshstrm", "stshstrm")
                 .Case("strm", "strm")
                 .Case("za", "za")
                 .Default(Keyword);
@@ -5046,7 +5047,8 @@ bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
     // operand as an identifier.
     if (Mnemonic == "brb" || Mnemonic == "smstart" || Mnemonic == "smstop" ||
         Mnemonic == "gcsb" || Mnemonic == "bti" || Mnemonic == "stshh" ||
-        Mnemonic == "psb" || Mnemonic == "tsb" || Mnemonic == "shuh")
+        Mnemonic == "psb" || Mnemonic == "tsb" || Mnemonic == "shuh" ||
+        Mnemonic == "srls")
       return parseKeywordOperand(Operands);
 
     // This was not a register so parse other operands that start with an
diff --git a/llvm/test/MC/AArch64/armv9.8a-rlcs-diagnostics.s b/llvm/test/MC/AArch64/armv9.8a-rlcs-diagnostics.s
new file mode 100644
index 00000000000000..dbcccab1cf2ad5
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.8a-rlcs-diagnostics.s
@@ -0,0 +1,31 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 | FileCheck %s
+
+srls x0
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: srls x0
+// CHECK-NEXT:      ^
+
+srls inj
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: srls inj
+// CHECK-NEXT:      ^
+
+srls #0
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: srls #0
+// CHECK-NEXT:      ^
+
+srls 0
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: srls 0
+// CHECK-NEXT:      ^
+
+srls stshstrm, x0
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: srls stshstrm, x0
+// CHECK-NEXT:                ^
+
+slbnd x0
+// CHECK:      error: invalid operand for instruction
+// CHECK-NEXT: slbnd x0
+// CHECK-NEXT:       ^
diff --git a/llvm/test/MC/AArch64/armv9.8a-rlcs.s b/llvm/test/MC/AArch64/armv9.8a-rlcs.s
new file mode 100644
index 00000000000000..11a4e08a27e27b
--- /dev/null
+++ b/llvm/test/MC/AArch64/armv9.8a-rlcs.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
+// RUN:        | llvm-objdump -d --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+srls
+// CHECK-INST: srls
+// CHECK-ENCODING: encoding: [0xdf,0x26,0x03,0xd5]
+
+srls stshstrm
+// CHECK-INST: srls stshstrm
+// CHECK-ENCODING: encoding: [0xff,0x26,0x03,0xd5]
+
+slbnd
+// CHECK-INST: slbnd
+// CHECK-ENCODING: encoding: [0x1f,0x27,0x03,0xd5]
+
+hint #54
+// CHECK-INST: srls
+// CHECK-ENCODING: encoding: [0xdf,0x26,0x03,0xd5]
+
+hint #55
+// CHECK-INST: srls stshstrm
+// CHECK-ENCODING: encoding: [0xff,0x26,0x03,0xd5]
+
+hint #56
+// CHECK-INST: slbnd
+// CHECK-ENCODING: encoding: [0x1f,0x27,0x03,0xd5]