[llvm-branch-commits] [llvm] [AMDGPU] Narrow provably-I32 address offsets (PR #224737)

[Dmitry Sidorov via llvm-branch-commits]

MrSidims wrote:

> Seems like it belongs at a way earlier point? I would hope any basic address arithmetic stuff would have been done in the IR long before

InstCombine's narrowMathIfNoOverflow does it, but:
a. it keeps shl (zext a), (zext b) in i64. I suppose, that teaching narrowMathIfNoOverflow about shl would fix that in IR;
b. values defined in another block, where the use block only sees a CopyFromReg;
c. shouldn't we do the address narrowing with -O0? If yes - InstCombine won't do it for us in this case.

https://github.com/llvm/llvm-project/pull/224737