[llvm-branch-commits] [llvm] [SLP] Drop the context of a vector fmul whose user is not vectorized (PR #228902)
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llvm-branch-commits at lists.llvm.org
Sun Oct 4 08:13:23 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Dmitry Sidorov (MrSidims)
<details>
<summary>Changes</summary>
Pass the context of a vector fmul only when its user is vectorized or
the target emits it lane by lane. AMDGPU prices an fmul with a contract
fadd user as free, which does not hold for the extracted lanes of a
root. Other operations keep their context for the fast math flags and
the function attributes.
---
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---
Patch is 23.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/228902.diff
4 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (+16-4)
- (modified) llvm/test/CodeGen/AMDGPU/slp-coalesced-loads.ll (+13-17)
- (modified) llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-coalesced-loads.ll (+64-16)
- (modified) llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll (+38-37)
``````````diff
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index c105f41bc15ab..25953e843be40 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -17575,9 +17575,22 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
unsigned OpIdx = isa<UnaryOperator>(VL0) ? 0 : 1;
TTI::OperandValueInfo Op1Info = getOperandInfo(E->getOperand(0));
TTI::OperandValueInfo Op2Info = getOperandInfo(E->getOperand(OpIdx));
+ // A target may price an fmul by the fadd or fsub user of its context.
+ // The vector fmul keeps that user when this tree vectorizes the user
+ // too or when the target emits the fmul lane by lane. The lanes of a
+ // root are extracted otherwise and their scalar users stay as they are.
+ // Every other operation keeps its context, targets read the fast math
+ // flags and the function attributes from it.
+ const TreeEntry *UserTE = E->UserTreeIndex.UserTE;
+ bool KeepsContext =
+ ShuffleOrOp != Instruction::FMul ||
+ (UserTE && !UserTE->isGather() && !DeletedNodes.contains(UserTE) &&
+ !TransformedToGatherNodes.contains(UserTE)) ||
+ TTI->getMaximumVF(DL->getTypeSizeInBits(ScalarTy), ShuffleOrOp) == 1;
+ Instruction *CxtI =
+ VL0->getOpcode() == ShuffleOrOp && KeepsContext ? VL0 : nullptr;
InstructionCost Cost = TTI->getArithmeticInstrCost(
- ShuffleOrOp, VecTy, CostKind, Op1Info, Op2Info, {},
- VL0->getOpcode() == ShuffleOrOp ? VL0 : nullptr, TLI);
+ ShuffleOrOp, VecTy, CostKind, Op1Info, Op2Info, {}, CxtI, TLI);
// N columns need N-1 vector combines; price extra columns
// conservatively, skipping identity-only columns (not combined by
// codegen).
@@ -17592,8 +17605,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
// static properties to model.
Cost += TTI->getArithmeticInstrCost(
ShuffleOrOp, VecTy, CostKind, {},
- getOperandInfo(E->getOperand(Idx)), {},
- VL0->getOpcode() == ShuffleOrOp ? VL0 : nullptr, TLI);
+ getOperandInfo(E->getOperand(Idx)), {}, CxtI, TLI);
}
}
return Cost + CommonCost;
diff --git a/llvm/test/CodeGen/AMDGPU/slp-coalesced-loads.ll b/llvm/test/CodeGen/AMDGPU/slp-coalesced-loads.ll
index 4ac9d6adf090e..4db68adac00aa 100644
--- a/llvm/test/CodeGen/AMDGPU/slp-coalesced-loads.ll
+++ b/llvm/test/CodeGen/AMDGPU/slp-coalesced-loads.ll
@@ -284,27 +284,23 @@ define float @dot_i16_window(ptr addrspace(1) %a, ptr addrspace(1) %b, float %ac
; GFX1250-NEXT: global_load_b128 v[6:9], v[2:3], off
; GFX1250-NEXT: s_wait_loadcnt 0x1
; GFX1250-NEXT: s_wait_xcnt 0x1
-; GFX1250-NEXT: v_ashrrev_i32_e32 v0, 16, v10
+; GFX1250-NEXT: v_bfe_i32 v0, v10, 0, 16
; GFX1250-NEXT: s_wait_xcnt 0x0
-; GFX1250-NEXT: v_bfe_i32 v2, v10, 0, 16
-; GFX1250-NEXT: v_bfe_i32 v5, v11, 0, 16
+; GFX1250-NEXT: v_dual_ashrrev_i32 v1, 16, v10 :: v_dual_ashrrev_i32 v3, 16, v11
+; GFX1250-NEXT: v_bfe_i32 v2, v11, 0, 16
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT: v_cvt_f32_i32_e32 v1, v0
-; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v2
-; GFX1250-NEXT: v_ashrrev_i32_e32 v2, 16, v11
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_pk_mul_f32 v[0:1], v[0:1], v[6:7]
-; GFX1250-NEXT: v_cvt_f32_i32_e32 v3, v2
-; GFX1250-NEXT: v_cvt_f32_i32_e32 v2, v5
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT: v_add_f32_e32 v0, v4, v0
-; GFX1250-NEXT: v_pk_mul_f32 v[2:3], v[2:3], v[8:9]
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX1250-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX1250-NEXT: v_fma_f32 v0, v0, v6, v4
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT: v_fmac_f32_e32 v0, v1, v7
+; GFX1250-NEXT: v_cvt_f32_i32_e32 v1, v3
+; GFX1250-NEXT: v_fmac_f32_e32 v0, v2, v8
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_add_f32_e32 v0, v0, v3
+; GFX1250-NEXT: v_fmac_f32_e32 v0, v1, v9
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
entry:
%a1 = getelementptr inbounds nuw i8, ptr addrspace(1) %a, i64 2
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-coalesced-loads.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-coalesced-loads.ll
index f7f2f69c1366e..3a41dc15103c1 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-coalesced-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-coalesced-loads.ll
@@ -167,22 +167,70 @@ declare i64 @_Z13get_global_idj(i32 noundef)
; coalesced loads and stay scalar too.
define float @dot_i16_window(ptr addrspace(1) %a, ptr addrspace(1) %b, float %acc) {
-; CHECK-LABEL: define float @dot_i16_window(
-; CHECK-SAME: ptr addrspace(1) [[A:%.*]], ptr addrspace(1) [[B:%.*]], float [[ACC:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr addrspace(1) [[A]], align 2
-; CHECK-NEXT: [[TMP1:%.*]] = sitofp <4 x i16> [[TMP0]] to <4 x float>
-; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr addrspace(1) [[B]], align 4
-; CHECK-NEXT: [[TMP3:%.*]] = fmul contract <4 x float> [[TMP1]], [[TMP2]]
-; CHECK-NEXT: [[M0:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
-; CHECK-NEXT: [[S0:%.*]] = fadd contract float [[ACC]], [[M0]]
-; CHECK-NEXT: [[M1:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
-; CHECK-NEXT: [[S1:%.*]] = fadd contract float [[S0]], [[M1]]
-; CHECK-NEXT: [[M2:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
-; CHECK-NEXT: [[S2:%.*]] = fadd contract float [[S1]], [[M2]]
-; CHECK-NEXT: [[M3:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
-; CHECK-NEXT: [[S3:%.*]] = fadd contract float [[S2]], [[M3]]
-; CHECK-NEXT: ret float [[S3]]
+; GFX9-LABEL: define float @dot_i16_window(
+; GFX9-SAME: ptr addrspace(1) [[A:%.*]], ptr addrspace(1) [[B:%.*]], float [[ACC:%.*]]) {
+; GFX9-NEXT: [[ENTRY:.*:]]
+; GFX9-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr addrspace(1) [[A]], align 2
+; GFX9-NEXT: [[TMP1:%.*]] = sitofp <4 x i16> [[TMP0]] to <4 x float>
+; GFX9-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr addrspace(1) [[B]], align 4
+; GFX9-NEXT: [[TMP3:%.*]] = fmul contract <4 x float> [[TMP1]], [[TMP2]]
+; GFX9-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
+; GFX9-NEXT: [[S0:%.*]] = fadd contract float [[ACC]], [[TMP4]]
+; GFX9-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
+; GFX9-NEXT: [[S1:%.*]] = fadd contract float [[S0]], [[TMP5]]
+; GFX9-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
+; GFX9-NEXT: [[S2:%.*]] = fadd contract float [[S1]], [[TMP6]]
+; GFX9-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
+; GFX9-NEXT: [[S3:%.*]] = fadd contract float [[S2]], [[TMP7]]
+; GFX9-NEXT: ret float [[S3]]
+;
+; GFX1030-LABEL: define float @dot_i16_window(
+; GFX1030-SAME: ptr addrspace(1) [[A:%.*]], ptr addrspace(1) [[B:%.*]], float [[ACC:%.*]]) {
+; GFX1030-NEXT: [[ENTRY:.*:]]
+; GFX1030-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr addrspace(1) [[A]], align 2
+; GFX1030-NEXT: [[TMP1:%.*]] = sitofp <4 x i16> [[TMP0]] to <4 x float>
+; GFX1030-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr addrspace(1) [[B]], align 4
+; GFX1030-NEXT: [[TMP3:%.*]] = fmul contract <4 x float> [[TMP1]], [[TMP2]]
+; GFX1030-NEXT: [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i64 0
+; GFX1030-NEXT: [[S0:%.*]] = fadd contract float [[ACC]], [[TMP4]]
+; GFX1030-NEXT: [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i64 1
+; GFX1030-NEXT: [[S1:%.*]] = fadd contract float [[S0]], [[TMP5]]
+; GFX1030-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i64 2
+; GFX1030-NEXT: [[S2:%.*]] = fadd contract float [[S1]], [[TMP6]]
+; GFX1030-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
+; GFX1030-NEXT: [[S3:%.*]] = fadd contract float [[S2]], [[TMP7]]
+; GFX1030-NEXT: ret float [[S3]]
+;
+; GFX1250-LABEL: define float @dot_i16_window(
+; GFX1250-SAME: ptr addrspace(1) [[A:%.*]], ptr addrspace(1) [[B:%.*]], float [[ACC:%.*]]) {
+; GFX1250-NEXT: [[ENTRY:.*:]]
+; GFX1250-NEXT: [[A1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[A]], i64 2
+; GFX1250-NEXT: [[A2:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[A]], i64 4
+; GFX1250-NEXT: [[A3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[A]], i64 6
+; GFX1250-NEXT: [[B1:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[B]], i64 4
+; GFX1250-NEXT: [[B2:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[B]], i64 8
+; GFX1250-NEXT: [[B3:%.*]] = getelementptr inbounds nuw i8, ptr addrspace(1) [[B]], i64 12
+; GFX1250-NEXT: [[I0:%.*]] = load i16, ptr addrspace(1) [[A]], align 2
+; GFX1250-NEXT: [[I1:%.*]] = load i16, ptr addrspace(1) [[A1]], align 2
+; GFX1250-NEXT: [[I2:%.*]] = load i16, ptr addrspace(1) [[A2]], align 2
+; GFX1250-NEXT: [[I3:%.*]] = load i16, ptr addrspace(1) [[A3]], align 2
+; GFX1250-NEXT: [[F0:%.*]] = sitofp i16 [[I0]] to float
+; GFX1250-NEXT: [[F1:%.*]] = sitofp i16 [[I1]] to float
+; GFX1250-NEXT: [[F2:%.*]] = sitofp i16 [[I2]] to float
+; GFX1250-NEXT: [[F3:%.*]] = sitofp i16 [[I3]] to float
+; GFX1250-NEXT: [[W0:%.*]] = load float, ptr addrspace(1) [[B]], align 4
+; GFX1250-NEXT: [[W1:%.*]] = load float, ptr addrspace(1) [[B1]], align 4
+; GFX1250-NEXT: [[W2:%.*]] = load float, ptr addrspace(1) [[B2]], align 4
+; GFX1250-NEXT: [[W3:%.*]] = load float, ptr addrspace(1) [[B3]], align 4
+; GFX1250-NEXT: [[M0:%.*]] = fmul contract float [[F0]], [[W0]]
+; GFX1250-NEXT: [[M1:%.*]] = fmul contract float [[F1]], [[W1]]
+; GFX1250-NEXT: [[M2:%.*]] = fmul contract float [[F2]], [[W2]]
+; GFX1250-NEXT: [[M3:%.*]] = fmul contract float [[F3]], [[W3]]
+; GFX1250-NEXT: [[S0:%.*]] = fadd contract float [[ACC]], [[M0]]
+; GFX1250-NEXT: [[S1:%.*]] = fadd contract float [[S0]], [[M1]]
+; GFX1250-NEXT: [[S2:%.*]] = fadd contract float [[S1]], [[M2]]
+; GFX1250-NEXT: [[S3:%.*]] = fadd contract float [[S2]], [[M3]]
+; GFX1250-NEXT: ret float [[S3]]
;
entry:
%a1 = getelementptr inbounds nuw i8, ptr addrspace(1) %a, i64 2
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll
index 6a7a93a44f8c9..a25409530b4bb 100644
--- a/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/ordered-reduction-fma-fusion.ll
@@ -8,44 +8,44 @@
define float @conv_contract(ptr addrspace(1) %input, ptr addrspace(4) %mask) {
; CHECK-LABEL: @conv_contract(
-; CHECK-NEXT: [[IP0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT:%.*]], i64 0
-; CHECK-NEXT: [[MP0:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK:%.*]], i64 0
-; CHECK-NEXT: [[IP4:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 4
+; CHECK-NEXT: [[IP4:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT:%.*]], i64 0
; CHECK-NEXT: [[IV4:%.*]] = load float, ptr addrspace(1) [[IP4]], align 4
-; CHECK-NEXT: [[IP5:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 8
+; CHECK-NEXT: [[MP1:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK:%.*]], i64 0
+; CHECK-NEXT: [[MV0:%.*]] = load float, ptr addrspace(4) [[MP1]], align 4
+; CHECK-NEXT: [[PROD0:%.*]] = fmul contract float [[IV4]], [[MV0]]
+; CHECK-NEXT: [[IP0:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 1
+; CHECK-NEXT: [[MP0:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK]], i64 1
+; CHECK-NEXT: [[IP6:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 8
+; CHECK-NEXT: [[IP5:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 12
; CHECK-NEXT: [[IV5:%.*]] = load float, ptr addrspace(1) [[IP5]], align 4
-; CHECK-NEXT: [[IP6:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 9
-; CHECK-NEXT: [[IP8:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 11
-; CHECK-NEXT: [[IP10:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 16
-; CHECK-NEXT: [[IP12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 18
-; CHECK-NEXT: [[IP14:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 20
+; CHECK-NEXT: [[IP14:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 16
; CHECK-NEXT: [[IV14:%.*]] = load float, ptr addrspace(1) [[IP14]], align 4
-; CHECK-NEXT: [[IP15:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 24
-; CHECK-NEXT: [[IV15:%.*]] = load float, ptr addrspace(1) [[IP15]], align 4
+; CHECK-NEXT: [[IP8:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 17
+; CHECK-NEXT: [[IP10:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 19
+; CHECK-NEXT: [[IP12:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 24
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr addrspace(1) [[IP0]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr addrspace(1) [[IP6]], align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr addrspace(1) [[IP6]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr addrspace(1) [[IP8]], align 4
; CHECK-NEXT: [[TMP4:%.*]] = load <2 x float>, ptr addrspace(1) [[IP10]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load <2 x float>, ptr addrspace(1) [[IP12]], align 4
; CHECK-NEXT: [[TMP6:%.*]] = load <16 x float>, ptr addrspace(4) [[MP0]], align 4
-; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x float> poison, float [[IV4]], i64 4
-; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x float> [[TMP7]], float [[IV5]], i64 5
-; CHECK-NEXT: [[TMP22:%.*]] = insertelement <16 x float> [[TMP8]], float [[IV14]], i64 14
-; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x float> [[TMP22]], float [[IV15]], i64 15
+; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x float> poison, float [[IV5]], i64 8
+; CHECK-NEXT: [[TMP23:%.*]] = insertelement <16 x float> [[TMP7]], float [[IV14]], i64 9
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <16 x float> [[TMP23]], <16 x float> [[TMP11]], <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <16 x float> [[TMP12]], <16 x float> [[TMP13]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: [[TMP25:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
-; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <16 x float> [[TMP24]], <16 x float> [[TMP25]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <16 x float> [[TMP12]], <16 x float> [[TMP13]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <2 x float> [[TMP3]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP18:%.*]] = shufflevector <16 x float> [[TMP16]], <16 x float> [[TMP17]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 16, i32 17, i32 12, i32 13, i32 14, i32 15>
-; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x float> [[TMP5]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <16 x float> [[TMP18]], <16 x float> [[TMP19]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 14, i32 15>
-; CHECK-NEXT: [[TMP21:%.*]] = fmul contract <16 x float> [[TMP20]], [[TMP6]]
+; CHECK-NEXT: [[TMP22:%.*]] = shufflevector <2 x float> [[TMP5]], <2 x float> poison, <16 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <16 x float> [[TMP20]], <16 x float> [[TMP22]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17>
+; CHECK-NEXT: [[TMP21:%.*]] = fmul contract <16 x float> [[TMP24]], [[TMP6]]
; CHECK-NEXT: [[ACC14:%.*]] = extractelement <16 x float> [[TMP21]], i64 0
+; CHECK-NEXT: [[ACC1:%.*]] = fadd contract float [[PROD0]], [[ACC14]]
; CHECK-NEXT: [[PROD15:%.*]] = extractelement <16 x float> [[TMP21]], i64 1
-; CHECK-NEXT: [[ACC15:%.*]] = fadd contract float [[ACC14]], [[PROD15]]
+; CHECK-NEXT: [[ACC15:%.*]] = fadd contract float [[ACC1]], [[PROD15]]
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <16 x float> [[TMP21]], i64 2
; CHECK-NEXT: [[ACC16:%.*]] = fadd contract float [[ACC15]], [[TMP9]]
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <16 x float> [[TMP21]], i64 3
@@ -74,15 +74,22 @@ define float @conv_contract(ptr addrspace(1) %input, ptr addrspace(4) %mask) {
; CHECK-NEXT: [[ACC25:%.*]] = fadd contract float [[ACC13]], [[TMP36]]
; CHECK-NEXT: [[TMP37:%.*]] = extractelement <16 x float> [[TMP21]], i64 15
; CHECK-NEXT: [[ACC26:%.*]] = fadd contract float [[ACC25]], [[TMP37]]
-; CHECK-NEXT: [[IP16:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[INPUT]], i64 25
-; CHECK-NEXT: [[MP16:%.*]] = getelementptr inbounds float, ptr addrspace(4) [[MASK]], i64 1...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/228902
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