[llvm-branch-commits] [llvm] CodeGen: Prefer getting the Triple from the Module (PR #228682)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Oct 3 01:55:48 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-spir-v
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
Continue replacing TargetMachine::getTargetTriple() with the module's
triple at sites where a Module is one hop away through an available
Function, GlobalValue or MachineModuleInfo.
Where the surrounding class already holds a Subtarget, use its triple
rather than routing through the Module.
Co-authored-by: Claude Opus 5 <noreply@<!-- -->anthropic.com>
---
Full diff: https://github.com/llvm/llvm-project/pull/228682.diff
20 Files Affected:
- (modified) llvm/lib/CodeGen/InsertCodePrefetch.cpp (+1-1)
- (modified) llvm/lib/CodeGen/TailDuplicator.cpp (+6-3)
- (modified) llvm/lib/CodeGen/TargetInstrInfo.cpp (+1-1)
- (modified) llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (+4-4)
- (modified) llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64FrameLowering.cpp (+1-2)
- (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64MCInstLower.cpp (+1-1)
- (modified) llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp (+2-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/ARMAsmPrinter.cpp (+1-1)
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+6-6)
- (modified) llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp (+2-2)
- (modified) llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp (+1-1)
- (modified) llvm/lib/Target/X86/X86IndirectThunks.cpp (+1-1)
``````````diff
diff --git a/llvm/lib/CodeGen/InsertCodePrefetch.cpp b/llvm/lib/CodeGen/InsertCodePrefetch.cpp
index d6db34aed9b42..2ea21ab0a0348 100644
--- a/llvm/lib/CodeGen/InsertCodePrefetch.cpp
+++ b/llvm/lib/CodeGen/InsertCodePrefetch.cpp
@@ -104,8 +104,8 @@ static bool
insertPrefetchHints(MachineFunction &MF,
const SmallVector<PrefetchHint> &PrefetchHints) {
bool PrefetchInserted = false;
- bool IsELF = MF.getTarget().getTargetTriple().isOSBinFormatELF();
const Module *M = MF.getFunction().getParent();
+ bool IsELF = M->getTargetTriple().isOSBinFormatELF();
DenseMap<UniqueBBID, SmallVector<PrefetchHint>> PrefetchHintsBySiteBBID;
for (const auto &H : PrefetchHints)
PrefetchHintsBySiteBBID[H.SiteID.BBID].push_back(H);
diff --git a/llvm/lib/CodeGen/TailDuplicator.cpp b/llvm/lib/CodeGen/TailDuplicator.cpp
index 3572cd8a3ac17..fadeb391fcabb 100644
--- a/llvm/lib/CodeGen/TailDuplicator.cpp
+++ b/llvm/lib/CodeGen/TailDuplicator.cpp
@@ -627,9 +627,12 @@ bool TailDuplicator::shouldTailDuplicate(bool IsSimple,
// unwind info emission can't handle multiple prologue setups. In case of
// DWARF, allow them be duplicated, so that their existence doesn't prevent
// tail duplication of some basic blocks, that would be duplicated otherwise.
- if (MI.isNotDuplicable() &&
- (TailBB.getParent()->getTarget().getTargetTriple().isOSDarwin() ||
- !MI.isCFIInstruction()))
+ if (MI.isNotDuplicable() && (TailBB.getParent()
+ ->getFunction()
+ .getParent()
+ ->getTargetTriple()
+ .isOSDarwin() ||
+ !MI.isCFIInstruction()))
return false;
// Convergent instructions can be duplicated only if doing so doesn't add
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 92fc628e888e5..bf65f0bba8dc1 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -480,7 +480,7 @@ TargetInstrInfo::duplicate(MachineBasicBlock &MBB,
// CFI instructions are marked as non-duplicable, because Darwin compact
// unwind info emission can't handle multiple prologue setups.
assert((!Orig.isNotDuplicable() ||
- (!MF.getTarget().getTargetTriple().isOSDarwin() &&
+ (!MF.getFunction().getParent()->getTargetTriple().isOSDarwin() &&
Orig.isCFIInstruction())) &&
"Instruction cannot be duplicated");
diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
index 7d82d05db7aed..bb5d5d84ec5dc 100644
--- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
@@ -858,7 +858,7 @@ static MCSection *selectExplicitSectionGlobal(const GlobalObject *GO,
// Infer section flags from the section name if we can.
Kind = getELFKindForNamedSection(SectionName, Kind);
- unsigned Flags = getELFSectionFlags(Kind, TM.getTargetTriple());
+ unsigned Flags = getELFSectionFlags(Kind, GO->getParent()->getTargetTriple());
auto [Group, IsComdat, ExtraFlags, Type, EntrySize] =
getGlobalObjectInfo(GO, TM, SectionName, Kind);
Flags |= ExtraFlags;
@@ -963,7 +963,7 @@ static MCSection *selectELFSectionForGlobal(
MCSection *TargetLoweringObjectFileELF::SelectSectionForGlobal(
const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
- unsigned Flags = getELFSectionFlags(Kind, TM.getTargetTriple());
+ unsigned Flags = getELFSectionFlags(Kind, GO->getParent()->getTargetTriple());
// If we have -ffunction-section or -fdata-section then we should emit the
// global value to a uniqued section specifically for it.
@@ -983,7 +983,7 @@ MCSection *TargetLoweringObjectFileELF::SelectSectionForGlobal(
MCSection *TargetLoweringObjectFileELF::getUniqueSectionForFunction(
const Function &F, const TargetMachine &TM) const {
SectionKind Kind = SectionKind::getText();
- unsigned Flags = getELFSectionFlags(Kind, TM.getTargetTriple());
+ unsigned Flags = getELFSectionFlags(Kind, F.getParent()->getTargetTriple());
// If the function's section names is pre-determined via pragma or a
// section attribute, call selectExplicitSectionGlobal.
if (F.hasSection())
@@ -2127,7 +2127,7 @@ MCSection *TargetLoweringObjectFileCOFF::getStaticDtorSection(
const MCExpr *TargetLoweringObjectFileCOFF::lowerRelativeReference(
const GlobalValue *LHS, const GlobalValue *RHS, int64_t Addend,
std::optional<int64_t> PCRelativeOffset, const TargetMachine &TM) const {
- const Triple &T = TM.getTargetTriple();
+ const Triple &T = LHS->getParent()->getTargetTriple();
if (T.isOSCygMing())
return nullptr;
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 51acae3a76388..b26362491eab9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -638,7 +638,7 @@ void AArch64AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
auto &O = *OutStreamer;
MCSymbol *CurSled = OutContext.createTempSymbol("xray_sled_", true);
O.emitLabel(CurSled);
- bool MachO = TM.getTargetTriple().isOSBinFormatMachO();
+ bool MachO = MMI->getModule()->getTargetTriple().isOSBinFormatMachO();
auto *Sym = MCSymbolRefExpr::create(
OutContext.getOrCreateSymbol(
Twine(MachO ? "_" : "") +
diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
index d816c4285a87d..5f0a5cd971461 100644
--- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -631,8 +631,7 @@ bool AArch64FrameLowering::hasFPImpl(const MachineFunction &MF) const {
/// Should the Frame Pointer be reserved for the current function?
bool AArch64FrameLowering::isFPReserved(const MachineFunction &MF) const {
- const TargetMachine &TM = MF.getTarget();
- const Triple &TT = TM.getTargetTriple();
+ const Triple &TT = MF.getFunction().getParent()->getTargetTriple();
// These OSes require the frame chain is valid, even if the current frame does
// not use a frame pointer.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9885dfc854d11..c5ec4146fd94e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -10227,7 +10227,7 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization(
// cannot rely on the linker replacing the tail call with a return.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
const GlobalValue *GV = G->getGlobal();
- const Triple &TT = getTargetMachine().getTargetTriple();
+ const Triple &TT = GV->getParent()->getTargetTriple();
if (GV->hasExternalWeakLinkage() &&
(!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 885b27677f786..485ba3ffd82d3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -10412,7 +10412,7 @@ enum MachineOutlinerMBBFlags {
/// gets the small FRAME encoding, and costs one extra instruction.
static bool isCompactUnwindFrameRecordEnabled(const MachineFunction &MF) {
return UseCompactUnwindFrameRecordForOutlinedFunctions &&
- MF.getTarget().getTargetTriple().isOSBinFormatMachO();
+ MF.getFunction().getParent()->getTargetTriple().isOSBinFormatMachO();
}
/// Return true if the outlined function in \p MBB should save FP and LR as a
diff --git a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
index b3f0e1121ce76..159539f1486bf 100644
--- a/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MCInstLower.cpp
@@ -45,7 +45,7 @@ AArch64MCInstLower::GetGlobalAddressSymbol(const MachineOperand &MO) const {
MCSymbol *AArch64MCInstLower::GetGlobalValueSymbol(const GlobalValue *GV,
unsigned TargetFlags) const {
- const Triple &TheTriple = Printer.TM.getTargetTriple();
+ const Triple &TheTriple = GV->getParent()->getTargetTriple();
if (!TheTriple.isOSBinFormatCOFF())
return Printer.getSymbolPreferLocal(*GV);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 488f0d948635b..fb04a78704f02 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -1098,7 +1098,7 @@ bool AArch64CallLowering::isEligibleForTailCallOptimization(
// cannot rely on the linker replacing the tail call with a return.
if (Info.Callee.isGlobal()) {
const GlobalValue *GV = Info.Callee.getGlobal();
- const Triple &TT = MF.getTarget().getTargetTriple();
+ const Triple &TT = GV->getParent()->getTargetTriple();
if (GV->hasExternalWeakLinkage() &&
(!TT.isOSWindows() || TT.isOSBinFormatELF() ||
TT.isOSBinFormatMachO())) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 21adf311c3355..b6012edef8721 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1750,7 +1750,7 @@ bool AMDGPUInstructionSelector::selectRelocConstant(MachineInstr &I) const {
}
bool AMDGPUInstructionSelector::selectGroupStaticSize(MachineInstr &I) const {
- Triple::OSType OS = MF->getTarget().getTargetTriple().getOS();
+ Triple::OSType OS = STI.getTargetTriple().getOS();
Register DstReg = I.getOperand(0).getReg();
const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp
index 146fbc1e12268..428ec9610ceb6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp
@@ -22,7 +22,7 @@ using namespace llvm;
AMDGPUMachineModuleInfo::AMDGPUMachineModuleInfo(const MachineModuleInfo &MMI)
: MachineModuleInfoELF(MMI) {
LLVMContext &CTX = MMI.getModule()->getContext();
- const Triple &TT = MMI.getTarget().getTargetTriple();
+ const Triple &TT = MMI.getModule()->getTargetTriple();
auto InsertScope = [&](AtomicScope Scope, bool OneAS) {
return CTX.getOrInsertSyncScopeID(
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
index 584e41bfd5461..867581b5825cc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.cpp
@@ -20,7 +20,8 @@ using namespace llvm;
MCSection *AMDGPUTargetObjectFile::SelectSectionForGlobal(
const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {
if (Kind.isReadOnly() && AMDGPU::isReadOnlySegment(GO) &&
- AMDGPU::shouldEmitConstantsToTextSection(TM.getTargetTriple()))
+ AMDGPU::shouldEmitConstantsToTextSection(
+ GO->getParent()->getTargetTriple()))
return TextSection;
return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index 9662be4530f78..5bdae548ce6dc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -107,7 +107,7 @@ static bool dependsOnLocalPhi(const Loop *L, const Value *Cond,
AMDGPUTTIImpl::AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
: BaseT(TM, F.getDataLayout()),
- TargetTriple(TM->getTargetTriple()),
+ TargetTriple(F.getParent()->getTargetTriple()),
ST(static_cast<const GCNSubtarget *>(TM->getSubtargetImpl(F))),
TLI(ST->getTargetLowering()) {}
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 4012992d3f1d6..8e06bf17f0fe7 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8721,7 +8721,7 @@ unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
}
bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
- const Triple &TT = getTargetMachine().getTargetTriple();
+ const Triple &TT = GV->getParent()->getTargetTriple();
return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
AMDGPU::shouldEmitConstantsToTextSection(TT);
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 0ab4311d01c4a..9bbd029495a79 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -929,7 +929,7 @@ static uint8_t getModifierSpecifier(ARMCP::ARMCPModifier Modifier) {
MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
unsigned char TargetFlags) {
- const Triple &TT = TM.getTargetTriple();
+ const Triple &TT = GV->getParent()->getTargetTriple();
if (TT.isOSBinFormatMachO()) {
bool IsIndirect =
(TargetFlags & ARMII::MO_NONLAZY) && getTM().isGVIndirectSymbol(GV);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9dfbef53ca1bd..7df759ca74e76 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -2842,7 +2842,7 @@ bool ARMTargetLowering::IsEligibleForTailCallOptimization(
// cannot rely on the linker replacing the tail call with a return.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
const GlobalValue *GV = G->getGlobal();
- const Triple &TT = getTargetMachine().getTargetTriple();
+ const Triple &TT = GV->getParent()->getTargetTriple();
if (GV->hasExternalWeakLinkage() &&
(!TT.isOSWindows() || TT.isOSBinFormatELF() ||
TT.isOSBinFormatMachO())) {
@@ -3326,7 +3326,7 @@ SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
SDValue
ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
SelectionDAG &DAG) const {
- assert(getTargetMachine().getTargetTriple().isOSDarwin() &&
+ assert(Subtarget->getTargetTriple().isOSDarwin() &&
"This function expects a Darwin target");
SDLoc DL(Op);
@@ -3370,7 +3370,7 @@ ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
SDValue
ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
SelectionDAG &DAG) const {
- assert(getTargetMachine().getTargetTriple().isOSWindows() &&
+ assert(Subtarget->getTargetTriple().isOSWindows() &&
"Windows specific TLS lowering");
SDValue Chain = DAG.getEntryNode();
@@ -3773,7 +3773,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
SelectionDAG &DAG) const {
- assert(getTargetMachine().getTargetTriple().isOSWindows() &&
+ assert(Subtarget->getTargetTriple().isOSWindows() &&
"non-Windows COFF is not supported");
assert(Subtarget->useMovt() &&
"Windows on ARM expects to use movw/movt");
@@ -11715,7 +11715,7 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
DebugLoc DL = MI.getDebugLoc();
- assert(TM.getTargetTriple().isOSWindows() &&
+ assert(Subtarget->getTargetTriple().isOSWindows() &&
"__chkstk is only supported on Windows");
assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
@@ -21060,7 +21060,7 @@ SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {
SDValue
ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
- assert(getTM().getTargetTriple().isOSWindows() &&
+ assert(Subtarget->getTargetTriple().isOSWindows() &&
"unsupported target platform");
SDLoc DL(Op);
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
index 186bfa185e135..4fa4edfc3caab 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -203,8 +203,8 @@ NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &MF.getSubtarget<NVPTXSubtarget>();
- Scopes = NVPTXScopes(MF.getFunction().getContext(),
- MF.getTarget().getTargetTriple());
+ Scopes =
+ NVPTXScopes(MF.getFunction().getContext(), Subtarget->getTargetTriple());
return SelectionDAGISel::runOnMachineFunction(MF);
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
index a0cd00a9deef3..aba549e6aec62 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPrepareFunctions.cpp
@@ -542,7 +542,7 @@ bool SPIRVPrepareFunctionsImpl::substituteIntrinsicCalls(Function *F) {
Changed = true;
break;
}
- if (TM.getTargetTriple().getVendor() == Triple::AMD ||
+ if (II->getModule()->getTargetTriple().getVendor() == Triple::AMD ||
any_of(SPVAllowUnknownIntrinsics, [II](auto &&Prefix) {
if (Prefix.empty())
return false;
diff --git a/llvm/lib/Target/X86/X86IndirectThunks.cpp b/llvm/lib/Target/X86/X86IndirectThunks.cpp
index adac7b3572e7c..db124cbcac4bd 100644
--- a/llvm/lib/Target/X86/X86IndirectThunks.cpp
+++ b/llvm/lib/Target/X86/X86IndirectThunks.cpp
@@ -125,7 +125,7 @@ bool RetpolineThunkInserter::insertThunks(MachineModuleInfo &MMI,
}
void RetpolineThunkInserter::populateThunk(MachineFunction &MF) {
- bool Is64Bit = MF.getTarget().getTargetTriple().isX86_64();
+ bool Is64Bit = MF.getFunction().getParent()->getTargetTriple().isX86_64();
Register ThunkReg;
if (Is64Bit) {
assert(MF.getName() == "__llvm_retpoline_r11" &&
``````````
</details>
https://github.com/llvm/llvm-project/pull/228682
More information about the llvm-branch-commits
mailing list