[llvm-branch-commits] [llvm] [InlineSpiller][AMDGPU] Implement subreg reload during RA spill (PR #175002)

[via llvm-branch-commits]

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@@ -1248,18 +1249,62 @@ void InlineSpiller::spillAroundUses(Register Reg) {
 
     // Create a new virtual register for spill/fill.
     // FIXME: Infer regclass from instruction alone.
-    Register NewVReg = Edit->createFrom(Reg);
+
+    unsigned SubReg = 0;
+    LaneBitmask CoveringLanes = LaneBitmask::getNone();
+    // If the subreg liveness is enabled, identify the subreg use(s) to try
+    // subreg reload. Skip if the instruction also defines the register.
+    // For copy bundles, get the covering lane masks.
+    if (MRI.subRegLivenessEnabled() && !RI.Writes) {
+      for (auto [MI, OpIdx] : Ops) {
+        const MachineOperand &MO = MI->getOperand(OpIdx);
+        assert(MO.isReg() && MO.getReg() == Reg);
+        if (MO.isUse()) {
+          SubReg = MO.getSubReg();
+          if (SubReg)
+            CoveringLanes |= TRI.getSubRegIndexLaneMask(SubReg);
+        }
+      }
+    }
+
+    if (MI.isBundled() && CoveringLanes.any()) {
+      CoveringLanes = LaneBitmask(bit_ceil(CoveringLanes.getAsInteger()) - 1);
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easyonaadit wrote:

> I believe this goes against how LaneBitmask are supposed to be used.
> 
> https://github.com/llvm/llvm-project/blob/c991fdd4bc26d601d5637a79a4f300d03cc77cb3/llvm/include/llvm/MC/LaneBitmask.h#L17
> 
> "The individual bits in a lane mask can't be assigne any specific meaning."
> 
> Unless I'm missing something you cannot bump the lane mask to the full binary mask and expect to get a valid (complete) subreg.

Removed the hacky LaneBitmask manipulations.

https://github.com/llvm/llvm-project/pull/175002