[llvm-branch-commits] [TableGen] Generate `getRegClassFromMatchKind()` for AsmMatchers (PR #200453)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/utils/TableGen/AsmMatcherEmitter.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 98f7f4b6e..f608d4d37 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1394,7 +1394,6 @@ static MatchClassKind remapRegClassByHwMode(MatchClassKind Kind, bool Purecap) {
   }
 }
 
-
 unsigned RISCVAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
                                                     unsigned _Kind) {
   // Convert to enum for improved debugger output.

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https://github.com/llvm/llvm-project/pull/200453