[llvm-branch-commits] [llvm] [AMDGPU][True16] Add legalization/selection handling for G_MERGE_VALUES of 2 s16 -> s32 (PR #200082)

[Petar Avramovic via llvm-branch-commits]

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@@ -706,7 +706,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
       .Any({{DivBRC, BRC}, {{}, {}, ApplyAllVgpr}});
 
   addRulesForGOpcs({G_MERGE_VALUES, G_CONCAT_VECTORS})
+      .Any({{UniBRC, S16}, {{}, {}, VerifyAllSgpr}})
       .Any({{UniBRC, BRC}, {{}, {}, VerifyAllSgpr}})
+      .Any({{DivBRC, S16}, {{}, {}, ApplyAllVgpr}})
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petar-avramovic wrote:

need end to end ll test that will use       `.Any({{DivBRC, S16}, {{}, {}, ApplyAllVgpr}})` so s16 vgpr G_MERGE_VALUES

for example this will hit it
```
define amdgpu_ps i48 @test(<3 x i16> %src0, <3 x i16> %src1) {
  %not.src1 = xor <3 x i16> %src1, <i16 -1, i16 -1, i16 -1>
  %and = and <3 x i16> %src0, %not.src1
  %cast = bitcast <3 x i16> %and to i48
  ret i48 %cast
}
```
that v_andn2_v3i16 does not.
instselect test is fine since you actually do something there

https://github.com/llvm/llvm-project/pull/200082