[llvm-branch-commits] [llvm] [AMDGPU][True16] Legalize extloads into 16-bit registers (PR #198670)

[Petar Avramovic via llvm-branch-commits]

================
@@ -464,8 +464,12 @@ static bool isLoadStoreSizeLegal(const GCNSubtarget &ST,
     MemSize = std::max(MemSize, Align);
 #endif
 
-  // Only 1-byte and 2-byte to 32-bit extloads are valid.
-  if (MemSize != RegSize && RegSize != 32)
+  // We want to allow extending loads into up to a 32-bit destination register.
+  // However, this would potentially allow 16-bit destinations even without
+  // True16. This function is used by isLoadStoreLegal, which will also call
+  // isRegisterType on the destination register type which will disallow
+  // 16-bit types without True16, so this is safe.
----------------
petar-avramovic wrote:

Not sure about this comment, too big, there are only few cases (s8->s32 s8->s16 and s16->s32). This it would be much clearer to have in Legalizer info, something like
```
    Actions.legalForTypesWithMemDesc(!ST.useRealTrue16Insts(),
                                     {{S32, GlobalPtr, S8, GlobalAlign8},

    Actions.legalForTypesWithMemDesc(ST.useRealTrue16Insts(),
                                     {{S16, GlobalPtr, S8, GlobalAlign8},
```
instead of having to chase it in around for conditions.

https://github.com/llvm/llvm-project/pull/198670