[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)

[Jay Foad via llvm-branch-commits]

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@@ -927,6 +927,7 @@ supported for the ``amdgcn`` target.
      *reserved for downstream use (LLPC)*  12
      *reserved for future use*             13
      *reserved for future use*             14
+     Barrier                               15              N/A         N/A              32      0
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jayfoad wrote:

Hardware defines 0 as a special "null-like" barrier ID. None of the barrier global variables that you define will get ID 0, they will all get "real" IDs starting from 1.

https://github.com/llvm/llvm-project/pull/195613