[llvm-branch-commits] [mlir] [MLIR][SPIRV] Enable strict property assembly format (PR #196282)
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Thu May 7 03:58:47 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mlir
Author: Mehdi Amini (joker-eph)
<details>
<summary>Changes</summary>
Enable strict property assembly format mode for SPIR-V and add property dictionaries to declarative formats that still carry inherent attributes outside explicit operands or clauses.
Refresh ARM graph and TOSA tests so GraphConstant uses prop-dict spelling for its inherent constant identifier.
Assisted-by: Codex
---
Full diff: https://github.com/llvm/llvm-project/pull/196282.diff
8 Files Affected:
- (modified) mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td (+1)
- (modified) mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td (+1-1)
- (modified) mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td (+1-1)
- (modified) mlir/test/Dialect/SPIRV/IR/graph-ops.mlir (+3-3)
- (modified) mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir (+6-6)
- (modified) mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir (+1-1)
- (modified) mlir/test/Target/SPIRV/graph-ops.mlir (+2-2)
- (modified) mlir/test/Target/SPIRV/tosa-ops.mlir (+1-1)
``````````diff
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
index b33a84d093fb9..7ba41873c36f9 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td
@@ -52,6 +52,7 @@ def SPIRV_Dialect : Dialect {
let hasOperationAttrVerify = 1;
let hasRegionArgAttrVerify = 1;
let hasRegionResultAttrVerify = 1;
+ let useStrictPropertiesInAssemblyFormat = 1;
let extraClassDeclaration = [{
void registerAttributes();
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
index e7c314cb9acb9..d55fa93f4f4b0 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td
@@ -237,7 +237,7 @@ def SPIRV_FunctionCallOp : SPIRV_Op<"FunctionCall", [
let autogenSerialization = 0;
let assemblyFormat = [{
- $callee `(` $arguments `)` attr-dict `:`
+ $callee `(` $arguments `)` prop-dict attr-dict `:`
functional-type($arguments, results)
}];
}
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
index d8012749131d6..b63a7813c44bb 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGraphOps.td
@@ -151,7 +151,7 @@ def SPIRV_GraphConstantARMOp : SPIRV_GraphARMOp<"GraphConstant", [InGraphScope,
let autogenSerialization = 0;
let assemblyFormat = [{
- attr-dict `:` type($output)
+ prop-dict attr-dict `:` type($output)
}];
}
diff --git a/mlir/test/Dialect/SPIRV/IR/graph-ops.mlir b/mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
index 798147df45a34..b8b2146a7e91f 100644
--- a/mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/graph-ops.mlir
@@ -18,8 +18,8 @@ spirv.ARM.Graph @graphAndOutputs(%arg0: !spirv.arm.tensor<14x19xi16>) -> !spirv.
// CHECK: spirv.ARM.Graph {{@.*}}() -> !spirv.arm.tensor<2x3xi16> {
spirv.ARM.Graph @graphConstant() -> !spirv.arm.tensor<2x3xi16> {
- // CHECK: [[CONST:%.*]] = spirv.ARM.GraphConstant {graph_constant_id = 42 : i32} : !spirv.arm.tensor<2x3xi16>
- %0 = spirv.ARM.GraphConstant { graph_constant_id = 42 : i32 } : !spirv.arm.tensor<2x3xi16>
+ // CHECK: [[CONST:%.*]] = spirv.ARM.GraphConstant <{graph_constant_id = 42 : i32}> : !spirv.arm.tensor<2x3xi16>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 42 : i32}> : !spirv.arm.tensor<2x3xi16>
// CHECK: spirv.ARM.GraphOutputs [[CONST:%.*]] : !spirv.arm.tensor<2x3xi16>
spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<2x3xi16>
}
@@ -63,7 +63,7 @@ spirv.ARM.Graph @graphNoOutputs(%arg0: !spirv.arm.tensor<14x19xi16>) -> () {
//===----------------------------------------------------------------------===//
// expected-error @+1 {{'spirv.ARM.GraphConstant' op failed to verify that op must appear in a spirv.ARM.Graph op's block}}
-%0 = spirv.ARM.GraphConstant { graph_constant_id = 42 : i32 } : !spirv.arm.tensor<2x3xi16>
+%0 = spirv.ARM.GraphConstant <{graph_constant_id = 42 : i32}> : !spirv.arm.tensor<2x3xi16>
// -----
//===----------------------------------------------------------------------===//
diff --git a/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir b/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
index ca15b69303361..079829b376099 100644
--- a/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/tosa-ops-verification.mlir
@@ -1604,42 +1604,42 @@ spirv.ARM.Graph @sub_output_shape_does_not_match_broadcast_shape(%arg0: !spirv.a
//===----------------------------------------------------------------------===//
spirv.ARM.Graph @table_input_and_table_must_have_same_element_type(%arg0: !spirv.arm.tensor<3x2x15x7xi8>) -> (!spirv.arm.tensor<3x2x15x7xi8>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<256xi16>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<256xi16>
// expected-error @+1 {{op failed to verify that all of {input1, table} have same element type}}
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<256xi16> -> !spirv.arm.tensor<3x2x15x7xi8>
spirv.ARM.GraphOutputs %1 : !spirv.arm.tensor<3x2x15x7xi8>
}
spirv.ARM.Graph @table_input_output_shapes_must_match(%arg0: !spirv.arm.tensor<3x2x15x7xi8>) -> (!spirv.arm.tensor<3x2x15x6xi8>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<256xi8>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<256xi8>
// expected-error @+1 {{op failed to verify that all of {input1, output} have same shape}}
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<256xi8> -> !spirv.arm.tensor<3x2x15x6xi8>
spirv.ARM.GraphOutputs %1 : !spirv.arm.tensor<3x2x15x6xi8>
}
spirv.ARM.Graph @table_input_with_element_type_i8_requires_a_table_of_size_256(%arg0: !spirv.arm.tensor<3x2x15x7xi8>) -> (!spirv.arm.tensor<3x2x15x7xi8>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<513xi8>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<513xi8>
// expected-error @+1 {{op failed to verify that table must have size 256 if input1 has element type 8-bit signless integer}}
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<513xi8> -> !spirv.arm.tensor<3x2x15x7xi8>
spirv.ARM.GraphOutputs %1 : !spirv.arm.tensor<3x2x15x7xi8>
}
spirv.ARM.Graph @table_input_with_element_type_i16_requires_a_table_of_size_513(%arg0: !spirv.arm.tensor<3x2x15x7xi16>) -> (!spirv.arm.tensor<3x2x15x7xi32>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<256xi16>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<256xi16>
// expected-error @+1 {{op failed to verify that table must have size 513 if input1 has element type 16-bit signless integer}}
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi16>, !spirv.arm.tensor<256xi16> -> !spirv.arm.tensor<3x2x15x7xi32>
spirv.ARM.GraphOutputs %1 : !spirv.arm.tensor<3x2x15x7xi32>
}
spirv.ARM.Graph @table_input_with_element_type_i8_requires_an_output_with_element_type_i8(%arg0: !spirv.arm.tensor<3x2x15x7xi8>) -> (!spirv.arm.tensor<3x2x15x7xi32>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<256xi8>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<256xi8>
// expected-error @+1 {{op failed to verify that if input1 has type 8-bit signless integer then output must have a type in [8-bit signless integer]}}
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<256xi8> -> !spirv.arm.tensor<3x2x15x7xi32>
spirv.ARM.GraphOutputs %1 : !spirv.arm.tensor<3x2x15x7xi32>
}
spirv.ARM.Graph @table_input_with_element_type_i16_requires_an_output_with_element_type_i32(%arg0: !spirv.arm.tensor<3x2x15x7xi16>) -> (!spirv.arm.tensor<3x2x15x7xi8>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<513xi16>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<513xi16>
// expected-error @+1 {{op failed to verify that if input1 has type 16-bit signless integer then output must have a type in [32-bit signless integer]}}
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi16>, !spirv.arm.tensor<513xi16> -> !spirv.arm.tensor<3x2x15x7xi8>
spirv.ARM.GraphOutputs %1 : !spirv.arm.tensor<3x2x15x7xi8>
diff --git a/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir b/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
index e1fcf2e3ec051..e0ef6077e4f61 100644
--- a/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
+++ b/mlir/test/Dialect/SPIRV/IR/tosa-ops.mlir
@@ -523,7 +523,7 @@ spirv.ARM.Graph @sub_fp(%arg0: !spirv.arm.tensor<1x10x13x12xf16>, %arg1: !spirv.
//===----------------------------------------------------------------------===//
spirv.ARM.Graph @table_int(%arg0: !spirv.arm.tensor<3x2x15x7xi8>) -> (!spirv.arm.tensor<3x2x15x7xi8>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<256xi8>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<256xi8>
// CHECK: {{%.*}} = spirv.Tosa.Table %arg0, {{%.*}} : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<256xi8> -> !spirv.arm.tensor<3x2x15x7xi8>
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<256xi8> -> !spirv.arm.tensor<3x2x15x7xi8>
// CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<3x2x15x7xi8>
diff --git a/mlir/test/Target/SPIRV/graph-ops.mlir b/mlir/test/Target/SPIRV/graph-ops.mlir
index c956157bfa6c1..1515051e69b67 100644
--- a/mlir/test/Target/SPIRV/graph-ops.mlir
+++ b/mlir/test/Target/SPIRV/graph-ops.mlir
@@ -11,8 +11,8 @@ spirv.module Logical Vulkan requires #spirv.vce<v1.3, [VulkanMemoryModel, Shader
spirv.ARM.GraphEntryPoint @main, @main_arg_0, @main_res_0
// CHECK: spirv.ARM.Graph [[GN]]({{%.*}}: !spirv.arm.tensor<14x19xi16>) -> !spirv.arm.tensor<2x3xi16> attributes {entry_point = true} {
spirv.ARM.Graph @main(%arg0 : !spirv.arm.tensor<14x19xi16>) -> !spirv.arm.tensor<2x3xi16> attributes {entry_point = true} {
- // CHECK: [[CONST2:%.*]] = spirv.ARM.GraphConstant {graph_constant_id = 42 : i32} : !spirv.arm.tensor<2x3xi16>
- %0 = spirv.ARM.GraphConstant { graph_constant_id = 42 : i32 } : !spirv.arm.tensor<2x3xi16>
+ // CHECK: [[CONST2:%.*]] = spirv.ARM.GraphConstant <{graph_constant_id = 42 : i32}> : !spirv.arm.tensor<2x3xi16>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 42 : i32}> : !spirv.arm.tensor<2x3xi16>
// CHECK: spirv.ARM.GraphOutputs [[OUT:%.*]] : !spirv.arm.tensor<2x3xi16>
spirv.ARM.GraphOutputs %0 : !spirv.arm.tensor<2x3xi16>
}
diff --git a/mlir/test/Target/SPIRV/tosa-ops.mlir b/mlir/test/Target/SPIRV/tosa-ops.mlir
index 47e819636e982..c6edc44fb1903 100644
--- a/mlir/test/Target/SPIRV/tosa-ops.mlir
+++ b/mlir/test/Target/SPIRV/tosa-ops.mlir
@@ -926,7 +926,7 @@ spirv.module Logical Vulkan requires #spirv.vce<v1.3, [VulkanMemoryModel, Shader
spirv.GlobalVariable @table_int_res_0 bind(1, 0) : !spirv.ptr<!spirv.arm.tensor<3x2x15x7xi8>, UniformConstant>
spirv.ARM.GraphEntryPoint @table_int, @table_int_arg_0, @table_int_res_0
spirv.ARM.Graph @table_int(%arg0: !spirv.arm.tensor<3x2x15x7xi8>) -> (!spirv.arm.tensor<3x2x15x7xi8>) {
- %0 = spirv.ARM.GraphConstant {graph_constant_id = 0 : i32} : !spirv.arm.tensor<256xi8>
+ %0 = spirv.ARM.GraphConstant <{graph_constant_id = 0 : i32}> : !spirv.arm.tensor<256xi8>
// CHECK: {{%.*}} = spirv.Tosa.Table %arg0, {{%.*}} : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<256xi8> -> !spirv.arm.tensor<3x2x15x7xi8>
%1 = spirv.Tosa.Table %arg0, %0 : !spirv.arm.tensor<3x2x15x7xi8>, !spirv.arm.tensor<256xi8> -> !spirv.arm.tensor<3x2x15x7xi8>
// CHECK: spirv.ARM.GraphOutputs {{%.*}} : !spirv.arm.tensor<3x2x15x7xi8>
``````````
</details>
https://github.com/llvm/llvm-project/pull/196282
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