[llvm-branch-commits] [llvm] [LV] Use isLegalMaskedLoadOrStore for interleaved accesses too (NFC) (PR #195243)

[Gaëtan Bossu via llvm-branch-commits]

https://github.com/gbossu created https://github.com/llvm/llvm-project/pull/195243

isLegalMaskedLoadOrStore is now the central place for querying target capabilities for masked accesses. Access pattern legality checks are hoisted outside of it.

>From 455140b42ed24eec3f79053ff19b4a12aeb769c4 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ga=C3=ABtan=20Bossu?= <gaetan.bossu at arm.com>
Date: Fri, 1 May 2026 09:18:45 +0000
Subject: [PATCH] [LV] Use isLegalMaskedLoadOrStore for interleaved accesses
 too (NFC)

isLegalMaskedLoadOrStore is now the central place for querying target
capabilities for masked accesses. Access pattern legality checks are
hoisted outside of it.
---
 .../Transforms/Vectorize/LoopVectorizationPlanner.cpp  |  4 ----
 llvm/lib/Transforms/Vectorize/LoopVectorize.cpp        | 10 ++++------
 2 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
index 5bd035fc40774..5663518dbd2cf 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.cpp
@@ -62,14 +62,10 @@ static cl::opt<bool> ForceTargetSupportsMaskedMemoryOps(
 bool VFSelectionContext::isLegalMaskedLoadOrStore(
     Instruction *I, ElementCount VF) const {
   assert(isa<LoadInst>(I) || isa<StoreInst>(I));
-  auto *Ptr = getLoadStorePointerOperand(I);
   auto *Ty = getLoadStoreType(I);
   const unsigned AS = getLoadStoreAddressSpace(I);
   const Align Alignment = getLoadStoreAlignment(I);
 
-  if (!Legal->isConsecutivePtr(Ty, Ptr))
-    return false;
-
   return ForceTargetSupportsMaskedMemoryOps ||
          (isa<LoadInst>(I) ? TTI.isLegalMaskedLoad(Ty, Alignment, AS)
                            : TTI.isLegalMaskedStore(Ty, Alignment, AS));
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index e62955162fddb..906c8ddc43a07 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -2465,7 +2465,9 @@ bool LoopVectorizationCostModel::isScalarWithPredication(Instruction *I,
     return getCallWideningDecision(cast<CallInst>(I), VF).Kind == CM_Scalarize;
   case Instruction::Load:
   case Instruction::Store: {
-    return !Config.isLegalMaskedLoadOrStore(I, VF) &&
+    bool IsConsecutive = Legal->isConsecutivePtr(getLoadStoreType(I),
+                                                 getLoadStorePointerOperand(I));
+    return !(IsConsecutive && Config.isLegalMaskedLoadOrStore(I, VF)) &&
            !Config.isLegalGatherOrScatter(I, VF);
   }
   case Instruction::UDiv:
@@ -2689,11 +2691,7 @@ bool LoopVectorizationCostModel::interleavedAccessCanBeWidened(
   if (VF.isScalable() && NeedsMaskForGaps)
     return false;
 
-  auto *Ty = getLoadStoreType(I);
-  const Align Alignment = getLoadStoreAlignment(I);
-  unsigned AS = getLoadStoreAddressSpace(I);
-  return isa<LoadInst>(I) ? TTI.isLegalMaskedLoad(Ty, Alignment, AS)
-                          : TTI.isLegalMaskedStore(Ty, Alignment, AS);
+  return Config.isLegalMaskedLoadOrStore(I, VF);
 }
 
 bool LoopVectorizationCostModel::memoryInstructionCanBeWidened(