[llvm-branch-commits] [llvm] [AMDGPU][Scheduler] Use MIR-level rematerializer in rematerialization stage (PR #189491)

[Matt Arsenault via llvm-branch-commits]

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@@ -1527,36 +1486,68 @@ bool PreRARematStage::initGCNSchedStage() {
     PrintTargetRegions();
   });
 
-  // Collect all rematerializable registers in the function, then create a
-  // corresponding scored rematerialization candidate for each one.
-  if (!collectRematRegs(MIRegion)) {
+  // We need up-to-date live-out info. to query live-out register masks in
+  // regions containing rematerializable instructions.
+  DAG.RegionLiveOuts.buildLiveRegMap();
+
+  if (!Remater.analyze()) {
     REMAT_DEBUG(dbgs() << "No rematerializable registers\n");
     return false;
   }
   const ScoredRemat::FreqInfo FreqInfo(MF, DAG);
+
+  // Set of registers already marked for potential remterialization; used to
+  // avoid rematerialization chains.
+  SmallSet<Register, 4> MarkedRegs;
+  auto IsMarkedForRemat = [&MarkedRegs](const MachineOperand &MO) -> bool {
+    return MO.isReg() && MarkedRegs.contains(MO.getReg());
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arsenm wrote:

If you use all_uses you don't need the isReg check (at which point you can just inline the MarkedRegs.contains to the use point) 

https://github.com/llvm/llvm-project/pull/189491