[llvm-branch-commits] [llvm] [AMDGPU][Scheduler] Prepare remat stage for rematerializer integration (NFC) (PR #189489)

[Matt Arsenault via llvm-branch-commits]

================
@@ -2958,12 +2952,29 @@ PreRARematStage::ScoredRemat::FreqInfo::FreqInfo(
 }
 
 PreRARematStage::ScoredRemat::ScoredRemat(RematReg *Remat, const FreqInfo &Freq,
-                                          const GCNScheduleDAGMILive &DAG)
-    : Remat(Remat), FreqDiff(getFreqDiff(Freq)) {
-  RPSave.inc(Remat->getReg(), LaneBitmask::getNone(), Remat->Mask, DAG.MRI);
-}
+                                          GCNScheduleDAGMILive &DAG)
+    : Remat(Remat), LiveIn(DAG.Regions.size()), LiveOut(DAG.Regions.size()),
+      Live(DAG.Regions.size()), UnpredictableRPSave(DAG.Regions.size()) {
+  Register DefReg = Remat->getReg();
+
+  // Mark regions in which the rematerializable register is live.
+  for (unsigned I = 0, E = DAG.Regions.size(); I != E; ++I) {
+    auto LiveInIt = DAG.LiveIns[I].find(DefReg);
+    if (LiveInIt != DAG.LiveIns[I].end())
+      LiveIn.set(I);
+    const auto &LiveOuts = DAG.RegionLiveOuts.getLiveRegsForRegionIdx(I);
+    if (auto LiveOutIt = LiveOuts.find(DefReg); LiveOutIt != LiveOuts.end())
----------------
arsenm wrote:

is_contained?

https://github.com/llvm/llvm-project/pull/189489