[llvm-branch-commits] [llvm] d033ffe - [ARM] Regenerate vld2.ll test. NFC
Cullen Rhodes via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Mar 30 07:57:27 PDT 2026
Author: David Green
Date: 2026-03-30T14:57:18Z
New Revision: d033ffe4eeb403b2bb8e1217f8f0f76c89385c02
URL: https://github.com/llvm/llvm-project/commit/d033ffe4eeb403b2bb8e1217f8f0f76c89385c02
DIFF: https://github.com/llvm/llvm-project/commit/d033ffe4eeb403b2bb8e1217f8f0f76c89385c02.diff
LOG: [ARM] Regenerate vld2.ll test. NFC
(cherry picked from commit bcdb7d3c8f3fb554938185d1f286941651864664)
Added:
Modified:
llvm/test/CodeGen/ARM/vld2.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/vld2.ll b/llvm/test/CodeGen/ARM/vld2.ll
index 8d77684b67c90..5d8c020dc2608 100644
--- a/llvm/test/CodeGen/ARM/vld2.ll
+++ b/llvm/test/CodeGen/ARM/vld2.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
@@ -11,137 +12,203 @@
%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
-define <8 x i8> @vld2i8(ptr %A) nounwind {
-;CHECK-LABEL: vld2i8:
;Check the alignment value. Max for this instruction is 128 bits:
-;CHECK: vld2.8 {d16, d17}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr %A, i32 8)
- %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
- %tmp4 = add <8 x i8> %tmp2, %tmp3
- ret <8 x i8> %tmp4
+define <8 x i8> @vld2i8(ptr %A) nounwind {
+; CHECK-LABEL: vld2i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.8 {d16, d17}, [r0:64]
+; CHECK-NEXT: vadd.i8 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr %A, i32 8)
+ %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
+ %tmp4 = add <8 x i8> %tmp2, %tmp3
+ ret <8 x i8> %tmp4
}
-define <4 x i16> @vld2i16(ptr %A) nounwind {
-;CHECK-LABEL: vld2i16:
;Check the alignment value. Max for this instruction is 128 bits:
-;CHECK: vld2.16 {d16, d17}, [{{r[0-9]+|lr}}:128]
- %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr %A, i32 32)
- %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
- %tmp4 = add <4 x i16> %tmp2, %tmp3
- ret <4 x i16> %tmp4
+define <4 x i16> @vld2i16(ptr %A) nounwind {
+; CHECK-LABEL: vld2i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.16 {d16, d17}, [r0:128]
+; CHECK-NEXT: vadd.i16 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr %A, i32 32)
+ %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
+ %tmp4 = add <4 x i16> %tmp2, %tmp3
+ ret <4 x i16> %tmp4
}
define <2 x i32> @vld2i32(ptr %A) nounwind {
-;CHECK-LABEL: vld2i32:
-;CHECK: vld2.32
- %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
- %tmp4 = add <2 x i32> %tmp2, %tmp3
- ret <2 x i32> %tmp4
+; CHECK-LABEL: vld2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17}, [r0]
+; CHECK-NEXT: vadd.i32 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
+ %tmp4 = add <2 x i32> %tmp2, %tmp3
+ ret <2 x i32> %tmp4
}
define <2 x float> @vld2f(ptr %A) nounwind {
-;CHECK-LABEL: vld2f:
-;CHECK: vld2.32
- %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
- %tmp4 = fadd <2 x float> %tmp2, %tmp3
- ret <2 x float> %tmp4
+; CHECK-LABEL: vld2f:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17}, [r0]
+; CHECK-NEXT: vadd.f32 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
+ %tmp4 = fadd <2 x float> %tmp2, %tmp3
+ ret <2 x float> %tmp4
}
-;Check for a post-increment updating load.
+;Check for a post-increment updating load.
define <2 x float> @vld2f_update(ptr %ptr) nounwind {
-;CHECK-LABEL: vld2f_update:
-;CHECK: vld2.32 {d16, d17}, [{{r[0-9]+|lr}}]!
- %A = load ptr, ptr %ptr
- %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
- %tmp4 = fadd <2 x float> %tmp2, %tmp3
- %tmp5 = getelementptr float, ptr %A, i32 4
- store ptr %tmp5, ptr %ptr
- ret <2 x float> %tmp4
+; CHECK-LABEL: vld2f_update:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: ldr r3, [r0]
+; CHECK-NEXT: vld2.32 {d16, d17}, [r3]!
+; CHECK-NEXT: vadd.f32 d16, d16, d17
+; CHECK-NEXT: str r3, [r0]
+; CHECK-NEXT: vmov r2, r1, d16
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: mov pc, lr
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
+ %tmp4 = fadd <2 x float> %tmp2, %tmp3
+ %tmp5 = getelementptr float, ptr %A, i32 4
+ store ptr %tmp5, ptr %ptr
+ ret <2 x float> %tmp4
}
-define <1 x i64> @vld2i64(ptr %A) nounwind {
-;CHECK-LABEL: vld2i64:
;Check the alignment value. Max for this instruction is 128 bits:
-;CHECK: vld1.64 {d16, d17}, [{{r[0-9]+|lr}}:128]
- %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr %A, i32 32)
- %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
- %tmp4 = add <1 x i64> %tmp2, %tmp3
- ret <1 x i64> %tmp4
+define <1 x i64> @vld2i64(ptr %A) nounwind {
+; CHECK-LABEL: vld2i64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: vadd.i64 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr %A, i32 32)
+ %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
+ %tmp4 = add <1 x i64> %tmp2, %tmp3
+ ret <1 x i64> %tmp4
}
-define <16 x i8> @vld2Qi8(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
-;CHECK: vld2.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 8)
- %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
- %tmp4 = add <16 x i8> %tmp2, %tmp3
- ret <16 x i8> %tmp4
+define <16 x i8> @vld2Qi8(ptr %A) nounwind {
+; CHECK-LABEL: vld2Qi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.8 {d16, d17, d18, d19}, [r0:64]
+; CHECK-NEXT: vadd.i8 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 8)
+ %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
+ %tmp4 = add <16 x i8> %tmp2, %tmp3
+ ret <16 x i8> %tmp4
}
;Check for a post-increment updating load with register increment.
define <16 x i8> @vld2Qi8_update(ptr %ptr, i32 %inc) nounwind {
-;CHECK-LABEL: vld2Qi8_update:
-;CHECK: vld2.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128], r1
- %A = load ptr, ptr %ptr
- %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 16)
- %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
- %tmp4 = add <16 x i8> %tmp2, %tmp3
- %tmp5 = getelementptr i8, ptr %A, i32 %inc
- store ptr %tmp5, ptr %ptr
- ret <16 x i8> %tmp4
+; CHECK-LABEL: vld2Qi8_update:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: ldr lr, [r0]
+; CHECK-NEXT: vld2.8 {d16, d17, d18, d19}, [lr:128], r1
+; CHECK-NEXT: vadd.i8 q8, q8, q9
+; CHECK-NEXT: str lr, [r0]
+; CHECK-NEXT: vmov r12, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov r0, r12
+; CHECK-NEXT: pop {r11, lr}
+; CHECK-NEXT: mov pc, lr
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 16)
+ %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
+ %tmp4 = add <16 x i8> %tmp2, %tmp3
+ %tmp5 = getelementptr i8, ptr %A, i32 %inc
+ store ptr %tmp5, ptr %ptr
+ ret <16 x i8> %tmp4
}
-define <8 x i16> @vld2Qi16(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
-;CHECK: vld2.16 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128]
- %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr %A, i32 16)
- %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
- %tmp4 = add <8 x i16> %tmp2, %tmp3
- ret <8 x i16> %tmp4
+define <8 x i16> @vld2Qi16(ptr %A) nounwind {
+; CHECK-LABEL: vld2Qi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.16 {d16, d17, d18, d19}, [r0:128]
+; CHECK-NEXT: vadd.i16 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr %A, i32 16)
+ %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
+ %tmp4 = add <8 x i16> %tmp2, %tmp3
+ ret <8 x i16> %tmp4
}
-define <4 x i32> @vld2Qi32(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
-;CHECK: vld2.32 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]
- %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %A, i32 64)
- %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
- %tmp4 = add <4 x i32> %tmp2, %tmp3
- ret <4 x i32> %tmp4
+define <4 x i32> @vld2Qi32(ptr %A) nounwind {
+; CHECK-LABEL: vld2Qi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17, d18, d19}, [r0:256]
+; CHECK-NEXT: vadd.i32 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %A, i32 64)
+ %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
+ %tmp4 = add <4 x i32> %tmp2, %tmp3
+ ret <4 x i32> %tmp4
}
define <4 x float> @vld2Qf(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qf:
-;CHECK: vld2.32
- %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
- %tmp4 = fadd <4 x float> %tmp2, %tmp3
- ret <4 x float> %tmp4
+; CHECK-LABEL: vld2Qf:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17, d18, d19}, [r0]
+; CHECK-NEXT: vadd.f32 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
+ %tmp4 = fadd <4 x float> %tmp2, %tmp3
+ ret <4 x float> %tmp4
}
-declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr, i32) nounwind readonly
-
-declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr, i32) nounwind readonly
+; FIXME: Do not update with an invalid increment
+define ptr @test_or_update(ptr %p, ptr %q) {
+; CHECK-LABEL: test_or_update:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: orr r0, r0, #3
+; CHECK-NEXT: mov r2, #2
+; CHECK-NEXT: vld2.32 {d16, d17}, [r0], r2
+; CHECK-NEXT: vstr d16, [r1]
+; CHECK-NEXT: mov pc, lr
+ %p1 = ptrtoint ptr %p to i32
+ %p2 = or i32 %p1, 3
+ %p3 = inttoptr i32 %p2 to ptr
+ %l = load <4 x i32>, ptr %p3, align 1
+ %s = shufflevector <4 x i32> %l, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+ store <2 x i32> %s, ptr %q
+ %q1 = getelementptr i8, ptr %p, i32 2
+ ret ptr %q1
+}
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