[llvm-branch-commits] [llvm] release/22.x: [AArch64] Use an unknown size for memcpy ops with non-constant sizes. (#187445) (PR #187651)

[Cullen Rhodes via llvm-branch-commits]

https://github.com/c-rhodes updated https://github.com/llvm/llvm-project/pull/187651

>From 5f04300518b574249f116c5434d76590a1dcdf2a Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Fri, 20 Mar 2026 07:28:16 +0000
Subject: [PATCH] [AArch64] Use an unknown size for memcpy ops with
 non-constant sizes. (#187445)

The previous value of 0 was allowing loads to move past the mops
operations where it is not valid. Use a LocationSize::afterPointer()
size instead.

The GISel lowering currently loses the MMO, which is fine as it should
be conservatively treated as a load/store to any location.

(cherry picked from commit 441790b31f06ed2300e0e8d74f3bdf446bc105aa)
---
 .../AArch64/AArch64SelectionDAGInfo.cpp       |  8 +++---
 llvm/test/CodeGen/AArch64/mops-mmo-size.ll    | 28 +++++++++++++++++++
 2 files changed, 32 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/AArch64/mops-mmo-size.ll

diff --git a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
index df8ba2c8e922f..f236118fd6dce 100644
--- a/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
@@ -123,9 +123,9 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
                                           MachinePointerInfo SrcPtrInfo) const {
 
   // Get the constant size of the copy/set.
-  uint64_t ConstSize = 0;
+  LocationSize MemSize = LocationSize::afterPointer();
   if (auto *C = dyn_cast<ConstantSDNode>(Size))
-    ConstSize = C->getZExtValue();
+    MemSize = LocationSize::precise(C->getZExtValue());
 
   const bool IsSet = Opcode == AArch64::MOPSMemorySetPseudo ||
                      Opcode == AArch64::MOPSMemorySetTaggingPseudo;
@@ -136,7 +136,7 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
       isVolatile ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
   auto DstFlags = MachineMemOperand::MOStore | Vol;
   auto *DstOp =
-      MF.getMachineMemOperand(DstPtrInfo, DstFlags, ConstSize, Alignment);
+      MF.getMachineMemOperand(DstPtrInfo, DstFlags, MemSize, Alignment);
 
   if (IsSet) {
     // Extend value to i64, if required.
@@ -154,7 +154,7 @@ SDValue AArch64SelectionDAGInfo::EmitMOPS(unsigned Opcode, SelectionDAG &DAG,
 
     auto SrcFlags = MachineMemOperand::MOLoad | Vol;
     auto *SrcOp =
-        MF.getMachineMemOperand(SrcPtrInfo, SrcFlags, ConstSize, Alignment);
+        MF.getMachineMemOperand(SrcPtrInfo, SrcFlags, MemSize, Alignment);
     DAG.setNodeMemRefs(Node, {DstOp, SrcOp});
     return SDValue(Node, 3);
   }
diff --git a/llvm/test/CodeGen/AArch64/mops-mmo-size.ll b/llvm/test/CodeGen/AArch64/mops-mmo-size.ll
new file mode 100644
index 0000000000000..1d203c7cdb955
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/mops-mmo-size.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+mops -stop-after=aarch64-isel -o - %s  | FileCheck %s --check-prefix=CHECK-SD
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+mops -global-isel -stop-after=finalize-isel -o - %s  | FileCheck %s --check-prefix=CHECK-GI
+
+define void @test(ptr %out, ptr %in, i64 %a) {
+  ; CHECK-SD-LABEL: name: test
+  ; CHECK-SD: bb.0.entry:
+  ; CHECK-SD-NEXT:   liveins: $x0, $x1, $x2
+  ; CHECK-SD-NEXT: {{  $}}
+  ; CHECK-SD-NEXT:   [[COPY:%[0-9]+]]:gpr64 = COPY $x2
+  ; CHECK-SD-NEXT:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
+  ; CHECK-SD-NEXT:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
+  ; CHECK-SD-NEXT:   [[MOPSMemoryMovePseudo:%[0-9]+]]:gpr64common, [[MOPSMemoryMovePseudo1:%[0-9]+]]:gpr64common, [[MOPSMemoryMovePseudo2:%[0-9]+]]:gpr64 = MOPSMemoryMovePseudo [[COPY2]], [[COPY1]], [[COPY]], implicit-def dead $nzcv :: (store unknown-size into %ir.out, align 1), (load unknown-size from %ir.in, align 1)
+  ; CHECK-SD-NEXT:   RET_ReallyLR
+  ;
+  ; CHECK-GI-LABEL: name: test
+  ; CHECK-GI: bb.1.entry:
+  ; CHECK-GI-NEXT:   liveins: $x0, $x1, $x2
+  ; CHECK-GI-NEXT: {{  $}}
+  ; CHECK-GI-NEXT:   [[COPY:%[0-9]+]]:gpr64common = COPY $x0
+  ; CHECK-GI-NEXT:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
+  ; CHECK-GI-NEXT:   [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
+  ; CHECK-GI-NEXT:   [[MOPSMemoryMovePseudo:%[0-9]+]]:gpr64common, [[MOPSMemoryMovePseudo1:%[0-9]+]]:gpr64common, [[MOPSMemoryMovePseudo2:%[0-9]+]]:gpr64 = MOPSMemoryMovePseudo [[COPY]], [[COPY1]], [[COPY2]], implicit-def dead $nzcv
+  ; CHECK-GI-NEXT:   RET_ReallyLR
+entry:
+  call void @llvm.memmove.p0.p0.i64(ptr %out, ptr %in, i64 %a, i1 false)
+  ret void
+}