[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)

[via llvm-branch-commits]

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@@ -903,128 +904,175 @@ multiclass TLBITableBase {
 defm TLBI  : TLBITableBase;
 defm TLBIP : TLBITableBase;
 
-multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
-             bits<3> op2, int reguse = REG_REQUIRED> {
-  def : TLBIEntry<name, op1, crn, crm, op2, reguse>;
-  def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, reguse> {
-    let Encoding{7} = 1;
+class TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn,
+           bits<4> crm, bits<3> op2, int reguse = REG_REQUIRED> {
+  string Name = name;
+  bit HasTLBIP = hasTLBIP;
+  bits<3> Op1 = op1;
+  bits<4> CRn = crn;
+  bits<4> CRm = crm;
+  bits<3> Op2 = op2;
+  int RegUse = reguse;
+}
+
+// TLBI and TLBIP instructions encodings.
+defvar TLBIBase = [
+  //    name    hasTLBIP  op1    CRn     CRm     op2    reguse
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Lukacma wrote:

After proposed changes above, CRn field becomes unnecessary in all tables

https://github.com/llvm/llvm-project/pull/187400