[llvm-branch-commits] [llvm] release/22.x: [ARM] Fix incorrect post increment from Or (#188036) (PR #188466)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Mar 25 04:39:02 PDT 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-arm
Author: llvmbot
<details>
<summary>Changes</summary>
Backport bcdb7d3c8f3fb554938185d1f286941651864664 5012b76ae273790340283084a3d0de96aeb54866
Requested by: @<!-- -->davemgreen
---
Full diff: https://github.com/llvm/llvm-project/pull/188466.diff
2 Files Affected:
- (modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+17-15)
- (modified) llvm/test/CodeGen/ARM/vld2.ll (+166-100)
``````````diff
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 4fd845fbc07ac..d7c32d764a5fb 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -15997,25 +15997,27 @@ static SDValue CombineBaseUpdate(SDNode *N,
if (findPointerConstIncrement(Addr.getNode(), &Base, &CInc)) {
unsigned Offset =
getPointerConstIncrement(Addr->getOpcode(), Base, CInc, DCI.DAG);
- for (SDUse &Use : Base->uses()) {
+ if (Offset) {
+ for (SDUse &Use : Base->uses()) {
- SDNode *User = Use.getUser();
- if (Use.getResNo() != Base.getResNo() || User == Addr.getNode() ||
- User->getNumOperands() != 2)
- continue;
+ SDNode *User = Use.getUser();
+ if (Use.getResNo() != Base.getResNo() || User == Addr.getNode() ||
+ User->getNumOperands() != 2)
+ continue;
- SDValue UserInc = User->getOperand(Use.getOperandNo() == 0 ? 1 : 0);
- unsigned UserOffset =
- getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG);
+ SDValue UserInc = User->getOperand(Use.getOperandNo() == 0 ? 1 : 0);
+ unsigned UserOffset =
+ getPointerConstIncrement(User->getOpcode(), Base, UserInc, DCI.DAG);
- if (!UserOffset || UserOffset <= Offset)
- continue;
+ if (!UserOffset || UserOffset <= Offset)
+ continue;
- unsigned NewConstInc = UserOffset - Offset;
- SDValue NewInc = DCI.DAG.getConstant(NewConstInc, SDLoc(N), MVT::i32);
- BaseUpdates.push_back({User, NewInc, NewConstInc});
- if (BaseUpdates.size() >= MaxBaseUpdates)
- break;
+ unsigned NewConstInc = UserOffset - Offset;
+ SDValue NewInc = DCI.DAG.getConstant(NewConstInc, SDLoc(N), MVT::i32);
+ BaseUpdates.push_back({User, NewInc, NewConstInc});
+ if (BaseUpdates.size() >= MaxBaseUpdates)
+ break;
+ }
}
}
diff --git a/llvm/test/CodeGen/ARM/vld2.ll b/llvm/test/CodeGen/ARM/vld2.ll
index 8d77684b67c90..55615d52acb70 100644
--- a/llvm/test/CodeGen/ARM/vld2.ll
+++ b/llvm/test/CodeGen/ARM/vld2.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
@@ -11,137 +12,202 @@
%struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
-define <8 x i8> @vld2i8(ptr %A) nounwind {
-;CHECK-LABEL: vld2i8:
;Check the alignment value. Max for this instruction is 128 bits:
-;CHECK: vld2.8 {d16, d17}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr %A, i32 8)
- %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
- %tmp4 = add <8 x i8> %tmp2, %tmp3
- ret <8 x i8> %tmp4
+define <8 x i8> @vld2i8(ptr %A) nounwind {
+; CHECK-LABEL: vld2i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.8 {d16, d17}, [r0:64]
+; CHECK-NEXT: vadd.i8 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr %A, i32 8)
+ %tmp2 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp1, 1
+ %tmp4 = add <8 x i8> %tmp2, %tmp3
+ ret <8 x i8> %tmp4
}
-define <4 x i16> @vld2i16(ptr %A) nounwind {
-;CHECK-LABEL: vld2i16:
;Check the alignment value. Max for this instruction is 128 bits:
-;CHECK: vld2.16 {d16, d17}, [{{r[0-9]+|lr}}:128]
- %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr %A, i32 32)
- %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
- %tmp4 = add <4 x i16> %tmp2, %tmp3
- ret <4 x i16> %tmp4
+define <4 x i16> @vld2i16(ptr %A) nounwind {
+; CHECK-LABEL: vld2i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.16 {d16, d17}, [r0:128]
+; CHECK-NEXT: vadd.i16 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr %A, i32 32)
+ %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1
+ %tmp4 = add <4 x i16> %tmp2, %tmp3
+ ret <4 x i16> %tmp4
}
define <2 x i32> @vld2i32(ptr %A) nounwind {
-;CHECK-LABEL: vld2i32:
-;CHECK: vld2.32
- %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
- %tmp4 = add <2 x i32> %tmp2, %tmp3
- ret <2 x i32> %tmp4
+; CHECK-LABEL: vld2i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17}, [r0]
+; CHECK-NEXT: vadd.i32 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1
+ %tmp4 = add <2 x i32> %tmp2, %tmp3
+ ret <2 x i32> %tmp4
}
define <2 x float> @vld2f(ptr %A) nounwind {
-;CHECK-LABEL: vld2f:
-;CHECK: vld2.32
- %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
- %tmp4 = fadd <2 x float> %tmp2, %tmp3
- ret <2 x float> %tmp4
+; CHECK-LABEL: vld2f:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17}, [r0]
+; CHECK-NEXT: vadd.f32 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
+ %tmp4 = fadd <2 x float> %tmp2, %tmp3
+ ret <2 x float> %tmp4
}
-;Check for a post-increment updating load.
+;Check for a post-increment updating load.
define <2 x float> @vld2f_update(ptr %ptr) nounwind {
-;CHECK-LABEL: vld2f_update:
-;CHECK: vld2.32 {d16, d17}, [{{r[0-9]+|lr}}]!
- %A = load ptr, ptr %ptr
- %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
- %tmp4 = fadd <2 x float> %tmp2, %tmp3
- %tmp5 = getelementptr float, ptr %A, i32 4
- store ptr %tmp5, ptr %ptr
- ret <2 x float> %tmp4
+; CHECK-LABEL: vld2f_update:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: ldr r3, [r0]
+; CHECK-NEXT: vld2.32 {d16, d17}, [r3]!
+; CHECK-NEXT: vadd.f32 d16, d16, d17
+; CHECK-NEXT: str r3, [r0]
+; CHECK-NEXT: vmov r2, r1, d16
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: mov pc, lr
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1
+ %tmp4 = fadd <2 x float> %tmp2, %tmp3
+ %tmp5 = getelementptr float, ptr %A, i32 4
+ store ptr %tmp5, ptr %ptr
+ ret <2 x float> %tmp4
}
-define <1 x i64> @vld2i64(ptr %A) nounwind {
-;CHECK-LABEL: vld2i64:
;Check the alignment value. Max for this instruction is 128 bits:
-;CHECK: vld1.64 {d16, d17}, [{{r[0-9]+|lr}}:128]
- %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr %A, i32 32)
- %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
- %tmp4 = add <1 x i64> %tmp2, %tmp3
- ret <1 x i64> %tmp4
+define <1 x i64> @vld2i64(ptr %A) nounwind {
+; CHECK-LABEL: vld2i64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld1.64 {d16, d17}, [r0:128]
+; CHECK-NEXT: vadd.i64 d16, d16, d17
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr %A, i32 32)
+ %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1
+ %tmp4 = add <1 x i64> %tmp2, %tmp3
+ ret <1 x i64> %tmp4
}
-define <16 x i8> @vld2Qi8(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
-;CHECK: vld2.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:64]
- %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 8)
- %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
- %tmp4 = add <16 x i8> %tmp2, %tmp3
- ret <16 x i8> %tmp4
+define <16 x i8> @vld2Qi8(ptr %A) nounwind {
+; CHECK-LABEL: vld2Qi8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.8 {d16, d17, d18, d19}, [r0:64]
+; CHECK-NEXT: vadd.i8 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 8)
+ %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
+ %tmp4 = add <16 x i8> %tmp2, %tmp3
+ ret <16 x i8> %tmp4
}
;Check for a post-increment updating load with register increment.
define <16 x i8> @vld2Qi8_update(ptr %ptr, i32 %inc) nounwind {
-;CHECK-LABEL: vld2Qi8_update:
-;CHECK: vld2.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128], r1
- %A = load ptr, ptr %ptr
- %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 16)
- %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
- %tmp4 = add <16 x i8> %tmp2, %tmp3
- %tmp5 = getelementptr i8, ptr %A, i32 %inc
- store ptr %tmp5, ptr %ptr
- ret <16 x i8> %tmp4
+; CHECK-LABEL: vld2Qi8_update:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: ldr lr, [r0]
+; CHECK-NEXT: vld2.8 {d16, d17, d18, d19}, [lr:128], r1
+; CHECK-NEXT: vadd.i8 q8, q8, q9
+; CHECK-NEXT: str lr, [r0]
+; CHECK-NEXT: vmov r12, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov r0, r12
+; CHECK-NEXT: pop {r11, lr}
+; CHECK-NEXT: mov pc, lr
+ %A = load ptr, ptr %ptr
+ %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr %A, i32 16)
+ %tmp2 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int8x16x2_t %tmp1, 1
+ %tmp4 = add <16 x i8> %tmp2, %tmp3
+ %tmp5 = getelementptr i8, ptr %A, i32 %inc
+ store ptr %tmp5, ptr %ptr
+ ret <16 x i8> %tmp4
}
-define <8 x i16> @vld2Qi16(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
-;CHECK: vld2.16 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128]
- %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr %A, i32 16)
- %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
- %tmp4 = add <8 x i16> %tmp2, %tmp3
- ret <8 x i16> %tmp4
+define <8 x i16> @vld2Qi16(ptr %A) nounwind {
+; CHECK-LABEL: vld2Qi16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.16 {d16, d17, d18, d19}, [r0:128]
+; CHECK-NEXT: vadd.i16 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr %A, i32 16)
+ %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1
+ %tmp4 = add <8 x i16> %tmp2, %tmp3
+ ret <8 x i16> %tmp4
}
-define <4 x i32> @vld2Qi32(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
-;CHECK: vld2.32 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]
- %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %A, i32 64)
- %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
- %tmp4 = add <4 x i32> %tmp2, %tmp3
- ret <4 x i32> %tmp4
+define <4 x i32> @vld2Qi32(ptr %A) nounwind {
+; CHECK-LABEL: vld2Qi32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17, d18, d19}, [r0:256]
+; CHECK-NEXT: vadd.i32 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr %A, i32 64)
+ %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1
+ %tmp4 = add <4 x i32> %tmp2, %tmp3
+ ret <4 x i32> %tmp4
}
define <4 x float> @vld2Qf(ptr %A) nounwind {
-;CHECK-LABEL: vld2Qf:
-;CHECK: vld2.32
- %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr %A, i32 1)
- %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
- %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
- %tmp4 = fadd <4 x float> %tmp2, %tmp3
- ret <4 x float> %tmp4
+; CHECK-LABEL: vld2Qf:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vld2.32 {d16, d17, d18, d19}, [r0]
+; CHECK-NEXT: vadd.f32 q8, q8, q9
+; CHECK-NEXT: vmov r0, r1, d16
+; CHECK-NEXT: vmov r2, r3, d17
+; CHECK-NEXT: mov pc, lr
+ %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr %A, i32 1)
+ %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0
+ %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1
+ %tmp4 = fadd <4 x float> %tmp2, %tmp3
+ ret <4 x float> %tmp4
}
-declare %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64.p0(ptr, i32) nounwind readonly
-
-declare %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32.p0(ptr, i32) nounwind readonly
-declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32.p0(ptr, i32) nounwind readonly
+define ptr @test_or_update(ptr %p, ptr %q) {
+; CHECK-LABEL: test_or_update:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: orr r2, r0, #3
+; CHECK-NEXT: add r0, r0, #2
+; CHECK-NEXT: vld2.32 {d16, d17}, [r2]
+; CHECK-NEXT: vstr d16, [r1]
+; CHECK-NEXT: mov pc, lr
+ %p1 = ptrtoint ptr %p to i32
+ %p2 = or i32 %p1, 3
+ %p3 = inttoptr i32 %p2 to ptr
+ %l = load <4 x i32>, ptr %p3, align 1
+ %s = shufflevector <4 x i32> %l, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
+ store <2 x i32> %s, ptr %q
+ %q1 = getelementptr i8, ptr %p, i32 2
+ ret ptr %q1
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/188466
More information about the llvm-branch-commits
mailing list