[llvm-branch-commits] [llvm] [AArch64][llvm] Separate TLBI-only feature gating from TLBIP aliases (PR #187400)

[via llvm-branch-commits]

================
@@ -903,128 +903,250 @@ multiclass TLBITableBase {
 defm TLBI  : TLBITableBase;
 defm TLBIP : TLBITableBase;
 
-multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
-             bits<3> op2, int reguse = REG_REQUIRED> {
-  def : TLBIEntry<name, op1, crn, crm, op2, reguse>;
-  def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, reguse> {
+class TLBI<bit hasTLBIP, bits<3> op1, bits<4> crn,
----------------
Lukacma wrote:

This is unnecessary and leads to you having to duplicate register name twice. Firstly, when defining the record, the 2nd time when creating the iteration. I would implement it as just a nested list with comments on top to explain what each field does.

https://github.com/llvm/llvm-project/pull/187400