[llvm-branch-commits] [llvm] release/22.x: [PowerPC] Preserve load output chain in vcmpequb combine (#187010) (PR #187234)

[via llvm-branch-commits]

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/187234

Backport 7404a5dbe0ca971e0f312a366019361fc9d576e0

Requested by: @nikic

>From 57a50d6ae795cc8224a9441962f2bc06a64c3bef Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Wed, 18 Mar 2026 11:38:51 +0100
Subject: [PATCH] [PowerPC] Preserve load output chain in vcmpequb combine
 (#187010)

Replace uses of the old load output chain with the new load output
chain. A plain replacement here is fine because the transform verifies
the load is one-use.

Fixes https://github.com/llvm/llvm-project/issues/186549.

(cherry picked from commit 7404a5dbe0ca971e0f312a366019361fc9d576e0)
---
 llvm/lib/Target/PowerPC/PPCISelLowering.cpp   |  7 ++-
 .../CodeGen/PowerPC/load-i128-eq-chain.ll     | 47 +++++++++++++++++++
 2 files changed, 52 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/PowerPC/load-i128-eq-chain.ll

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 640082153e57d..f818cce380632 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -15644,8 +15644,11 @@ SDValue convertTwoLoadsAndCmpToVCMPEQUB(SelectionDAG &DAG, SDNode *N,
     assert(Operand.getOpcode() == ISD::LOAD && "Must be LoadSDNode here.");
 
     auto *LoadNode = cast<LoadSDNode>(Operand);
-    return DAG.getLoad(MVT::v16i8, DL, LoadNode->getChain(),
-                       LoadNode->getBasePtr(), LoadNode->getMemOperand());
+    SDValue NewLoad =
+        DAG.getLoad(MVT::v16i8, DL, LoadNode->getChain(),
+                    LoadNode->getBasePtr(), LoadNode->getMemOperand());
+    DAG.ReplaceAllUsesOfValueWith(Operand.getValue(1), NewLoad.getValue(1));
+    return NewLoad;
   };
 
   // Following code transforms the DAG
diff --git a/llvm/test/CodeGen/PowerPC/load-i128-eq-chain.ll b/llvm/test/CodeGen/PowerPC/load-i128-eq-chain.ll
new file mode 100644
index 0000000000000..6fc3e07cb21f5
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/load-i128-eq-chain.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=ppc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Make sure the loads happen after each call, not after both calls.
+define i1 @test() nounwind {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    stdu 1, -96(1)
+; CHECK-NEXT:    std 0, 112(1)
+; CHECK-NEXT:    std 30, 80(1) # 8-byte Folded Spill
+; CHECK-NEXT:    li 3, 64
+; CHECK-NEXT:    addi 30, 1, 48
+; CHECK-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
+; CHECK-NEXT:    mr 3, 30
+; CHECK-NEXT:    bl call
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    lxvd2x 63, 0, 30
+; CHECK-NEXT:    mr 3, 30
+; CHECK-NEXT:    bl call
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    lxvd2x 34, 0, 30
+; CHECK-NEXT:    li 4, 64
+; CHECK-NEXT:    ld 30, 80(1) # 8-byte Folded Reload
+; CHECK-NEXT:    vcmpequb. 2, 31, 2
+; CHECK-NEXT:    lxvd2x 63, 1, 4 # 16-byte Folded Reload
+; CHECK-NEXT:    mfocrf 3, 2
+; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
+; CHECK-NEXT:    addi 1, 1, 96
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+  %a1 = alloca [16 x i8], align 16
+  %a2 = alloca [16 x i8], align 16
+  call void @llvm.lifetime.start.p0(i64 16, ptr %a2)
+  call void @call(ptr %a2)
+  %l1 = load i128, ptr %a2, align 16
+  call void @llvm.lifetime.end.p0(i64 16, ptr %a2)
+  call void @llvm.lifetime.start.p0(i64 16, ptr %a1)
+  call void @call(ptr %a1)
+  %l2 = load i128, ptr %a1, align 16
+  call void @llvm.lifetime.end.p0(i64 16, ptr %a1)
+  %res = icmp eq i128 %l1, %l2
+  ret i1 %res
+}
+
+declare void @call(ptr)