[llvm-branch-commits] [llvm] [MIR] Support symbolic INLINEASM extra-info flags (PR #186818)
Ivan Kosarev via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Mar 17 02:18:14 PDT 2026
https://github.com/kosarev updated https://github.com/llvm/llvm-project/pull/186818
>From 286747cb98ed42088660ac79b9b4cccd5554dae9 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Mon, 16 Mar 2026 12:22:42 +0000
Subject: [PATCH] [MIR] Support symbolic INLINEASM extra-info flags
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 54 +++++++++++++++----
llvm/lib/CodeGen/MIRPrinter.cpp | 6 +++
llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir | 24 ++++-----
...ubreg-undef-def-with-other-subreg-defs.mir | 24 ++++-----
.../MIR/Generic/inline-asm-extra-info.mir | 38 ++++++-------
.../MIR/Generic/inline-asm-unknown-kind.mir | 11 ++++
6 files changed, 103 insertions(+), 54 deletions(-)
create mode 100644 llvm/test/CodeGen/MIR/Generic/inline-asm-unknown-kind.mir
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index c62cd50f4fd98..fdd8f490eb52f 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -461,7 +461,7 @@ class MIParser {
std::optional<unsigned> &TiedDefIdx,
bool IsDef = false);
bool parseImmediateOperand(MachineOperand &Dest);
- bool parseInlineAsmOperand(MachineOperand &Dest);
+ bool parseSymbolicInlineAsmOperand(unsigned OpIdx, MachineOperand &Dest);
bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue,
const Constant *&C);
bool parseIRConstant(StringRef::iterator Loc, const Constant *&C);
@@ -1903,9 +1903,42 @@ bool MIParser::parseImmediateOperand(MachineOperand &Dest) {
return false;
}
-bool MIParser::parseInlineAsmOperand(MachineOperand &Dest) {
+bool MIParser::parseSymbolicInlineAsmOperand(unsigned OpIdx,
+ MachineOperand &Dest) {
+ assert(OpIdx >= InlineAsm::MIOp_ExtraInfo);
+ assert(Token.is(MIToken::Identifier) &&
+ "expected symbolic inline asm operand");
+
+ // Parse ExtraInfo flags.
+ if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
+ unsigned ExtraInfo = 0;
+ for (;;) {
+ if (Token.isNot(MIToken::Identifier))
+ break;
+
+ StringRef FlagName = Token.stringValue();
+ unsigned Flag = StringSwitch<unsigned>(FlagName)
+ .Case("sideeffect", InlineAsm::Extra_HasSideEffects)
+ .Case("mayload", InlineAsm::Extra_MayLoad)
+ .Case("maystore", InlineAsm::Extra_MayStore)
+ .Case("isconvergent", InlineAsm::Extra_IsConvergent)
+ .Case("alignstack", InlineAsm::Extra_IsAlignStack)
+ .Case("unwind", InlineAsm::Extra_MayUnwind)
+ .Case("attdialect", 0)
+ .Case("inteldialect", InlineAsm::Extra_AsmDialect)
+ .Default(~0u);
+ if (Flag == ~0u)
+ return error("unknown inline asm extra info flag '" + FlagName + "'");
+
+ ExtraInfo |= Flag;
+ lex();
+ }
+
+ Dest = MachineOperand::CreateImm(ExtraInfo);
+ return false;
+ }
+
// Parse symbolic form: kind[:constraint].
- assert(Token.is(MIToken::Identifier) && "expected inline asm operand kind");
StringRef KindStr = Token.stringValue();
constexpr auto InvalidKind = static_cast<InlineAsm::Kind>(0);
InlineAsm::Kind K =
@@ -1917,7 +1950,8 @@ bool MIParser::parseInlineAsmOperand(MachineOperand &Dest) {
.Case("imm", InlineAsm::Kind::Imm)
.Case("mem", InlineAsm::Kind::Mem)
.Default(InvalidKind);
- assert(K != InvalidKind && "unknown inline asm operand kind");
+ if (K == InvalidKind)
+ return error("unknown inline asm operand kind '" + KindStr + "'");
lex();
@@ -3172,14 +3206,12 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
case MIToken::Error:
return true;
case MIToken::Identifier: {
+ bool IsInlineAsm = OpCode == TargetOpcode::INLINEASM ||
+ OpCode == TargetOpcode::INLINEASM_BR;
+ if (IsInlineAsm)
+ return parseSymbolicInlineAsmOperand(OpIdx, Dest);
+
StringRef Id = Token.stringValue();
- bool IsInlineAsmOperand = (OpCode == TargetOpcode::INLINEASM ||
- OpCode == TargetOpcode::INLINEASM_BR) &&
- OpIdx >= InlineAsm::MIOp_FirstOperand;
- if (IsInlineAsmOperand &&
- (Id == "regdef" || Id == "reguse" || Id == "regdef-ec" ||
- Id == "clobber" || Id == "imm" || Id == "mem"))
- return parseInlineAsmOperand(Dest);
if (const auto *RegMask = PFS.Target.getRegMask(Id)) {
Dest = MachineOperand::CreateRegMask(RegMask);
lex();
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 9de35f3309a8a..250b40863c9f3 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -975,6 +975,12 @@ static void printMIOperand(raw_ostream &OS, MFPrintState &State,
break;
}
if (PrintSymbolicInlineAsmOps && MI.isInlineAsm()) {
+ if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
+ unsigned ExtraInfo = Op.getImm();
+ interleave(InlineAsm::getExtraInfoNames(ExtraInfo), OS, " ");
+ break;
+ }
+
int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
if (FlagIdx >= 0 && (unsigned)FlagIdx == OpIdx) {
InlineAsm::Flag F(Op.getImm());
diff --git a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
index 77029d109a6be..14543fcf6ce88 100644
--- a/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
+++ b/llvm/test/CodeGen/AMDGPU/dst-sel-hazard.mir
@@ -370,7 +370,7 @@ body: |
; HAZARD-LABEL: name: inline_sdwa_hazard
; HAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; HAZARD-NEXT: {{ $}}
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_NOP 0
; HAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; HAZARD-NEXT: S_ENDPGM 0
@@ -378,10 +378,10 @@ body: |
; NOHAZARD-LABEL: name: inline_sdwa_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; NOHAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; NOHAZARD-NEXT: S_ENDPGM 0
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
S_ENDPGM 0
...
@@ -397,17 +397,17 @@ body: |
; HAZARD-NEXT: {{ $}}
; HAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
; HAZARD-NEXT: S_NOP 0
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_ENDPGM 0
;
; NOHAZARD-LABEL: name: sdwa_inline_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
; NOHAZARD-NEXT: renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; NOHAZARD-NEXT: S_ENDPGM 0
renamable $vgpr0 = V_ADD_U16_sdwa 0, $vgpr1, 0, $vgpr2, 0, 1, 0, 3, 3, implicit $exec, implicit killed $vgpr0(tied-def 0)
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
S_ENDPGM 0
...
@@ -421,19 +421,19 @@ body: |
; HAZARD-LABEL: name: inline_inline_hazard
; HAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; HAZARD-NEXT: {{ $}}
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_NOP 0
- ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; HAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; HAZARD-NEXT: S_ENDPGM 0
;
; NOHAZARD-LABEL: name: inline_inline_hazard
; NOHAZARD: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $exec, $mode
; NOHAZARD-NEXT: {{ $}}
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
- ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ ; NOHAZARD-NEXT: INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
; NOHAZARD-NEXT: S_ENDPGM 0
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
- INLINEASM &"v_or_b32 $0, 0, $1", 0 /* attdialect */, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
+ INLINEASM &"v_or_b32 $0, 0, $1", attdialect, regdef:VGPR_32, def $vgpr0, reguse:VGPR_32, $vgpr1
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
index b96907be2fa1d..e795751b57fb4 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
+++ b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
@@ -28,9 +28,9 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, regdef:VGPR_32, def [[V_MOV_B32_e32_]], reguse tiedto:$0, [[V_MOV_B32_e32_]](tied-def 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, reguse:VGPR_32, [[DS_READ_B32_gfx9_]]
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub0, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub1
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def [[V_MOV_B32_e32_]], reguse tiedto:$0, [[V_MOV_B32_e32_]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, [[DS_READ_B32_gfx9_]]
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub0, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
; CHECK-NEXT: S_BRANCH %bb.1
@@ -41,9 +41,9 @@ body: |
bb.1:
%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1114122 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1114121 /* reguse:VGPR_32 */, %2
- INLINEASM &"", 1 /* sideeffect attdialect */, 1114122 /* regdef:VGPR_32 */, def undef %0.sub0, 1114122 /* regdef:VGPR_32 */, def %0.sub1
+ INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def %0, reguse tiedto:$0, %0(tied-def 3)
+ INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, %2
+ INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def undef %0.sub0, regdef:VGPR_32, def %0.sub1
S_NOP 0, implicit %0.sub1
$sgpr10 = S_MOV_B32 -1
S_BRANCH %bb.1
@@ -69,9 +69,9 @@ body: |
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (load (s32), addrspace 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, regdef:VGPR_32, def [[V_MOV_B32_e32_]], reguse tiedto:$0, [[V_MOV_B32_e32_]](tied-def 3)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, reguse:VGPR_32, [[DS_READ_B32_gfx9_]]
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub1, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub0
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def [[V_MOV_B32_e32_]], reguse tiedto:$0, [[V_MOV_B32_e32_]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, [[DS_READ_B32_gfx9_]]
+ ; CHECK-NEXT: INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub1, regdef:VGPR_32, def undef [[V_MOV_B32_e32_]].sub0
; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1
; CHECK-NEXT: $sgpr10 = S_MOV_B32 -1
; CHECK-NEXT: S_BRANCH %bb.1
@@ -82,9 +82,9 @@ body: |
bb.1:
%2:vgpr_32 = DS_READ_B32_gfx9 %1, 0, 0, implicit $exec :: (load (s32), addrspace 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1114122 /* regdef:VGPR_32 */, def %0, 2147483657 /* reguse tiedto:$0 */, %0(tied-def 3)
- INLINEASM &"", 1 /* sideeffect attdialect */, 1114121 /* reguse:VGPR_32 */, %2
- INLINEASM &"", 1 /* sideeffect attdialect */, 1114122 /* regdef:VGPR_32 */, def %0.sub1, 1114122 /* regdef:VGPR_32 */, def undef %0.sub0
+ INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def %0, reguse tiedto:$0, %0(tied-def 3)
+ INLINEASM &"", sideeffect attdialect, reguse:VGPR_32, %2
+ INLINEASM &"", sideeffect attdialect, regdef:VGPR_32, def %0.sub1, regdef:VGPR_32, def undef %0.sub0
S_NOP 0, implicit %0.sub1
$sgpr10 = S_MOV_B32 -1
S_BRANCH %bb.1
diff --git a/llvm/test/CodeGen/MIR/Generic/inline-asm-extra-info.mir b/llvm/test/CodeGen/MIR/Generic/inline-asm-extra-info.mir
index 6318a397b58d9..3857198769f68 100644
--- a/llvm/test/CodeGen/MIR/Generic/inline-asm-extra-info.mir
+++ b/llvm/test/CodeGen/MIR/Generic/inline-asm-extra-info.mir
@@ -1,12 +1,12 @@
-# RUN: llc -run-pass=none -o - %s | FileCheck --match-full-lines %s
+# RUN: llc -run-pass=none -print-symbolic-inline-asm-ops -o - %s | FileCheck --match-full-lines %s
---
name: test_attdialect
body: |
bb.0:
; CHECK-LABEL: name: test_attdialect
- ; CHECK: INLINEASM &"", 0 /* attdialect */
- INLINEASM &"", 0
+ ; CHECK: INLINEASM &"", attdialect
+ INLINEASM &"", attdialect
...
---
@@ -14,8 +14,8 @@ name: test_sideeffect
body: |
bb.0:
; CHECK-LABEL: name: test_sideeffect
- ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
- INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", sideeffect attdialect
+ INLINEASM &"", sideeffect
...
---
@@ -23,8 +23,8 @@ name: test_alignstack
body: |
bb.0:
; CHECK-LABEL: name: test_alignstack
- ; CHECK: INLINEASM &"", 2 /* alignstack attdialect */
- INLINEASM &"", 2
+ ; CHECK: INLINEASM &"", alignstack attdialect
+ INLINEASM &"", alignstack
...
---
@@ -32,8 +32,8 @@ name: test_inteldialect
body: |
bb.0:
; CHECK-LABEL: name: test_inteldialect
- ; CHECK: INLINEASM &"", 4 /* inteldialect */
- INLINEASM &"", 4
+ ; CHECK: INLINEASM &"", inteldialect
+ INLINEASM &"", inteldialect
...
---
@@ -41,8 +41,8 @@ name: test_mayload
body: |
bb.0:
; CHECK-LABEL: name: test_mayload
- ; CHECK: INLINEASM &"", 8 /* mayload attdialect */
- INLINEASM &"", 8
+ ; CHECK: INLINEASM &"", mayload attdialect
+ INLINEASM &"", mayload
...
---
@@ -50,8 +50,8 @@ name: test_maystore
body: |
bb.0:
; CHECK-LABEL: name: test_maystore
- ; CHECK: INLINEASM &"", 16 /* maystore attdialect */
- INLINEASM &"", 16
+ ; CHECK: INLINEASM &"", maystore attdialect
+ INLINEASM &"", maystore
...
---
@@ -59,8 +59,8 @@ name: test_isconvergent
body: |
bb.0:
; CHECK-LABEL: name: test_isconvergent
- ; CHECK: INLINEASM &"", 32 /* isconvergent attdialect */
- INLINEASM &"", 32
+ ; CHECK: INLINEASM &"", isconvergent attdialect
+ INLINEASM &"", isconvergent
...
---
@@ -68,8 +68,8 @@ name: test_unwind
body: |
bb.0:
; CHECK-LABEL: name: test_unwind
- ; CHECK: INLINEASM &"", 64 /* unwind attdialect */
- INLINEASM &"", 64
+ ; CHECK: INLINEASM &"", unwind attdialect
+ INLINEASM &"", unwind
...
---
@@ -77,6 +77,6 @@ name: test_combined
body: |
bb.0:
; CHECK-LABEL: name: test_combined
- ; CHECK: INLINEASM &"", 13 /* sideeffect mayload inteldialect */
- INLINEASM &"", 13
+ ; CHECK: INLINEASM &"", sideeffect mayload inteldialect
+ INLINEASM &"", sideeffect mayload inteldialect
...
diff --git a/llvm/test/CodeGen/MIR/Generic/inline-asm-unknown-kind.mir b/llvm/test/CodeGen/MIR/Generic/inline-asm-unknown-kind.mir
new file mode 100644
index 0000000000000..7603dd23c44ad
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/Generic/inline-asm-unknown-kind.mir
@@ -0,0 +1,11 @@
+# RUN: not llc -run-pass=none -o - %s 2>&1 | FileCheck %s
+
+# Test error handling for unknown inline asm operand kind.
+
+---
+name: test_unknown_operand_kind
+body: |
+ bb.0:
+ ; CHECK: [[@LINE+1]]:32: unknown inline asm operand kind 'badkind'
+ INLINEASM &"", attdialect, badkind
+...
More information about the llvm-branch-commits
mailing list