[llvm-branch-commits] [llvm] [Draft][SPIRV] Lower load/store atomic to OpAtomicLoad/OpAtomicStore (PR #185696)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 3097a70cc..40ac75897 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -1664,8 +1664,8 @@ bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
   if (I.getNumMemOperands()) {
     const MachineMemOperand *MemOp = *I.memoperands_begin();
     if (MemOp->isAtomic()) {
-      uint32_t Scope = static_cast<uint32_t>(getMemScope(
-          Context, MemOp->getSyncScopeID()));
+      uint32_t Scope =
+          static_cast<uint32_t>(getMemScope(Context, MemOp->getSyncScopeID()));
       Register ScopeReg = buildI32Constant(Scope, I);
 
       AtomicOrdering AO = MemOp->getSuccessOrdering();
@@ -1673,11 +1673,11 @@ bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
       Register MemSemReg = buildI32Constant(MemSem, I);
 
       auto Load = MIRBuilder.buildInstr(SPIRV::OpAtomicLoad)
-          .addDef(ResVReg)
-          .addUse(GR.getSPIRVTypeID(ResType))
-          .addUse(Ptr)
-          .addUse(ScopeReg)
-          .addUse(MemSemReg);
+                      .addDef(ResVReg)
+                      .addUse(GR.getSPIRVTypeID(ResType))
+                      .addUse(Ptr)
+                      .addUse(ScopeReg)
+                      .addUse(MemSemReg);
       Load.constrainAllUses(TII, TRI, RBI);
       return true;
     }
@@ -1741,8 +1741,8 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
   if (I.getNumMemOperands()) {
     const MachineMemOperand *MemOp = *I.memoperands_begin();
     if (MemOp->isAtomic()) {
-      uint32_t Scope = static_cast<uint32_t>(getMemScope(
-          Context, MemOp->getSyncScopeID()));
+      uint32_t Scope =
+          static_cast<uint32_t>(getMemScope(Context, MemOp->getSyncScopeID()));
       Register ScopeReg = buildI32Constant(Scope, I);
 
       AtomicOrdering AO = MemOp->getSuccessOrdering();
@@ -1750,18 +1750,16 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
       Register MemSemReg = buildI32Constant(MemSem, I);
 
       auto Store = MIRBuilder.buildInstr(SPIRV::OpAtomicStore)
-          .addUse(Ptr)
-          .addUse(ScopeReg)
-          .addUse(MemSemReg)
-          .addUse(StoreVal);
+                       .addUse(Ptr)
+                       .addUse(ScopeReg)
+                       .addUse(MemSemReg)
+                       .addUse(StoreVal);
       Store.constrainAllUses(TII, TRI, RBI);
       return true;
     }
   }
 
-  auto MIB = MIRBuilder.buildInstr(SPIRV::OpStore)
-                 .addUse(Ptr)
-                 .addUse(StoreVal);
+  auto MIB = MIRBuilder.buildInstr(SPIRV::OpStore).addUse(Ptr).addUse(StoreVal);
   if (!I.getNumMemOperands()) {
     assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS ||
            I.getOpcode() ==

``````````

</details>


https://github.com/llvm/llvm-project/pull/185696