[llvm-branch-commits] [llvm] release/22.x: [AMDGPU] Ignore unused VALU src0/1/2 fields when disassembling (#175182) (PR #183313)
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llvm-branch-commits at lists.llvm.org
Mon Mar 9 02:50:46 PDT 2026
https://github.com/dyung updated https://github.com/llvm/llvm-project/pull/183313
>From fef02d48c08db859ef83f84232ed78bd9d1c323a Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 14 Jan 2026 16:27:22 +0000
Subject: [PATCH] [AMDGPU] Ignore unused VALU src0/1/2 fields when
disassembling (#175182)
This enables a future patch to change the default encoding of these
fields, which are mostly ignored by hardware.
(cherry picked from commit 8099e127cde22a5989515ce940eaa2a0a944d95e)
---
llvm/lib/Target/AMDGPU/VOP2Instructions.td | 24 +++---
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 6 +-
llvm/lib/Target/AMDGPU/VOPCInstructions.td | 10 +--
llvm/lib/Target/AMDGPU/VOPInstructions.td | 82 +++++++++----------
.../MC/Disassembler/AMDGPU/gfx10_vop1.txt | 3 +
.../Disassembler/AMDGPU/gfx11_dasm_vop1.txt | 3 +
.../gfx11_dasm_vop3_dpp16_from_vop1.txt | 4 +
.../AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt | 4 +
.../AMDGPU/gfx11_dasm_vop3_from_vop1.txt | 3 +
.../AMDGPU/gfx1250_dasm_vop3_from_vop1.txt | 3 +
.../Disassembler/AMDGPU/gfx12_dasm_vop3.txt | 3 +
.../gfx12_dasm_vop3_from_vop1_dpp16.txt | 4 +
.../AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt | 3 +-
.../test/MC/Disassembler/AMDGPU/gfx8_vop1.txt | 3 +
.../test/MC/Disassembler/AMDGPU/gfx8_vop3.txt | 3 +
.../MC/Disassembler/AMDGPU/gfx908_mai.txt | 8 ++
.../test/MC/Disassembler/AMDGPU/gfx9_vop1.txt | 3 +
.../test/MC/Disassembler/AMDGPU/gfx9_vop3.txt | 3 +
18 files changed, 110 insertions(+), 62 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 799bdb8b18c9c..2ccf39224a278 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -15,8 +15,8 @@ class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
bits<9> src0;
bits<8> src1;
- let Inst{8-0} = !if(P.HasSrc0, src0, 0);
- let Inst{16-9} = !if(P.HasSrc1, src1, 0);
+ let Inst{8-0} = !if(P.HasSrc0, src0, ?);
+ let Inst{16-9} = !if(P.HasSrc1, src1, ?);
let Inst{24-17} = !if(P.EmitDst, vdst, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0; //encoding
@@ -28,8 +28,8 @@ class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
bits<8> src1;
bits<32> imm;
- let Inst{8-0} = !if(P.HasSrc0, src0, 0);
- let Inst{16-9} = !if(P.HasSrc1, src1, 0);
+ let Inst{8-0} = !if(P.HasSrc0, src0, ?);
+ let Inst{16-9} = !if(P.HasSrc1, src1, ?);
let Inst{24-17} = !if(P.EmitDst, vdst, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0; // encoding
@@ -42,8 +42,8 @@ class VOP2_MADK64e <bits<6> op, VOPProfile P> : Enc96 {
bits<8> src1;
bits<64> imm;
- let Inst{8-0} = !if(P.HasSrc0, src0, 0);
- let Inst{16-9} = !if(P.HasSrc1, src1, 0);
+ let Inst{8-0} = !if(P.HasSrc0, src0, ?);
+ let Inst{16-9} = !if(P.HasSrc1, src1, ?);
let Inst{24-17} = !if(P.EmitDst, vdst, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0; // encoding
@@ -55,7 +55,7 @@ class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
bits<8> src1;
let Inst{8-0} = 0xf9; // sdwa
- let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
+ let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, ?);
let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0; // encoding
@@ -66,11 +66,11 @@ class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
bits<9> src1;
let Inst{8-0} = 0xf9; // sdwa
- let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
+ let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, ?);
let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0; // encoding
- let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
+ let Inst{63} = !if(P.HasSrc1, src1{8}, ?); // src1_sgpr
}
class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
@@ -1507,7 +1507,7 @@ class VOP2_DPP<bits<6> op, VOP2_DPP_Pseudo ps,
bits<8> vdst;
bits<8> src1;
let Inst{8-0} = 0xfa;
- let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);
+ let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, ?);
let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0;
@@ -1549,7 +1549,7 @@ class VOP2_DPP8<bits<6> op, VOP2_Pseudo ps,
bits<8> src1;
let Inst{8-0} = fi;
- let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, 0);
+ let Inst{16-9} = !if(p.HasSrc1, src1{7-0}, ?);
let Inst{24-17} = !if(p.EmitDst, vdst{7-0}, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0;
@@ -2351,7 +2351,7 @@ class VOP2_DPPe <bits<6> op, VOP2_DPP_Pseudo ps, VOPProfile P = ps.Pfl> :
bits<8> vdst;
bits<8> src1;
let Inst{8-0} = 0xfa; //dpp
- let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
+ let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, ?);
let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
let Inst{30-25} = op;
let Inst{31} = 0x0; //encoding
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 3ddf7a8a93824..a96d54a8210c3 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -2276,9 +2276,9 @@ class VOP3PX2e <bits<8> op, bits<8> LdScaleOp, VOP3PWMMA_Profile P> : Enc128, VO
let Inst{87-80} = op;
let Inst{95-88} = 0xcc; //encoding
- let Inst{104-96} = !if(P.HasSrc0, src0, 0);
- let Inst{113-105} = !if(P.HasSrc1, src1, 0);
- let Inst{122-114} = !if(P.HasSrc2, src2, 0);
+ let Inst{104-96} = !if(P.HasSrc0, src0, ?);
+ let Inst{113-105} = !if(P.HasSrc1, src1, ?);
+ let Inst{122-114} = !if(P.HasSrc2, src2, ?);
// neg_lo
let Inst{125} = !if(P.NegLo01, src0_modifiers{0}, 0);
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index c15bc0b66a0f4..95e40dd8e99d9 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -24,7 +24,7 @@ class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
bits<8> src1;
let Inst{8-0} = 0xf9; // sdwa
- let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
+ let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, ?);
let Inst{24-17} = op;
let Inst{31-25} = 0x3e; // encoding
}
@@ -33,10 +33,10 @@ class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
bits<9> src1;
let Inst{8-0} = 0xf9; // sdwa
- let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
+ let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, ?);
let Inst{24-17} = op;
let Inst{31-25} = 0x3e; // encoding
- let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
+ let Inst{63} = !if(P.HasSrc1, src1{8}, ?); // src1_sgpr
}
@@ -1460,7 +1460,7 @@ class VOPC_DPP_Base<bits<8> op, string OpName, VOPProfile P>
let Inst{8-0} = 0xfa;
- let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
+ let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, ?);
let Inst{48-40} = dpp_ctrl;
let Inst{50} = fi;
let Inst{51} = bound_ctrl;
@@ -1486,7 +1486,7 @@ class VOPC_DPP8_Base<bits<8> op, string OpName, VOPProfile P>
let Inst{8-0} = fi;
- let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, 0);
+ let Inst{39-32} = !if (P.HasSrc0, src0{7-0}, ?);
let Inst{63-40} = dpp8{23-0};
let AsmMatchConverter = "cvtDPP8";
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index 91aa754986bf0..6056cd22875a7 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -242,9 +242,9 @@ class VOP3a<VOPProfile P> : Enc64 {
let Inst{10} = !if(P.HasSrc2Mods, src2_modifiers{1}, 0);
let Inst{31-26} = 0x34; //encoding
- let Inst{40-32} = !if(P.HasSrc0, src0, 0);
- let Inst{49-41} = !if(P.HasSrc1, src1, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2, 0);
+ let Inst{40-32} = !if(P.HasSrc0, src0, ?);
+ let Inst{49-41} = !if(P.HasSrc1, src1, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2, ?);
let Inst{60-59} = !if(P.HasOMod, omod, 0);
let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
@@ -277,9 +277,9 @@ class VOP3a_t16<VOPProfile P> : Enc64 {
let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
let Inst{31-26} = 0x35;
- let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0);
- let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2{8-0}, 0);
+ let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, ?);
+ let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2{8-0}, ?);
let Inst{60-59} = !if(P.HasOMod, omod, 0);
let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
@@ -461,9 +461,9 @@ class VOP3be <VOPProfile P> : Enc64 {
let Inst{7-0} = vdst;
let Inst{14-8} = sdst;
let Inst{31-26} = 0x34; //encoding
- let Inst{40-32} = !if(P.HasSrc0, src0, 0);
- let Inst{49-41} = !if(P.HasSrc1, src1, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2, 0);
+ let Inst{40-32} = !if(P.HasSrc0, src0, ?);
+ let Inst{49-41} = !if(P.HasSrc1, src1, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2, ?);
let Inst{60-59} = !if(P.HasOMod, omod, 0);
let Inst{61} = !if(P.HasSrc0Mods, src0_modifiers{0}, 0);
let Inst{62} = !if(P.HasSrc1Mods, src1_modifiers{0}, 0);
@@ -513,9 +513,9 @@ class VOP3Pe <VOPProfile P> : Enc64, VOP3Pe_Base {
let Inst{15} = !if(P.HasClamp, clamp{0}, 0);
- let Inst{40-32} = !if(P.HasSrc0, src0, 0);
- let Inst{49-41} = !if(P.HasSrc1, src1, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2, 0);
+ let Inst{40-32} = !if(P.HasSrc0, src0, ?);
+ let Inst{49-41} = !if(P.HasSrc1, src1, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2, ?);
let Inst{59} = !cond(!and(P.HasSrc0, P.HasOpSel) : src0_modifiers{3},
P.IsDOT : 1,
P.HasMatrixScale : matrix_b_scale{0},
@@ -550,12 +550,12 @@ class VOP3Pe_MAI <bits<7> op, VOPProfile P, bit acc_cd = 0> : Enc64, VOP3Pe_MAI_
let Inst{22-16} = op;
let Inst{31-23} = 0x1a7; //encoding
- let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, 0);
- let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2, 0);
+ let Inst{40-32} = !if(P.HasSrc0, src0{8-0}, ?);
+ let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2, ?);
- let Inst{59} = !if(P.HasSrc0, src0{9}, 0); // acc(0)
- let Inst{60} = !if(P.HasSrc1, src1{9}, 0); // acc(1)
+ let Inst{59} = !if(P.HasSrc0, src0{9}, ?); // acc(0)
+ let Inst{60} = !if(P.HasSrc1, src1{9}, ?); // acc(1)
let Inst{63-61} = !if(P.HasSrc1, blgp, 0);
}
@@ -635,12 +635,12 @@ class VOP3PXe <bits<7> op, VOPProfile MFMAPfl, bit acc_cd = 0> : Enc128, VOP3Pe_
let Inst{86-80} = op;
let Inst{95-87} = 0x1a7; //encoding
- let Inst{104-96} = !if(MFMAPfl.HasSrc0, src0{8-0}, 0);
- let Inst{113-105} = !if(MFMAPfl.HasSrc1, src1{8-0}, 0);
- let Inst{122-114} = !if(MFMAPfl.HasSrc2, src2, 0);
+ let Inst{104-96} = !if(MFMAPfl.HasSrc0, src0{8-0}, ?);
+ let Inst{113-105} = !if(MFMAPfl.HasSrc1, src1{8-0}, ?);
+ let Inst{122-114} = !if(MFMAPfl.HasSrc2, src2, ?);
- let Inst{123} = !if(MFMAPfl.HasSrc0, src0{9}, 0); // acc(0)
- let Inst{124} = !if(MFMAPfl.HasSrc1, src1{9}, 0); // acc(1)
+ let Inst{123} = !if(MFMAPfl.HasSrc0, src0{9}, ?); // acc(0)
+ let Inst{124} = !if(MFMAPfl.HasSrc1, src1{9}, ?); // acc(1)
let Inst{127-125} = !if(MFMAPfl.HasSrc1, blgp, 0);
}
@@ -702,7 +702,7 @@ class VOP_SDWAe<VOPProfile P> : Enc64 {
bits<2> dst_unused;
bits<1> clamp;
- let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, ?);
let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, ?);
let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0);
@@ -736,11 +736,11 @@ class VOP_SDWA9e<VOPProfile P> : Enc64 {
bits<5> src1_modifiers;
bits<1> src1_sgpr;
- let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{4}, 0);
let Inst{53-52} = !if(P.HasSrc0FloatMods, src0_modifiers{1-0}, 0);
- let Inst{55} = !if(P.HasSrc0, src0{8}, 0);
+ let Inst{55} = !if(P.HasSrc0, src0{8}, ?);
let Inst{58-56} = !if(P.HasSrc1, src1_sel{2-0}, 0);
let Inst{59} = !if(P.HasSrc1IntMods, src1_modifiers{4}, 0);
let Inst{61-60} = !if(P.HasSrc1FloatMods, src1_modifiers{1-0}, 0);
@@ -893,7 +893,7 @@ class VOP_DPPe<VOPProfile P, bit IsDPP16=0> : Enc64 {
bits<4> row_mask;
bit fi;
- let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{48-40} = dpp_ctrl;
let Inst{50} = !if(IsDPP16, fi, ?);
let Inst{51} = bound_ctrl;
@@ -958,8 +958,8 @@ class VOP3_DPPe_Common<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op, P>
bits<9> src2;
let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
- let Inst{49-41} = !if(P.HasSrc1, src1, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2, 0);
+ let Inst{49-41} = !if(P.HasSrc1, src1, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2, ?);
}
class VOP3_DPPe_Common_t16<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op, P> {
@@ -968,8 +968,8 @@ class VOP3_DPPe_Common_t16<bits<10> op, VOPProfile P> : VOP3_DPPe_Common_Base<op
bits<11> src2;
let Inst{7-0} = !if(P.EmitDst, vdst{7-0}, 0);
- let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2{8-0}, 0);
+ let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2{8-0}, ?);
}
class VOP3P_DPPe_Common_Base<bits<8> op, VOPProfile P> : Enc96 {
@@ -1002,8 +1002,8 @@ class VOP3P_DPPe_Common<bits<8> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P
bits<9> src2;
let Inst{7-0} = vdst;
- let Inst{49-41} = !if(P.HasSrc1, src1, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2, 0);
+ let Inst{49-41} = !if(P.HasSrc1, src1, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2, ?);
}
class VOP3P_DPPe_Common_t16<bits<8> op, VOPProfile P> : VOP3P_DPPe_Common_Base<op, P> {
@@ -1012,8 +1012,8 @@ class VOP3P_DPPe_Common_t16<bits<8> op, VOPProfile P> : VOP3P_DPPe_Common_Base<o
bits<11> src2;
let Inst{7-0} = vdst{7-0};
- let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, 0);
- let Inst{58-50} = !if(P.HasSrc2, src2{8-0}, 0);
+ let Inst{49-41} = !if(P.HasSrc1, src1{8-0}, ?);
+ let Inst{58-50} = !if(P.HasSrc2, src2{8-0}, ?);
}
class VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[],
@@ -1138,7 +1138,7 @@ class VOP3_DPP_Enc <bits<10> op, VOPProfile P, bit IsDPP16> :
VOP3_DPPe_Fields {
let Inst{40-32} = 0xfa;
- let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{80-72} = dpp_ctrl;
let Inst{82} = !if(IsDPP16, fi, ?);
let Inst{83} = bound_ctrl;
@@ -1158,7 +1158,7 @@ class VOP3_DPP_Enc_t16<bits<10> op, VOPProfile P, bit IsDPP16 >
VOP3_DPPe_Fields_t16 {
let Inst{40-32} = 0xfa;
- let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{80-72} = dpp_ctrl;
let Inst{82} = !if(IsDPP16, fi, ?);
let Inst{83} = bound_ctrl;
@@ -1184,7 +1184,7 @@ class VOP3P_DPP <bits<8> op, string OpName, VOPProfile P, bit IsDPP16,
let VOP3P = 1;
let Inst{40-32} = 0xfa;
- let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{80-72} = dpp_ctrl;
let Inst{82} = !if(IsDPP16, fi, ?);
let Inst{83} = bound_ctrl;
@@ -1199,7 +1199,7 @@ class VOP_DPP8e<VOPProfile P> : Enc64 {
bits<24> dpp8;
bits<9> fi;
- let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{63-40} = dpp8{23-0};
}
@@ -1250,7 +1250,7 @@ class VOP3_DPP8_Enc <bits<10> op, VOPProfile P> :
VOP3_DPPe_Common<op, P>,
VOP3_DPP8e_Fields {
let Inst{40-32} = fi;
- let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{95-72} = dpp8{23-0};
}
@@ -1261,7 +1261,7 @@ class VOP3_DPP8_Enc_t16 <bits<10> op, VOPProfile P> :
VOP3_DPPe_Common_t16<op, P>,
VOP3_DPP8e_Fields_t16 {
let Inst{40-32} = fi;
- let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{95-72} = dpp8{23-0};
}
@@ -1274,7 +1274,7 @@ class VOP3P_DPP8<bits<8> op, string OpName, VOPProfile P> :
let VOP3P = 1;
let Inst{40-32} = fi;
- let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, 0);
+ let Inst{71-64} = !if(P.HasSrc0, src0{7-0}, ?);
let Inst{95-72} = dpp8{23-0};
}
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt
index d574d139df466..f4ed5990fa0fe 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_vop1.txt
@@ -2559,6 +2559,9 @@
0x00,0x00,0x00,0x7e
# GFX10: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+0xff,0x01,0x00,0x7e
+# GFX10: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+
0x01,0x6f,0xfe,0x7f
# GFX10: v_not_b32_e32 v255, v1 ; encoding: [0x01,0x6f,0xfe,0x7f]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
index e87bc397894c6..a7d17316eaee8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
@@ -2758,6 +2758,9 @@
0x00,0x00,0x00,0x7e
# GFX11: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+0xff,0x01,0x00,0x7e
+# GFX11: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+
0x01,0xd3,0x0a,0x7e
# GFX11-FAKE16: v_not_b16_e32 v5, v1 ; encoding: [0x01,0xd3,0x0a,0x7e]
# GFX11-REAL16: v_not_b16_e32 v5.l, v1.l ; encoding: [0x01,0xd3,0x0a,0x7e]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
index a291d5d552595..7bd85e2ca6317 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
@@ -5,6 +5,10 @@
0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
# GFX11: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+# Check that src1 and src2 are ignored.
+0x05,0x00,0xb8,0xd5,0xfa,0xfe,0xff,0x07,0x01,0x1b,0x00,0xff
+# GFX11: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
# GFX11: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
index 69c3cd859e56d..a9f0a2cac0d21 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
@@ -5,6 +5,10 @@
0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
# GFX11: v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+# Check that src1 and src2 are ignored.
+0x05,0x00,0xb8,0xd5,0xe9,0xfe,0xff,0x07,0x01,0x77,0x39,0x05
+# GFX11: v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
+
0xff,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
# GFX11: v_bfrev_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
index f08cbcf0da9eb..b83721265e42e 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_from_vop1.txt
@@ -2750,6 +2750,9 @@
0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00
# GFX11: v_nop ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+0x00,0x00,0x80,0xd5,0xff,0xff,0xff,0x07
+# GFX11: v_nop ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+
0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00
# GFX11-FAKE16: v_not_b16_e64 v5, v1 ; encoding: [0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00]
# GFX11-REAL16: v_not_b16_e64 v5.l, v1.l ; encoding: [0x05,0x00,0xe9,0xd5,0x01,0x01,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
index c2ff03eed3e49..5e428c8066f04 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_vop3_from_vop1.txt
@@ -2927,6 +2927,9 @@
0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00
# GFX1250: v_nop ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+0x00,0x00,0x80,0xd5,0xff,0xff,0xff,0x07
+# GFX1250: v_nop ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+
0xff,0x00,0xe9,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00
# GFX1250-FAKE16: v_not_b16_e64 v255, 0xfe0b ; encoding: [0xff,0x00,0xe9,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
# GFX1250-REAL16: v_not_b16_e64 v255.l, 0xfe0b ; encoding: [0xff,0x00,0xe9,0xd5,0xff,0x00,0x00,0x00,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
index caad79daccc2e..49e2f893ef1fc 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
@@ -6575,6 +6575,9 @@
0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00
# GFX12: v_nop ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+0x00,0x00,0x80,0xd5,0xff,0xff,0xff,0x07
+# GFX12: v_nop ; encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+
0x05,0x00,0x58,0xd6,0x01,0x05,0x0e,0x00
# GFX12: v_or3_b32 v5, v1, v2, s3 ; encoding: [0x05,0x00,0x58,0xd6,0x01,0x05,0x0e,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
index f7359660daa18..71c2f0c4ac201 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
@@ -7,6 +7,10 @@
0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff
# GFX12: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+# Check that src1 and src2 are ignored.
+0x05,0x00,0xb8,0xd5,0xfa,0xfe,0xff,0x07,0x01,0x1b,0x00,0xff
+# GFX12: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
+
0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff
# GFX12: v_bfrev_b32_e64_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0xb8,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
index 1b2d51b350f8c..e3b8a3ba68876 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
@@ -7,7 +7,8 @@
0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
# GFX12: v_bfrev_b32_e64_dpp v5, v1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0xb8,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05]
-0xff,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00
+# Check that src1 and src2 are ignored.
+0xff,0x00,0xb8,0xd5,0xea,0xfe,0xff,0x07,0xff,0x00,0x00,0x00
# GFX12: v_bfrev_b32_e64_dpp v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xff,0x00,0xb8,0xd5,0xea,0x00,0x00,0x00,0xff,0x00,0x00,0x00]
0x05,0x00,0xdc,0xd5,0xe9,0x00,0x00,0x00,0x01,0x77,0x39,0x05
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt
index b979828fc0d29..88a53b953a7fe 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop1.txt
@@ -3448,6 +3448,9 @@
0x00,0x00,0x00,0x7e
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+0xff,0x01,0x00,0x7e
+# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+
0x01,0x57,0xfe,0x7f
# CHECK: v_not_b32_e32 v255, v1 ; encoding: [0x01,0x57,0xfe,0x7f]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
index 689d92f785afa..7a1c5f3b42be4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_vop3.txt
@@ -18793,6 +18793,9 @@
0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00
# CHECK: v_nop ; encoding: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
+0x00,0x00,0x40,0xd1,0xff,0xff,0xff,0x07
+# CHECK: v_nop ; encoding: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
+
0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00
# CHECK: v_not_b32_e64 v255, v1 ; encoding: [0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt
index 2f3de6dc28239..da0de7c3bb757 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx908_mai.txt
@@ -3,6 +3,10 @@
# GFX908: v_accvgpr_read_b32 v2, a0 ; encoding: [0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18]
0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18
+# Check that src1 and src2 are ignored.
+# GFX908: v_accvgpr_read_b32 v2, a0 ; encoding: [0x02,0x40,0xd8,0xd3,0x00,0x01,0x00,0x18]
+0x02,0x40,0xd8,0xd3,0x00,0xff,0xff,0x1f
+
# Check the alternative encoding with unused op_sel_hi bits set to zero
# and not to default 1 is accepted.
#
@@ -27,6 +31,10 @@
# GFX908: v_accvgpr_write_b32 a2, v1 ; encoding: [0x02,0x40,0xd9,0xd3,0x01,0x01,0x00,0x18]
0x02,0x40,0xd9,0xd3,0x01,0x01,0x00,0x18
+# Check that src1 and src2 are ignored.
+# GFX908: v_accvgpr_write_b32 a2, v1 ; encoding: [0x02,0x40,0xd9,0xd3,0x01,0x01,0x00,0x18]
+0x02,0x40,0xd9,0xd3,0x01,0xff,0xff,0x1f
+
# Check the alternative encoding with unused op_sel_hi bits set to zero
# and not to default 1 is accepted.
#
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt
index d3575d414264b..5cd317320096c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop1.txt
@@ -2701,6 +2701,9 @@
0x00,0x00,0x00,0x7e
# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+0xff,0x01,0x00,0x7e
+# CHECK: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
+
0x01,0x57,0xfe,0x7f
# CHECK: v_not_b32_e32 v255, v1 ; encoding: [0x01,0x57,0xfe,0x7f]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
index 0bbb50e88bd2f..3c1534717b8b3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_vop3.txt
@@ -18778,6 +18778,9 @@
0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00
# CHECK: v_nop ; encoding: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
+0x00,0x00,0x40,0xd1,0xff,0xff,0xff,0x07
+# CHECK: v_nop ; encoding: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
+
0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00
# CHECK: v_not_b32_e64 v255, v1 ; encoding: [0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
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