[llvm-branch-commits] [llvm] 1a5938e - [Hexagon] Disable new value jumps when packetizer is disabled (#180615)

[Douglas Yung via llvm-branch-commits]

Author: Brian Cain
Date: 2026-03-05T17:10:15Z
New Revision: 1a5938e7c87cdf913a0aff72ef3a48dd02625184

URL: https://github.com/llvm/llvm-project/commit/1a5938e7c87cdf913a0aff72ef3a48dd02625184
DIFF: https://github.com/llvm/llvm-project/commit/1a5938e7c87cdf913a0aff72ef3a48dd02625184.diff

LOG: [Hexagon] Disable new value jumps when packetizer is disabled (#180615)

New value jumps require the feeder instruction to be in the same packet
as the consumer (.new) instruction. When --disable-packetizer is used,
each instruction is placed in its own packet, making it impossible to
satisfy this requirement.

Previously, using --disable-packetizer would cause an assertion failure
in the MCCodeEmitter: "Couldn't find producer". This change fixes the
crash by checking the DisablePacketizer flag in the NewValueJump pass
and skipping NVJ generation when packetization is disabled.

(cherry picked from commit e1be4dfe1ef889c51d7e1704782a31dc65bb745c)

Added: 
    llvm/test/CodeGen/Hexagon/disable-packetizer-nvj.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
    llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
index 5a1d5bc669169..b237f11d926aa 100644
--- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -63,6 +63,8 @@ static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden,
 static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden,
                                           cl::desc("Disable New Value Jumps"));
 
+extern cl::opt<bool> DisablePacketizer;
+
 namespace {
 
   struct HexagonNewValueJump : public MachineFunctionPass {
@@ -453,7 +455,9 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
       MF.getSubtarget().getRegisterInfo());
   MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
 
-  if (DisableNewValueJumps ||
+  // New value jumps require the feeder instruction to be in the same packet.
+  // If packetization is disabled, we cannot generate new value jumps.
+  if (DisableNewValueJumps || DisablePacketizer ||
       !MF.getSubtarget<HexagonSubtarget>().useNewValueJumps())
     return false;
 

diff  --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index d39b79a86753a..8d1c17ca97421 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -55,9 +55,8 @@ using namespace llvm;
 
 #define DEBUG_TYPE "packets"
 
-static cl::opt<bool>
-    DisablePacketizer("disable-packetizer", cl::Hidden,
-                      cl::desc("Disable Hexagon packetizer pass"));
+cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden,
+                                cl::desc("Disable Hexagon packetizer pass"));
 
 static cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden,
                                 cl::init(true),

diff  --git a/llvm/test/CodeGen/Hexagon/disable-packetizer-nvj.ll b/llvm/test/CodeGen/Hexagon/disable-packetizer-nvj.ll
new file mode 100644
index 0000000000000..c2fac38625d76
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/disable-packetizer-nvj.ll
@@ -0,0 +1,34 @@
+; RUN: llc -mtriple=hexagon -mcpu=hexagonv68 -O2 --disable-packetizer -filetype=obj -o /dev/null %s
+; RUN: llc -mtriple=hexagon -mcpu=hexagonv68 -O2 -mattr=-nvj -filetype=obj -o /dev/null %s
+; REQUIRES: asserts
+
+; Check that compiling with --disable-packetizer does not crash.
+; New value jumps require the feeder instruction to be in the same packet
+; as the consumer (.new) instruction. When packetization is disabled, the
+; NVJ pass must be skipped to avoid an assertion in the MCCodeEmitter
+; ("Couldn't find producer").
+;
+; The branches here are non-if-convertible (due to calls), ensuring the
+; compare+branch pattern survives to the NVJ pass regardless of the
+; optimization pipeline used.
+
+declare void @do_work(i32)
+declare void @do_other(i32)
+
+define void @test_nvj(ptr %p, i32 %threshold) {
+entry:
+  %val = load i32, ptr %p, align 4
+  %cmp = icmp eq i32 %val, %threshold
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:
+  call void @do_work(i32 %val)
+  br label %exit
+
+if.else:
+  call void @do_other(i32 %val)
+  br label %exit
+
+exit:
+  ret void
+}