[llvm-branch-commits] [llvm] release/22.x: [AArch64] Fix sign-extend-inreg combine for i1 types (#177976) (PR #184777)

[via llvm-branch-commits]

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/184777

Backport ffb7a9f0ec80d5b12aa440d8446d2379827100f4

Requested by: @sdesmalen-arm

>From 34bc9e8c260e63766e6e901c7bde0ee09c1827a8 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Fri, 30 Jan 2026 08:26:35 +0000
Subject: [PATCH] [AArch64] Fix sign-extend-inreg combine for i1 types
 (#177976)

This fixes https://github.com/llvm/llvm-project/issues/177925

(cherry picked from commit ffb7a9f0ec80d5b12aa440d8446d2379827100f4)
---
 .../Target/AArch64/AArch64ISelLowering.cpp    |  6 ++--
 llvm/test/CodeGen/AArch64/sve-sext-zext.ll    | 28 +++++++++++++++++++
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 5dfa65fca4f4a..a55b1facb103f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -27658,10 +27658,10 @@ performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
     SDValue ExtOp = Src->getOperand(0);
     auto VT = cast<VTSDNode>(N->getOperand(1))->getVT();
     EVT EltTy = VT.getVectorElementType();
-    (void)EltTy;
 
-    assert((EltTy == MVT::i8 || EltTy == MVT::i16 || EltTy == MVT::i32) &&
-           "Sign extending from an invalid type");
+    if (EltTy.getSizeInBits() >
+        ExtOp.getValueType().getScalarType().getSizeInBits())
+      return SDValue();
 
     EVT ExtVT = VT.getDoubleNumVectorElementsVT(*DAG.getContext());
 
diff --git a/llvm/test/CodeGen/AArch64/sve-sext-zext.ll b/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
index 845628a91498b..54dd83eaec507 100644
--- a/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
+++ b/llvm/test/CodeGen/AArch64/sve-sext-zext.ll
@@ -584,3 +584,31 @@ define <vscale x 2 x i64> @zext_inreg_i64_from_i32(<vscale x 4 x i32> %a) {
   %zext = zext <vscale x 2 x i32> %subvec to <vscale x 2 x i64>
   ret <vscale x 2 x i64> %zext
 }
+
+; Sign-extend-inreg from i8 -> i1 -> i16
+define <vscale x 16 x i16> @sext_inreg_i1_to_i16_from_i8(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: sext_inreg_i1_to_i16_from_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.b, z0.b, #7
+; CHECK-NEXT:    asr z1.b, z0.b, #7
+; CHECK-NEXT:    sunpklo z0.h, z1.b
+; CHECK-NEXT:    sunpkhi z1.h, z1.b
+; CHECK-NEXT:    ret
+  %a.trunc = trunc <vscale x 16 x i8> %a to <vscale x 16 x i1>
+  %a.sextinreg = sext <vscale x 16 x i1> %a.trunc to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %a.sextinreg
+}
+
+; Sign-extend-inreg from i8 -> i2 -> i16
+define <vscale x 16 x i16> @sext_inreg_i2_to_i16_from_i8(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: sext_inreg_i2_to_i16_from_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsl z0.b, z0.b, #6
+; CHECK-NEXT:    asr z1.b, z0.b, #6
+; CHECK-NEXT:    sunpklo z0.h, z1.b
+; CHECK-NEXT:    sunpkhi z1.h, z1.b
+; CHECK-NEXT:    ret
+  %a.trunc = trunc <vscale x 16 x i8> %a to <vscale x 16 x i2>
+  %a.sextinreg = sext <vscale x 16 x i2> %a.trunc to <vscale x 16 x i16>
+  ret <vscale x 16 x i16> %a.sextinreg
+}