[llvm-branch-commits] [RISCV] Combine vwaddu_wv+vabd(u) to vwabda(u) (PR #184603)

[Luke Lau via llvm-branch-commits]

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@@ -19128,6 +19128,66 @@ static SDValue performVWABDACombine(SDNode *N, SelectionDAG &DAG,
   return Result;
 }
 
+// vwaddu_wv C (vabd A B) -> vwabda(A B C)
+// vwaddu_wv C (vabdu A B) -> vwabdau(A B C)
+static SDValue performVWABDACombine_WV(SDNode *N, SelectionDAG &DAG,
+                                       const RISCVSubtarget &Subtarget) {
+  if (!Subtarget.hasStdExtZvabd())
+    return SDValue();
+
+  MVT VT = N->getSimpleValueType(0);
+  // The result is widened, so we can accept i16/i32 here.
+  if (VT.getVectorElementType() != MVT::i16 &&
+      VT.getVectorElementType() != MVT::i32)
+    return SDValue();
+
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  SDValue Passthru = N->getOperand(2);
+  if (!Passthru->isUndef())
+    return SDValue();
+
+  SDValue Mask = N->getOperand(3);
+  SDValue VL = N->getOperand(4);
+  bool HasZExt = 0;
+  MVT ExtVT = MVT::INVALID_SIMPLE_VALUE_TYPE;
+  auto IsABD = [&](SDValue Op) {
+    unsigned Opc = Op.getOpcode();
+    if (Opc != ISD::ABDS && Opc != ISD::ABDU) {
+      if (Opc == RISCVISD::VZEXT_VL) {
+        SDValue Src = Op->getOperand(0);
+        if (Src->getOpcode() == RISCVISD::ABDS_VL ||
+            Src->getOpcode() == RISCVISD::ABDU_VL) {
+          HasZExt = true;
+          ExtVT = Op->getSimpleValueType(0);
+          return Src;
+        }
+      }
+      return SDValue();
+    }
+    return Op;
+  };
+
+  SDValue Diff = IsABD(Op0);
+  Diff = Diff ? Diff : IsABD(Op1);
+  if (!Diff)
+    return SDValue();
+  SDValue Acc = Diff == Op0 ? Op1 : Op0;
+
+  SDLoc DL(N);
+  SDValue DiffA = Diff.getOperand(0);
+  SDValue DiffB = Diff.getOperand(1);
+  if (HasZExt) {
+    DiffA = DAG.getNode(RISCVISD::VZEXT_VL, DL, ExtVT, DiffA, Mask, VL);
+    DiffB = DAG.getNode(RISCVISD::VZEXT_VL, DL, ExtVT, DiffB, Mask, VL);
+  }
+  SDValue Result =
+      DAG.getNode(Diff.getOpcode() == ISD::ABDS ? RISCVISD::VWABDA_VL
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lukel97 wrote:

Does this need to check for RISCVISD::ABDS_VL too?

https://github.com/llvm/llvm-project/pull/184603