[llvm-branch-commits] [lldb] [lldb][RISCV][test] Add RVV API tests (PR #184309)
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Tue Mar 3 01:59:01 PST 2026
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``````````bash
darker --check --diff -r origin/main...HEAD lldb/packages/Python/lldbsuite/test/rvvutil.py lldb/test/API/riscv/rvv-availability/TestRVVAvailability.py lldb/test/API/riscv/rvv-consistency/TestRVVConsistency.py lldb/test/API/riscv/rvv-printout/TestRVVPrintout.py lldb/test/API/riscv/rvv-rwr/TestRVVReadWrite.py lldb/test/API/riscv/rvv-side-effects/TestRVVSideEffects.py lldb/test/API/riscv/rvv-unsupported/TestRVVUnsupported.py lldb/test/API/riscv/rvv-vcsr-consistency/TestRVVConsistencyVCSR.py lldb/packages/Python/lldbsuite/test/lldbtest.py
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``````````diff
--- packages/Python/lldbsuite/test/lldbtest.py 2026-03-03 08:34:25.000000 +0000
+++ packages/Python/lldbsuite/test/lldbtest.py 2026-03-03 09:58:30.550731 +0000
@@ -1438,11 +1438,13 @@
"""Returns true if the architecture is RISCV64 or RISCV32."""
return self.getArchitecture() in ["riscv64", "riscv32"]
def isRISCVRVV(self):
riscv_std_extensions_pattern = r"rv([0-9a-z]+)(_|\b)"
- riscv_std_extensions = re.search(riscv_std_extensions_pattern, self.getCPUInfo()).group(1)
+ riscv_std_extensions = re.search(
+ riscv_std_extensions_pattern, self.getCPUInfo()
+ ).group(1)
return self.isRISCV() and "v" in riscv_std_extensions
def getArchitecture(self):
"""Returns the architecture in effect the test suite is running with."""
return lldbplatformutil.getArchitecture()
--- test/API/riscv/rvv-availability/TestRVVAvailability.py 2026-03-03 08:34:25.000000 +0000
+++ test/API/riscv/rvv-availability/TestRVVAvailability.py 2026-03-03 09:58:30.636092 +0000
@@ -12,23 +12,45 @@
class RISCVRVVAvailabilityTestCase(TestBase):
def _check_vector_registers_unavailable(self):
"""Check that all vector registers and CSRs are unavailable."""
- for reg_name in ["vstart", "vl", "vtype", "vcsr", "vlenb", "v0", "v1", "v15", "v31"]:
+ for reg_name in [
+ "vstart",
+ "vl",
+ "vtype",
+ "vcsr",
+ "vlenb",
+ "v0",
+ "v1",
+ "v15",
+ "v31",
+ ]:
self.expect(f"register read {reg_name}", substrs=["error:", "unavailable"])
def _check_vector_registers_available(self):
"""Check that all vector registers and CSRs are available."""
- for reg_name in ["vstart", "vl", "vtype", "vcsr", "vlenb", "v0", "v1", "v15", "v31"]:
+ for reg_name in [
+ "vstart",
+ "vl",
+ "vtype",
+ "vcsr",
+ "vlenb",
+ "v0",
+ "v1",
+ "v15",
+ "v31",
+ ]:
self.expect(f"register read {reg_name}", substrs=[f"{reg_name} = "])
@skipIf(archs=no_match("^riscv.*"))
def test_available_with_vlenb_read(self):
"""Test registers available even when only vlenb is read before main."""
rvvutil.skip_if_rvv_unsupported(self)
- self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv -DREAD_VLENB_BEFORE_MAIN"})
+ self.build(
+ dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv -DREAD_VLENB_BEFORE_MAIN"}
+ )
lldbutil.run_to_name_breakpoint(self, "main")
self._check_vector_registers_available()
@skipIf(archs=no_match("^riscv.*"))
def test_unavailable_without_vector_ops(self):
@@ -40,8 +62,10 @@
@skipIf(archs=no_match("^riscv.*"))
def test_available_after_vsetvli(self):
"""Test registers available after vsetvli is executed."""
rvvutil.skip_if_rvv_unsupported(self)
- self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv -DSET_VSETVLI_BEFORE_MAIN"})
+ self.build(
+ dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv -DSET_VSETVLI_BEFORE_MAIN"}
+ )
lldbutil.run_to_name_breakpoint(self, "main")
self._check_vector_registers_available()
--- test/API/riscv/rvv-consistency/TestRVVConsistency.py 2026-03-03 08:34:25.000000 +0000
+++ test/API/riscv/rvv-consistency/TestRVVConsistency.py 2026-03-03 09:58:30.675885 +0000
@@ -16,29 +16,36 @@
"""Test that vl is clamped to VLMAX when set too high."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "workload_end", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "workload_end", lldb.SBFileSpec("main.cpp")
+ )
# Try to set vl to a huge value (9999)
self.runCmd("register write vl 9999")
self.expect("register read vl", substrs=[f"vl = 0x{9999:0>16x}"])
# Continue and check that vl is clamped
self.runCmd("continue")
- self.expect("register read vl", substrs=[f"vl = 0x{rvvutil.calculate_vlmax(self):0>16x}"])
+ self.expect(
+ "register read vl",
+ substrs=[f"vl = 0x{rvvutil.calculate_vlmax(self):0>16x}"],
+ )
@skipIf(archs=no_match("^riscv.*"))
def test_rvv_vl_lmul_coherence(self):
"""Test that changing LMUL affects vl appropriately."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "workload_end", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "workload_end", lldb.SBFileSpec("main.cpp")
+ )
self.runCmd("register write vtype 3")
self.expect("register read vtype", substrs=[f"vtype = 0x{3:0>16x}"])
self.runCmd("register write vl 9999")
self.expect("register read vl", substrs=[f"vl = 0x{9999:0>16x}"])
@@ -46,11 +53,14 @@
self.runCmd("continue")
self.assertEqual(rvvutil.get_lmul(self), 8, "LMUL should be 8")
vlenb = rvvutil.get_vlenb(self)
- self.expect("register read vl", substrs=[f"vl = 0x{rvvutil.calculate_vlmax(self):0>16x}"])
+ self.expect(
+ "register read vl",
+ substrs=[f"vl = 0x{rvvutil.calculate_vlmax(self):0>16x}"],
+ )
self.runCmd("continue")
# Restore LMUL=1
self.runCmd("register write vtype 0")
@@ -59,20 +69,25 @@
self.runCmd("continue")
self.assertEqual(rvvutil.get_lmul(self), 1, "LMUL should be 1")
# Check that vl is clamped after the LMUL was reduced
- self.expect("register read vl", substrs=[f"vl = 0x{rvvutil.calculate_vlmax(self):0>16x}"])
+ self.expect(
+ "register read vl",
+ substrs=[f"vl = 0x{rvvutil.calculate_vlmax(self):0>16x}"],
+ )
@skipIf(archs=no_match("^riscv.*"))
def test_rvv_vstart(self):
"""Test vstart behavior."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "workload_end", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "workload_end", lldb.SBFileSpec("main.cpp")
+ )
self.runCmd("register write vstart 8")
self.expect("register read vstart", substrs=[f"vstart = 0x{8:0>16x}"])
self.runCmd("continue")
@@ -84,11 +99,13 @@
def test_rvv_illegal_vtype(self):
"""Test illegal vtype configuration handling."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "workload_end", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "workload_end", lldb.SBFileSpec("main.cpp")
+ )
vlenb = rvvutil.get_vlenb(self)
if vlenb >= 64:
self.skipTest("Test requires VLENB < 64")
@@ -97,11 +114,13 @@
# Set illegal vtype: SEW=64 (vsew=3), LMUL=1/8 (vlmul=5)
# vtype = 5 | (3 << 3) = 5 | 24 = 29
illegal_vtype = 5 | (3 << 3)
self.runCmd(f"register write vtype {illegal_vtype}")
self.assertEqual(rvvutil.get_sew(self), 64, "SEW should be 64")
- self.assertAlmostEqual(rvvutil.get_lmul(self), 1 / 8, places=7, msg="LMUL should be 1/8")
+ self.assertAlmostEqual(
+ rvvutil.get_lmul(self), 1 / 8, places=7, msg="LMUL should be 1/8"
+ )
self.runCmd("stepi")
vtype = rvvutil.get_register_value(self, "vtype")
self.assertEqual((vtype >> 63) & 1, 1, "vtype should have vill=1")
--- test/API/riscv/rvv-printout/TestRVVPrintout.py 2026-03-03 08:34:25.000000 +0000
+++ test/API/riscv/rvv-printout/TestRVVPrintout.py 2026-03-03 09:58:30.702766 +0000
@@ -15,34 +15,44 @@
def test_rvv_register_read(self):
"""Test basic vector register printing."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "pre_vect_mem", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "pre_vect_mem", lldb.SBFileSpec("main.cpp")
+ )
vlenb = rvvutil.get_vlenb(self)
for reg_name in ["vstart", "vtype", "vcsr"]:
- self.expect(f"register read {reg_name}", substrs=[f"{reg_name} = 0x{0:0>16x}"])
+ self.expect(
+ f"register read {reg_name}", substrs=[f"{reg_name} = 0x{0:0>16x}"]
+ )
for reg_name in ["vl", "vlenb"]:
- self.expect(f"register read {reg_name}", substrs=[f"{reg_name} = 0x{vlenb:0>16x}"])
+ self.expect(
+ f"register read {reg_name}", substrs=[f"{reg_name} = 0x{vlenb:0>16x}"]
+ )
rvvutil.check_vector_register_bytes(self, "v0", [0 for _ in range(vlenb)])
rvvutil.check_vector_register_bytes(self, "v1", [1 for _ in range(vlenb)])
rvvutil.check_vector_register_bytes(self, "v2", [3 for _ in range(vlenb)])
for reg_num in range(3, 32):
- rvvutil.check_vector_register_bytes(self, f"v{reg_num}", [0 for _ in range(vlenb)])
+ rvvutil.check_vector_register_bytes(
+ self, f"v{reg_num}", [0 for _ in range(vlenb)]
+ )
@skipIf(archs=no_match("^riscv.*"))
def test_rvv_register_list(self):
"""Test 'register read --all' includes vector registers."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "pre_vect_mem", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "pre_vect_mem", lldb.SBFileSpec("main.cpp")
+ )
expected_regs = [f"v{i}" for i in range(32)]
expected_regs += ["vtype", "vcsr", "vl", "vstart", "vlenb"]
self.expect("register read --all")
--- test/API/riscv/rvv-rwr/TestRVVReadWrite.py 2026-03-03 08:34:25.000000 +0000
+++ test/API/riscv/rvv-rwr/TestRVVReadWrite.py 2026-03-03 09:58:30.726920 +0000
@@ -11,22 +11,28 @@
class RISCVRVVReadWriteTestCase(TestBase):
def _run_check(self, reg_name, write_value, expected_value):
self.runCmd(f"register write {reg_name} '{write_value}'")
- self.expect(f"register read {reg_name}", substrs=[f"{reg_name} = {expected_value}"])
+ self.expect(
+ f"register read {reg_name}", substrs=[f"{reg_name} = {expected_value}"]
+ )
self.runCmd("stepi")
- self.expect(f"register read {reg_name}", substrs=[f"{reg_name} = {expected_value}"])
+ self.expect(
+ f"register read {reg_name}", substrs=[f"{reg_name} = {expected_value}"]
+ )
@skipIf(archs=no_match("^riscv.*"))
def test_rvv_write_vector_registers(self):
"""Test writing to vector registers v0-v31."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "do_vector_stuff_end", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "do_vector_stuff_end", lldb.SBFileSpec("main.cpp")
+ )
vlenb = rvvutil.get_vlenb(self)
self.assertIsNotNone(vlenb, "vlenb should be readable")
for reg_num in range(32):
@@ -38,16 +44,20 @@
def test_rvv_write_vcsrs(self):
"""Test writing to CSRs."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
- lldbutil.run_to_source_breakpoint(self, "do_vector_stuff_end", lldb.SBFileSpec("main.cpp"))
+ lldbutil.run_to_source_breakpoint(
+ self, "do_vector_stuff_end", lldb.SBFileSpec("main.cpp")
+ )
for reg_name in ["vstart", "vtype", "vl"]:
self.runCmd("continue")
# 1 should be a valid value for vstart, vtype, vl
# so we use it here
self._run_check(reg_name, 1, f"0x{1:0>16x}")
# vlenb is read only
self.runCmd("continue")
- self.expect("register write vlenb 1", substrs=["Failed to write register"], error=True)
+ self.expect(
+ "register write vlenb 1", substrs=["Failed to write register"], error=True
+ )
--- test/API/riscv/rvv-side-effects/TestRVVSideEffects.py 2026-03-03 08:34:25.000000 +0000
+++ test/API/riscv/rvv-side-effects/TestRVVSideEffects.py 2026-03-03 09:58:30.765894 +0000
@@ -25,52 +25,68 @@
vlenb = rvvutil.get_vlenb(self)
self.assertIsNotNone(vlenb, "VLENB should be readable")
for i in range(32):
- rvvutil.check_vector_register_bytes(self, f"v{i}", [0 for _ in range(vlenb)])
+ rvvutil.check_vector_register_bytes(
+ self, f"v{i}", [0 for _ in range(vlenb)]
+ )
rvvutil.set_vector_register_bytes(self, "v0", list(range(vlenb)))
rvvutil.set_vector_register_bytes(self, "v1", [i + 7 for i in range(vlenb)])
# Continue to after vadd
- lldbutil.continue_to_source_breakpoint(self, process, "controlled_vadd_done", main_source_file)
+ lldbutil.continue_to_source_breakpoint(
+ self, process, "controlled_vadd_done", main_source_file
+ )
# Check that v0 and v1 are unchanged
rvvutil.check_vector_register_bytes(self, "v0", list(range(vlenb)))
rvvutil.check_vector_register_bytes(self, "v1", [i + 7 for i in range(vlenb)])
# Check that v2 contains the sum (v0 + v1)
- rvvutil.check_vector_register_bytes(self, "v2", [i + i + 7 for i in range(vlenb)])
+ rvvutil.check_vector_register_bytes(
+ self, "v2", [i + i + 7 for i in range(vlenb)]
+ )
for i in range(3, 32):
- rvvutil.check_vector_register_bytes(self, f"v{i}", [0 for _ in range(vlenb)])
+ rvvutil.check_vector_register_bytes(
+ self, f"v{i}", [0 for _ in range(vlenb)]
+ )
@skipIf(archs=no_match("^riscv.*"))
def test_rvv_wide_operations_with_vl_modification(self):
"""Test that modifying vl affects subsequent operations."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
main_source_file = lldb.SBFileSpec("main.cpp")
- (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(self, "vect_op_v0_add1", main_source_file)
+ (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
+ self, "vect_op_v0_add1", main_source_file
+ )
self.runCmd("register write vl 2")
- lldbutil.continue_to_source_breakpoint(self, process, "vect_op_v24_v0_add2", main_source_file)
+ lldbutil.continue_to_source_breakpoint(
+ self, process, "vect_op_v24_v0_add2", main_source_file
+ )
vlenb = rvvutil.get_vlenb(self)
self.assertIsNotNone(vlenb, "VLENB should be readable")
rvvutil.set_vector_register_bytes(self, "v8", list(range(vlenb)))
- lldbutil.continue_to_source_breakpoint(self, process, "vect_op_v16_v8_add2", main_source_file)
+ lldbutil.continue_to_source_breakpoint(
+ self, process, "vect_op_v16_v8_add2", main_source_file
+ )
self.runCmd("register write vtype 0")
- lldbutil.continue_to_source_breakpoint(self, process, "vect_wide_op_end", main_source_file)
+ lldbutil.continue_to_source_breakpoint(
+ self, process, "vect_wide_op_end", main_source_file
+ )
self.expect("register read vtype", substrs=[f"vtype = 0x{0:0>16x}"])
self.expect("register read vl", substrs=[f"vl = 0x{2:0>16x}"])
rvvutil.check_vector_register_bytes(self, "v8", list(range(vlenb)))
--- test/API/riscv/rvv-unsupported/TestRVVUnsupported.py 2026-03-03 08:34:25.000000 +0000
+++ test/API/riscv/rvv-unsupported/TestRVVUnsupported.py 2026-03-03 09:58:30.788949 +0000
@@ -22,11 +22,15 @@
self.expect("print a", substrs=["42"])
self.runCmd("register write a0 42")
self.expect("register read a0", substrs=[f"0x{42:0>16x}"])
for reg_name in ["vstart", "vl", "vlenb", "v0", "v15", "v31"]:
- self.expect(f"register read {reg_name}", substrs=["error:", "Invalid register name"], error=True)
+ self.expect(
+ f"register read {reg_name}",
+ substrs=["error:", "Invalid register name"],
+ error=True,
+ )
# Basic debugging should still work
self.expect("print a", substrs=["42"])
self.runCmd("register write a0 43")
self.expect("register read a0", substrs=[f"0x{43:0>16x}"])
--- test/API/riscv/rvv-vcsr-consistency/TestRVVConsistencyVCSR.py 2026-03-03 08:34:25.000000 +0000
+++ test/API/riscv/rvv-vcsr-consistency/TestRVVConsistencyVCSR.py 2026-03-03 09:58:30.922295 +0000
@@ -46,39 +46,53 @@
(target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
self, "vsetvl_done", lldb.SBFileSpec("main.cpp")
)
finish_bp = lldbutil.run_break_set_by_source_regexp(self, "do_vsetv_test_end")
- finish_thread = lldbutil.get_one_thread_stopped_at_breakpoint_id(process, finish_bp)
+ finish_thread = lldbutil.get_one_thread_stopped_at_breakpoint_id(
+ process, finish_bp
+ )
while finish_thread is None:
if not self._is_lmul_sew_legal():
# For illegal configs, vtype should show vill=1
vtype = rvvutil.get_register_value(self, "vtype")
self.assertEqual((vtype >> 63) & 1, 1, "vtype should show vill=1")
- self.expect("register read vl", substrs=[f"vl = 0x{self._get_expected_vl():0>16x}"])
+ self.expect(
+ "register read vl", substrs=[f"vl = 0x{self._get_expected_vl():0>16x}"]
+ )
self.runCmd("continue")
- finish_thread = lldbutil.get_one_thread_stopped_at_breakpoint_id(process, finish_bp)
+ finish_thread = lldbutil.get_one_thread_stopped_at_breakpoint_id(
+ process, finish_bp
+ )
@skipIf(archs=no_match("^riscv.*"))
def test_rvv_vcsr_register(self):
"""Test vcsr register."""
rvvutil.skip_if_rvv_unsupported(self)
self.build(dictionary={"CFLAGS_EXTRAS": "-march=rv64gcv"})
main_source_file = lldb.SBFileSpec("main.cpp")
- (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(self, "rvv_initialized", main_source_file)
+ (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
+ self, "rvv_initialized", main_source_file
+ )
# Test different vxrm values
for vxrm in range(4):
- lldbutil.continue_to_source_breakpoint(self, process, f"vxrm_{vxrm}", main_source_file)
+ lldbutil.continue_to_source_breakpoint(
+ self, process, f"vxrm_{vxrm}", main_source_file
+ )
self.assertEqual(self._get_vxml(), vxrm, "Invalid vxrm value")
- lldbutil.continue_to_source_breakpoint(self, process, "vxrm_0_again", main_source_file)
+ lldbutil.continue_to_source_breakpoint(
+ self, process, "vxrm_0_again", main_source_file
+ )
self.assertEqual(self._get_vxsat(), 1, "Invalid vxsat value")
self.assertEqual(self._get_vxml(), 3, "Invalid vxrm value")
- lldbutil.continue_to_source_breakpoint(self, process, "vcsr_done", main_source_file)
+ lldbutil.continue_to_source_breakpoint(
+ self, process, "vcsr_done", main_source_file
+ )
self.assertEqual(self._get_vxsat(), 1, "Invalid vxsat value")
self.assertEqual(self._get_vxml(), 0, "Invalid vxrm value")
``````````
</details>
https://github.com/llvm/llvm-project/pull/184309
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