[llvm-branch-commits] [RISC-V][MC][RVY] Add support for RVY loads/stores (PR #213417)

[Alexander Richardson via llvm-branch-commits]

https://github.com/arichardson created https://github.com/llvm/llvm-project/pull/213417

This adds supports for all new RVY loads/stores (capability-wide
versions: ly/sy instructions). Additionally, existing I/Zc* loads and
stores are updated to be mode-dependent, using either a YLEN register or
a XLEN register as the base.
In the former case loads/stores are authorized by that register,
and in the latter (compatibility mode), the loads/stores keep using an
address but are authorized by the DDC CSR. The assembler mnemonics are
the same in both cases. Prior to the standardization process CHERI
assembly used c-prefixed register names for capabilities, so we had the
following syntax:

```
lw x4, 0(c3) # capability mode: use new `CLW` instruction
lw x4, 0(x3) # integer mode: use existing `LW` instruction
```

During the standardization this was changed to keep the same register
name in both modes, so now we use `lw x4, 0(x3)` in both modes.

This allows using the RegClassByHwMode feature to reuse the same MC
instruction but with a different operand type depending on the HwMode.
The downstream fork had duplicated definitions which meant a lot of
switch statements now needed to handle both MCInsts. This approach
using HwMode should be much more maintainable and only introduces a
minor diff compared to what we had downstream.
This will also make it much easier adding support for RVY versions of
other extensions such as vector, since we just need to change out the
`GPRMem` operand with `PtrMem`.

This commit also adds assembler-level support for the RVI-compatible
mode of RVY where all base pointers are interpreted as XLEN values
instead of YLEN values using an internal xllvmrvyipm extension (until
the final toolchain convention has been ratified).