[llvm-branch-commits] [llvm] release/23.x: [RISCV] Fix incorrect lowering of VECTOR_INTERLEAVE on fixed vectors (#212642) (PR #213306)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jul 31 09:42:58 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: llvmbot
<details>
<summary>Changes</summary>
Backport ff9b99207b5d4ec73554defc1e3c1ac50f8ff1d8
Requested by: @<!-- -->mshockwave
---
Patch is 100.64 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/213306.diff
2 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+24-27)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll (+690-1062)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 738aa6dcf780a..00a13c95d1607 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13636,29 +13636,12 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
if (VecVT.getVectorElementType() == MVT::i1)
return widenVectorOpsToi8(Op, DL, DAG);
- // Convert to scalable vectors first.
- if (VecVT.isFixedLengthVector()) {
- MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
- SmallVector<SDValue, 8> Ops(Factor);
- for (unsigned i = 0U; i < Factor; ++i)
- Ops[i] = convertToScalableVector(ContainerVT, Op.getOperand(i), DAG,
- Subtarget);
-
- SmallVector<EVT, 8> VTs(Factor, ContainerVT);
- SDValue NewInterleave = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL, VTs, Ops);
-
- SmallVector<SDValue, 8> Res(Factor);
- for (unsigned i = 0U; i < Factor; ++i)
- Res[i] = convertFromScalableVector(VecVT, NewInterleave.getValue(i), DAG,
- Subtarget);
- return DAG.getMergeValues(Res, DL);
- }
-
- MVT XLenVT = Subtarget.getXLenVT();
- auto [Mask, VL] = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
+ MVT ContainerVecVT = VecVT;
+ if (VecVT.isFixedLengthVector())
+ ContainerVecVT = getContainerForFixedLengthVector(VecVT);
// If the VT is larger than LMUL=8, we need to split and reassemble.
- if ((VecVT.getSizeInBits().getKnownMinValue() * Factor) >
+ if ((ContainerVecVT.getSizeInBits().getKnownMinValue() * Factor) >
(8 * RISCV::RVVBitsPerBlock)) {
SmallVector<SDValue, 8> Ops(Factor * 2);
for (unsigned i = 0; i != Factor; ++i) {
@@ -13686,6 +13669,9 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
return DAG.getMergeValues(Concats, DL);
}
+ MVT XLenVT = Subtarget.getXLenVT();
+ auto [Mask, VL] = getDefaultVLOps(VecVT, ContainerVecVT, DL, DAG, Subtarget);
+
SDValue Interleaved;
// Spill to the stack using a segment store for simplicity.
@@ -13695,6 +13681,10 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
VecVT.getVectorElementCount() * Factor);
// Allocate a stack slot.
+ // Note that in the case where VecVT is fixed vector, even we later
+ // create a container for each (fixed vector) operand, we still allocate
+ // the stack with fixed vector size, rather than container size, as
+ // fixed vector size is already sufficient.
Align Alignment = DAG.getReducedAlign(VecVT, /*UseABI=*/false);
SDValue StackPtr =
DAG.CreateStackTemporary(MemVT.getStoreSize(), Alignment);
@@ -13710,15 +13700,18 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
Intrinsic::riscv_vsseg8_mask,
};
- unsigned Sz =
- Factor * VecVT.getVectorMinNumElements() * VecVT.getScalarSizeInBits();
+ unsigned Sz = Factor * ContainerVecVT.getVectorMinNumElements() *
+ ContainerVecVT.getScalarSizeInBits();
EVT VecTupTy = MVT::getRISCVVectorTupleVT(Sz, Factor);
SDValue StoredVal = DAG.getUNDEF(VecTupTy);
- for (unsigned i = 0; i < Factor; i++)
- StoredVal =
- DAG.getNode(RISCVISD::TUPLE_INSERT, DL, VecTupTy, StoredVal,
- Op.getOperand(i), DAG.getTargetConstant(i, DL, MVT::i32));
+ for (unsigned i = 0; i < Factor; i++) {
+ SDValue OpVal = Op.getOperand(i);
+ if (VecVT.isFixedLengthVector())
+ OpVal = convertToScalableVector(ContainerVecVT, OpVal, DAG, Subtarget);
+ StoredVal = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, VecTupTy, StoredVal,
+ OpVal, DAG.getTargetConstant(i, DL, MVT::i32));
+ }
SDValue Ops[] = {DAG.getEntryNode(),
DAG.getTargetConstant(IntrIds[Factor - 2], DL, XLenVT),
@@ -13747,6 +13740,10 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
return DAG.getMergeValues(Loads, DL);
}
+ assert(!VecVT.isFixedLengthVector() &&
+ "Fixed factor=2 vector interleave should already lower to "
+ "SHUFFLE_VECTOR");
+
if (Subtarget.hasStdExtZvzip() && !Op.getOperand(0).isUndef() &&
!Op.getOperand(1).isUndef()) {
MVT VT = Op->getSimpleValueType(0);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
index a56bb463dd2c4..56a68500747dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -171,83 +171,59 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind {
; CHECK-LABEL: vector_interleave3_v6i32_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: addi a0, sp, 8
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg3e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: vle32.v v9, (a2)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 2
-; CHECK-NEXT: add a1, a2, a1
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a1)
+; CHECK-NEXT: addi a0, sp, 24
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave3_v6i32_v2i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: addi sp, sp, -16
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: sub sp, sp, a0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: addi sp, sp, -32
+; ZVBB-NEXT: addi a0, sp, 8
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg3e32.v v8, (a0)
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: srli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: vle32.v v9, (a2)
+; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: vle32.v v9, (a1)
; ZVBB-NEXT: vle32.v v8, (a0)
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v9, 2
-; ZVBB-NEXT: add a1, a2, a1
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a1)
+; ZVBB-NEXT: addi a0, sp, 24
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a0)
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 4
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: add sp, sp, a0
-; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave3_v6i32_v2i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: sub sp, sp, a0
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: addi sp, sp, -32
+; ZVZIP-NEXT: addi a0, sp, 8
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVZIP-NEXT: vsseg3e32.v v8, (a0)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: srli a1, a1, 1
-; ZVZIP-NEXT: add a2, a0, a1
-; ZVZIP-NEXT: vle32.v v9, (a2)
+; ZVZIP-NEXT: addi a1, sp, 16
+; ZVZIP-NEXT: vle32.v v9, (a1)
; ZVZIP-NEXT: vle32.v v8, (a0)
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v9, 2
-; ZVZIP-NEXT: add a1, a2, a1
-; ZVZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a1)
+; ZVZIP-NEXT: addi a0, sp, 24
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v10, (a0)
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: add sp, sp, a0
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <6 x i32> @llvm.vector.interleave3.v6i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c)
ret <6 x i32> %res
@@ -256,95 +232,71 @@ define <6 x i32> @vector_interleave3_v6i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) nounwind {
; CHECK-LABEL: vector_interleave4_v8i32_v2i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: mv a0, sp
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vsseg4e32.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: add a1, a3, a1
+; CHECK-NEXT: addi a1, sp, 24
; CHECK-NEXT: vle32.v v9, (a1)
-; CHECK-NEXT: vle32.v v10, (a2)
+; CHECK-NEXT: addi a1, sp, 8
+; CHECK-NEXT: vle32.v v10, (a1)
; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
-; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT: vle32.v v10, (a3)
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v10, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 4
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave4_v8i32_v2i32:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: addi sp, sp, -16
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: sub sp, sp, a0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVBB-NEXT: addi sp, sp, -32
+; ZVBB-NEXT: mv a0, sp
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVBB-NEXT: vsseg4e32.v v8, (a0)
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: srli a1, a1, 1
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: add a1, a3, a1
+; ZVBB-NEXT: addi a1, sp, 24
; ZVBB-NEXT: vle32.v v9, (a1)
-; ZVBB-NEXT: vle32.v v10, (a2)
+; ZVBB-NEXT: addi a1, sp, 8
+; ZVBB-NEXT: vle32.v v10, (a1)
; ZVBB-NEXT: vle32.v v8, (a0)
+; ZVBB-NEXT: addi a0, sp, 16
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 2
-; ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVBB-NEXT: vle32.v v10, (a3)
+; ZVBB-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB-NEXT: vle32.v v10, (a0)
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v10, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 4
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: add sp, sp, a0
-; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave4_v8i32_v2i32:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: sub sp, sp, a0
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVZIP-NEXT: addi sp, sp, -32
+; ZVZIP-NEXT: mv a0, sp
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; ZVZIP-NEXT: vsseg4e32.v v8, (a0)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: srli a1, a1, 1
-; ZVZIP-NEXT: add a2, a0, a1
-; ZVZIP-NEXT: add a3, a2, a1
-; ZVZIP-NEXT: add a1, a3, a1
+; ZVZIP-NEXT: addi a1, sp, 24
; ZVZIP-NEXT: vle32.v v9, (a1)
-; ZVZIP-NEXT: vle32.v v10, (a2)
+; ZVZIP-NEXT: addi a1, sp, 8
+; ZVZIP-NEXT: vle32.v v10, (a1)
; ZVZIP-NEXT: vle32.v v8, (a0)
+; ZVZIP-NEXT: addi a0, sp, 16
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 2
-; ZVZIP-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; ZVZIP-NEXT: vle32.v v10, (a3)
+; ZVZIP-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVZIP-NEXT: vle32.v v10, (a0)
; ZVZIP-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v10, v9, 2
; ZVZIP-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 4
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: add sp, sp, a0
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <8 x i32> @llvm.vector.interleave4.v8i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d)
ret <8 x i32> %res
@@ -353,104 +305,80 @@ define <8 x i32> @vector_interleave4_v8i32_v2i32(<2 x i32> %a, <2 x i32> %b, <2
define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e) nounwind {
; CHECK-LABEL: vector_interleave5_v10i16_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: addi a0, sp, 12
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsseg5e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: vle16.v v9, (a2)
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: vle16.v v11, (a2)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: addi a1, sp, 24
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: addi a1, sp, 20
+; CHECK-NEXT: vle16.v v11, (a1)
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: vslideup.vi v8, v9, 2
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v11, 4
-; CHECK-NEXT: add a1, a3, a1
-; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: addi a0, sp, 28
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 8
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
;
; ZVBB-LABEL: vector_interleave5_v10i16_v2i16:
; ZVBB: # %bb.0:
-; ZVBB-NEXT: addi sp, sp, -16
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: sub sp, sp, a0
-; ZVBB-NEXT: addi a0, sp, 16
-; ZVBB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVBB-NEXT: addi sp, sp, -32
+; ZVBB-NEXT: addi a0, sp, 12
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVBB-NEXT: vsseg5e16.v v8, (a0)
-; ZVBB-NEXT: csrr a1, vlenb
-; ZVBB-NEXT: srli a1, a1, 2
-; ZVBB-NEXT: add a2, a0, a1
-; ZVBB-NEXT: vle16.v v9, (a2)
-; ZVBB-NEXT: add a2, a2, a1
-; ZVBB-NEXT: add a3, a2, a1
-; ZVBB-NEXT: vle16.v v10, (a3)
-; ZVBB-NEXT: vle16.v v11, (a2)
+; ZVBB-NEXT: addi a1, sp, 16
+; ZVBB-NEXT: vle16.v v9, (a1)
+; ZVBB-NEXT: addi a1, sp, 24
+; ZVBB-NEXT: vle16.v v10, (a1)
+; ZVBB-NEXT: addi a1, sp, 20
+; ZVBB-NEXT: vle16.v v11, (a1)
; ZVBB-NEXT: vle16.v v8, (a0)
; ZVBB-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVBB-NEXT: vslideup.vi v11, v10, 2
; ZVBB-NEXT: vslideup.vi v8, v9, 2
; ZVBB-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v11, 4
-; ZVBB-NEXT: add a1, a3, a1
-; ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVBB-NEXT: vle16.v v10, (a1)
+; ZVBB-NEXT: addi a0, sp, 28
+; ZVBB-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVBB-NEXT: vle16.v v10, (a0)
; ZVBB-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVBB-NEXT: vslideup.vi v8, v10, 8
-; ZVBB-NEXT: csrr a0, vlenb
-; ZVBB-NEXT: slli a0, a0, 1
-; ZVBB-NEXT: add sp, sp, a0
-; ZVBB-NEXT: addi sp, sp, 16
+; ZVBB-NEXT: addi sp, sp, 32
; ZVBB-NEXT: ret
;
; ZVZIP-LABEL: vector_interleave5_v10i16_v2i16:
; ZVZIP: # %bb.0:
-; ZVZIP-NEXT: addi sp, sp, -16
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: sub sp, sp, a0
-; ZVZIP-NEXT: addi a0, sp, 16
-; ZVZIP-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVZIP-NEXT: addi sp, sp, -32
+; ZVZIP-NEXT: addi a0, sp, 12
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; ZVZIP-NEXT: vsseg5e16.v v8, (a0)
-; ZVZIP-NEXT: csrr a1, vlenb
-; ZVZIP-NEXT: srli a1, a1, 2
-; ZVZIP-NEXT: add a2, a0, a1
-; ZVZIP-NEXT: vle16.v v9, (a2)
-; ZVZIP-NEXT: add a2, a2, a1
-; ZVZIP-NEXT: add a3, a2, a1
-; ZVZIP-NEXT: vle16.v v10, (a3)
-; ZVZIP-NEXT: vle16.v v11, (a2)
+; ZVZIP-NEXT: addi a1, sp, 16
+; ZVZIP-NEXT: vle16.v v9, (a1)
+; ZVZIP-NEXT: addi a1, sp, 24
+; ZVZIP-NEXT: vle16.v v10, (a1)
+; ZVZIP-NEXT: addi a1, sp, 20
+; ZVZIP-NEXT: vle16.v v11, (a1)
; ZVZIP-NEXT: vle16.v v8, (a0)
; ZVZIP-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVZIP-NEXT: vslideup.vi v11, v10, 2
; ZVZIP-NEXT: vslideup.vi v8, v9, 2
; ZVZIP-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v11, 4
-; ZVZIP-NEXT: add a1, a3, a1
-; ZVZIP-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVZIP-NEXT: vle16.v v10, (a1)
+; ZVZIP-NEXT: addi a0, sp, 28
+; ZVZIP-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVZIP-NEXT: vle16.v v10, (a0)
; ZVZIP-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; ZVZIP-NEXT: vslideup.vi v8, v10, 8
-; ZVZIP-NEXT: csrr a0, vlenb
-; ZVZIP-NEXT: slli a0, a0, 1
-; ZVZIP-NEXT: add sp, sp, a0
-; ZVZIP-NEXT: addi sp, sp, 16
+; ZVZIP-NEXT: addi sp, sp, 32
; ZVZIP-NEXT: ret
%res = call <10 x i16> @llvm.vector.interleave5.v10i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e)
ret <10 x i16> %res
@@ -459,119 +387,95 @@ define <10 x i16> @vector_interleave5_v10i16_v2i16(<2 x i16> %a, <2 x i16> %b, <
define <12 x i16> @vector_interleave6_v12i16_v2i16(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d, <2 x i16> %e, <2 x i16> %f) nounwind {
; CHECK-LABEL: vector_interleave6_v12i16_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 1
-; CHECK-NEXT: sub sp, sp, a0
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; CHECK-NEXT: addi sp, sp, -32
+; CHECK-NEXT: addi a0, sp, 8
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vsseg6e16.v v8, (a0)
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: srli a1, a1, 2
-; CHECK-NEXT: add a2, a0, a1
-; CHECK-NEXT: vle16.v v9, (a2)
-; CHECK-NEXT: add a2, a2, a1
-; CHECK-NEXT: add a3, a2, a1
-; CHECK-NEXT: vle16.v v10, (a3)
-; CHECK-NEXT: vle16.v v11, (a2)
+; CHECK-NEXT: addi a1, sp, 12
+; CHECK-NEXT: vle16.v v9, (a1)
+; CHECK-NEXT: addi a1, sp, 20
+; CHECK-NEXT: vle16.v v10, (a1)
+; CHECK-NEXT: addi a1, sp, 16
+; CHECK-NEXT: vle16.v v11, (a1)
; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-N...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/213306
More information about the llvm-branch-commits
mailing list