[llvm-branch-commits] [llvm] [AMDGPU] Add support for sub-dword types for address space 13 (PR #213223)

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git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/AMDGPU/AMDGPULowerIdxOps.cpp llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUMachineInstrs.cpp llvm/lib/Target/AMDGPU/AMDGPUMachineInstrs.h llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp llvm/lib/Target/AMDGPU/SIISelLowering.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 03d430d5b..ebc4d6f2e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5235,8 +5235,8 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
   // The lowering of a VGPR "as memory" indexed access relies on it having
   // exactly one memory operand, since a sub-dword store synthesizes a load
   // operand from it, and on the index carrying no subregister, since
-  // AMDGPUAssignIdxToM0 rewrites it in place to M0. That the access writes M0 is
-  // declared by the instruction itself, so it needs no check here.
+  // AMDGPUAssignIdxToM0 rewrites it in place to M0. That the access writes M0
+  // is declared by the instruction itself, so it needs no check here.
   if (auto *LdStIdx = dyn_cast<AMDGPUMI::VLoadStoreIdxInst>(&MI)) {
     if (MI.getNumMemOperands() != 1) {
       ErrInfo = "v_load/store_idx should have exactly one memory operand.";

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https://github.com/llvm/llvm-project/pull/213223