[llvm-branch-commits] [llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Gheorghe-Teodor Bercea via llvm-branch-commits]

doru1004 wrote:

Pushed an update: gfx9 was silently miscompiled (the lowering emitted `v_movrel[sd]` where `AMDGPUAssignIdxToM0` had bailed, so M0 was never written — fixed via `useVGPRIndexMode()` and verified), the pseudos now declare `Defs = [M0]` in TableGen so the manual post-selection handling in both selectors is gone, and the movrel verifier rules are no longer gated on `IsPreRA`.

Two things left for follow-ups: correct register liveness for the indexed registers (4th PR in this stack TODO) and moving the lowering out of the combiner.

https://github.com/llvm/llvm-project/pull/209541