[llvm-branch-commits] [llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Gheorghe-Teodor Bercea via llvm-branch-commits]

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@@ -1777,6 +1735,10 @@ void GCNPassConfig::addFastRegAlloc() {
 }
 
 void GCNPassConfig::addPreRegAlloc() {
+  // Set up M0 for the movrel that expands a VGPR "as memory" indexed access.
+  // Run before allocation so the index computation coalesces into M0.
+  addPass(&AMDGPUAssignIdxToM0ID);
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doru1004 wrote:

Can confirm it happens, actually checked.

https://github.com/llvm/llvm-project/pull/209541