[llvm-branch-commits] [llvm] release/23.x: [RISCV] Fix crash in convertToVLMAX when AVL is an ADDI of a frame index (#212923) (PR #212960)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: llvmbot

<details>
<summary>Changes</summary>

Backport ef7f2f611993a4bc59e181d2bf8fc6269d7e1c7d

Requested by: @<!-- -->wangpc-pp

---
Full diff: https://github.com/llvm/llvm-project/pull/212960.diff


2 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp (+1-1) 
- (added) llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir (+25) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index aabfd5506789f..6071006882b31 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -105,7 +105,7 @@ RISCVVectorPeephole::getConstant(const MachineOperand &VL) const {
     return VL.getImm();
 
   MachineInstr *Def = MRI->getVRegDef(VL.getReg());
-  if (!Def || Def->getOpcode() != RISCV::ADDI ||
+  if (!Def || Def->getOpcode() != RISCV::ADDI || !Def->getOperand(1).isReg() ||
       Def->getOperand(1).getReg() != RISCV::X0)
     return std::nullopt;
   return Def->getOperand(2).getImm();
diff --git a/llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir b/llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
new file mode 100644
index 0000000000000..d2c34b502941d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vlmax-peephole.mir
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole -verify-machineinstrs | FileCheck %s
+
+# The AVL is defined by an ADDI whose second operand is a frame index rather than
+# a register.
+
+---
+name: avl_addi_frameindex
+tracksRegLiveness: true
+stack:
+  - { id: 0, type: default, size: 1, alignment: 1 }
+body: |
+  bb.0:
+    ; CHECK-LABEL: name: avl_addi_frameindex
+    ; CHECK: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vr = IMPLICIT_DEF
+    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI %stack.0, 1
+    ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 $noreg, [[DEF]], [[DEF1]], killed [[ADDI]] /* vl */, 5 /* e32 */, 0 /* tu, mu */
+    ; CHECK-NEXT: PseudoRET implicit [[PseudoVADD_VV_M1_]]
+    %0:vr = IMPLICIT_DEF
+    %1:vr = IMPLICIT_DEF
+    %2:gprnox0 = ADDI %stack.0, 1
+    %3:vr = PseudoVADD_VV_M1 $noreg, %0, %1, killed %2, 5 /* e32 */, 0 /* tu, mu */
+    PseudoRET implicit %3
+...

``````````

</details>


https://github.com/llvm/llvm-project/pull/212960