[llvm-branch-commits] [llvm] [RISCV] Support CodeGen of Zilx extension (PR #209420)

[Craig Topper via llvm-branch-commits]

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@@ -93,3 +102,106 @@ let Predicates = [HasStdExtZilx] in {
 def : InstAlias<"lxb $rd, $rs2, $rs1",  (LXSB  GPR:$rd, GPRMemZeroOffset:$rs2, GPR:$rs1), 0>;
 def : InstAlias<"lxbu $rd, $rs2, $rs1", (LXSBU GPR:$rd, GPRMemZeroOffset:$rs2, GPR:$rs1), 0>;
 }
+
+//===----------------------------------------------------------------------===//
+// Pattern matching
+//===----------------------------------------------------------------------===//
+
+// The complexities below are chosen to give the indexed loads a strict
+// priority over the plain reg+imm loads and to encode which form is the more
+// specific match. Without an explicit complexity these patterns tie with the
+// base L{B,H,W,D}[U] patterns (which also match a "reg + reg" address as
+// base+0) and, being listed later, would never be selected. The required
+// ordering is:
+//   base L*  <  scale-0 (unscaled) Zilx  <  scaled Zilx
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topperc wrote:

Why are we calling it scale-0? Isn't unscaled equivalent to scale-1?

https://github.com/llvm/llvm-project/pull/209420