[llvm-branch-commits] [llvm] 0818e7f - Revert "[VectorCombine] Fold binop(shuffle(V1, Mask), shuffle(V2, Mask)) -> s…"
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Jul 25 00:15:14 PDT 2026
Author: Simon Pilgrim
Date: 2026-07-25T08:15:10+01:00
New Revision: 0818e7f74c67283dae7c6b2b765f2f7ddae75ff2
URL: https://github.com/llvm/llvm-project/commit/0818e7f74c67283dae7c6b2b765f2f7ddae75ff2
DIFF: https://github.com/llvm/llvm-project/commit/0818e7f74c67283dae7c6b2b765f2f7ddae75ff2.diff
LOG: Revert "[VectorCombine] Fold binop(shuffle(V1, Mask), shuffle(V2, Mask)) -> s…"
This reverts commit b7fa8b21227c7c6a1c625db9ceab4acb485c2e6b.
Added:
Modified:
llvm/lib/Transforms/Vectorize/VectorCombine.cpp
llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll
llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll
llvm/test/Transforms/VectorCombine/pr197910.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
index 7948eb47bc559..b5f5cd96f4aa5 100644
--- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
+++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp
@@ -125,7 +125,6 @@ class VectorCombine {
bool foldInsExtVectorToShuffle(Instruction &I);
bool foldBitOpOfCastops(Instruction &I);
bool foldBitOpOfCastConstant(Instruction &I);
- bool foldBinopOfShuffles(Instruction &I);
bool foldBitcastShuffle(Instruction &I);
bool scalarizeOpOrCmp(Instruction &I);
bool scalarizeVPIntrinsic(Instruction &I);
@@ -2444,70 +2443,6 @@ bool VectorCombine::foldConcatOfBoolMasks(Instruction &I) {
return true;
}
-/// Fold binop(shuffle(V0, Mask), shuffle(V1, Mask))
-/// --> shuffle(binop(V0, V1), Mask)
-bool VectorCombine::foldBinopOfShuffles(Instruction &I) {
- // It is not safe to transform things like div, urem, etc. because we may
- // create undefined behavior when executing those on unknown vector elements.
- if (!isSafeToSpeculativelyExecute(&I))
- return false;
-
- // If both arguments of the binary operation are shuffles that use the same
- // mask and shuffle within a single vector, move the shuffle after the binop.
- ArrayRef<int> Mask;
- Value *LHS, *RHS, *V0, *V1;
- if (!match(&I, m_BinOp(m_Value(LHS), m_Value(RHS))) ||
- !match(LHS, m_Shuffle(m_Value(V0), m_Poison(), m_Mask(Mask))) ||
- !match(RHS, m_Shuffle(m_Value(V1), m_Poison(), m_SpecificMask(Mask))))
- return false;
-
- if (V0->getType() != V1->getType())
- return false;
-
- auto *BO = cast<BinaryOperator>(&I);
- auto *OpTy = cast<VectorType>(V0->getType());
- auto *DstTy = cast<VectorType>(I.getType());
- Instruction::BinaryOps Opcode = BO->getOpcode();
-
- InstructionCost OldCost;
- OldCost += TTI.getInstructionCost(&I, CostKind);
- OldCost += TTI.getInstructionCost(cast<Instruction>(LHS), CostKind);
- if (LHS != RHS)
- OldCost += TTI.getInstructionCost(cast<Instruction>(RHS), CostKind);
-
- InstructionCost NewCost;
- NewCost += TTI.getArithmeticInstrCost(Opcode, OpTy, CostKind,
- TTI::getOperandInfo(V0),
- TTI::getOperandInfo(V1), {V0, V1});
- NewCost += TTI.getShuffleCost(TargetTransformInfo::SK_PermuteSingleSrc, DstTy,
- OpTy, Mask, CostKind);
-
- // Add multiple use costs (assuming the multiple use isn't just the BinOp).
- if (!(LHS == RHS && LHS->hasOneUser())) {
- if (!LHS->hasOneUse())
- NewCost += TTI.getInstructionCost(cast<Instruction>(LHS), CostKind);
- if (LHS != RHS && !RHS->hasOneUse())
- NewCost += TTI.getInstructionCost(cast<Instruction>(RHS), CostKind);
- }
-
- LLVM_DEBUG(dbgs() << "Found a binop of matching shuffles: " << I
- << "\n OldCost: " << OldCost << " vs NewCost: " << NewCost
- << "\n");
-
- // TODO: When to allow equal costs (as we reduce instruction count)?
- if (!NewCost.isValid() || NewCost >= OldCost)
- return false;
-
- Value *NewBO = Builder.CreateBinOp(Opcode, V0, V1);
- Value *NewShuffle = Builder.CreateShuffleVector(NewBO, Mask);
- if (auto *NewInst = dyn_cast<Instruction>(NewBO))
- NewInst->copyIRFlags(BO);
-
- Worklist.pushValue(NewBO);
- replaceValue(I, *NewShuffle);
- return true;
-}
-
/// Try to convert "shuffle (binop (shuffle, shuffle)), undef"
/// --> "binop (shuffle), (shuffle)".
bool VectorCombine::foldPermuteOfBinops(Instruction &I) {
@@ -6629,16 +6564,12 @@ bool VectorCombine::run() {
return true;
if (foldBitOpOfCastConstant(I))
return true;
- if (foldBinopOfShuffles(I))
- return true;
break;
case Instruction::PHI:
if (shrinkPhiOfShuffles(I))
return true;
break;
default:
- if (foldBinopOfShuffles(I))
- return true;
if (shrinkType(I))
return true;
break;
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll b/llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
index daf2c8f3e87f6..43e538e14058d 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/fmaddsub.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE4
-; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA4
-; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA3
+; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA,AVX_FMA4
+; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA,AVX_FMA3
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -passes="default<O3>" -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
; RUN: opt < %s -passes="default<O3>" -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE4
-; RUN: opt < %s -passes="default<O3>" -S -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA4
-; RUN: opt < %s -passes="default<O3>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA3
+; RUN: opt < %s -passes="default<O3>" -S -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA,AVX_FMA4
+; RUN: opt < %s -passes="default<O3>" -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX_FMA,AVX_FMA3
; RUN: opt < %s -passes="default<O3>" -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; This test checks the vectorisation of FMUL+ADDSUB/FMADDSUB patterns, including cases with undef elements.
@@ -469,14 +469,14 @@ define <8 x double> @buildvector_mul_addsub_pd512_partial(<8 x double> %C, <8 x
;
; AVX512-LABEL: @buildvector_mul_addsub_pd512_partial(
; AVX512-NEXT: [[A:%.*]] = fmul <8 x double> [[C:%.*]], [[D:%.*]]
-; AVX512-NEXT: [[TMP8:%.*]] = fsub <8 x double> [[A]], [[B:%.*]]
; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x double> [[A]], <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[B]], <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[B:%.*]], <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; AVX512-NEXT: [[TMP3:%.*]] = fsub <4 x double> [[TMP1]], [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]]
; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; AVX512-NEXT: [[TMP6:%.*]] = fadd <8 x double> [[A]], [[B]]
; AVX512-NEXT: [[TMP7:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> <double undef, double poison, double poison, double poison>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 4, i32 poison, i32 poison>
+; AVX512-NEXT: [[TMP8:%.*]] = fsub <8 x double> [[A]], [[B]]
; AVX512-NEXT: [[TMP9:%.*]] = shufflevector <8 x double> [[TMP8]], <8 x double> poison, <8 x i32> <i32 4, i32 poison, i32 6, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX512-NEXT: [[VECINSERT71:%.*]] = shufflevector <8 x double> [[TMP7]], <8 x double> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 10, i32 poison>
; AVX512-NEXT: [[VECINSERT8:%.*]] = shufflevector <8 x double> [[VECINSERT71]], <8 x double> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
@@ -578,16 +578,35 @@ define <8 x float> @buildvector_mul_subadd_ps256(<8 x float> %C, <8 x float> %D,
; SSE4-LABEL: @buildvector_mul_subadd_ps256(
; SSE4-NEXT: [[A:%.*]] = fmul <8 x float> [[C:%.*]], [[D:%.*]]
; SSE4-NEXT: [[TMP2:%.*]] = fadd <8 x float> [[A]], [[B:%.*]]
+; SSE4-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[TMP2]], <8 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>
; SSE4-NEXT: [[TMP5:%.*]] = fsub <8 x float> [[A]], [[B]]
-; SSE4-NEXT: [[TMP6:%.*]] = shufflevector <8 x float> [[TMP2]], <8 x float> [[TMP5]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; SSE4-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP5]], <8 x float> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
+; SSE4-NEXT: [[TMP6:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> [[TMP4]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
; SSE4-NEXT: ret <8 x float> [[TMP6]]
;
-; AVX-LABEL: @buildvector_mul_subadd_ps256(
-; AVX-NEXT: [[A:%.*]] = fmul <8 x float> [[C:%.*]], [[D:%.*]]
-; AVX-NEXT: [[TMP1:%.*]] = fadd <8 x float> [[A]], [[B:%.*]]
-; AVX-NEXT: [[TMP2:%.*]] = fsub <8 x float> [[A]], [[B]]
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
-; AVX-NEXT: ret <8 x float> [[TMP3]]
+; AVX_FMA4-LABEL: @buildvector_mul_subadd_ps256(
+; AVX_FMA4-NEXT: [[A:%.*]] = fmul <8 x float> [[C:%.*]], [[D:%.*]]
+; AVX_FMA4-NEXT: [[TMP2:%.*]] = fadd <8 x float> [[A]], [[B:%.*]]
+; AVX_FMA4-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[TMP2]], <8 x float> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX_FMA4-NEXT: [[TMP7:%.*]] = fsub <8 x float> [[A]], [[B]]
+; AVX_FMA4-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP7]], <8 x float> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX_FMA4-NEXT: [[TMP5:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+; AVX_FMA4-NEXT: [[TMP6:%.*]] = shufflevector <8 x float> [[TMP5]], <8 x float> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
+; AVX_FMA4-NEXT: ret <8 x float> [[TMP6]]
+;
+; AVX_FMA3-LABEL: @buildvector_mul_subadd_ps256(
+; AVX_FMA3-NEXT: [[A:%.*]] = fmul <8 x float> [[C:%.*]], [[D:%.*]]
+; AVX_FMA3-NEXT: [[TMP0:%.*]] = fadd <8 x float> [[A]], [[B:%.*]]
+; AVX_FMA3-NEXT: [[TMP1:%.*]] = fsub <8 x float> [[A]], [[B]]
+; AVX_FMA3-NEXT: [[TMP2:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; AVX_FMA3-NEXT: ret <8 x float> [[TMP2]]
+;
+; AVX512-LABEL: @buildvector_mul_subadd_ps256(
+; AVX512-NEXT: [[A:%.*]] = fmul <8 x float> [[C:%.*]], [[D:%.*]]
+; AVX512-NEXT: [[TMP0:%.*]] = fadd <8 x float> [[A]], [[B:%.*]]
+; AVX512-NEXT: [[TMP1:%.*]] = fsub <8 x float> [[A]], [[B]]
+; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x float> [[TMP0]], <8 x float> [[TMP1]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; AVX512-NEXT: ret <8 x float> [[TMP2]]
;
%A = fmul <8 x float> %C, %D
%A0 = extractelement <8 x float> %A, i32 0
@@ -665,12 +684,21 @@ define <16 x float> @buildvector_mul_subadd_ps512(<16 x float> %C, <16 x float>
; SSE-NEXT: [[VECINSERT161:%.*]] = shufflevector <8 x float> [[TMP2]], <8 x float> [[TMP4]], <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
; SSE-NEXT: ret <16 x float> [[VECINSERT161]]
;
-; AVX-LABEL: @buildvector_mul_subadd_ps512(
-; AVX-NEXT: [[A:%.*]] = fmul <16 x float> [[C:%.*]], [[D:%.*]]
-; AVX-NEXT: [[TMP1:%.*]] = fadd <16 x float> [[A]], [[B:%.*]]
-; AVX-NEXT: [[TMP2:%.*]] = fsub <16 x float> [[A]], [[B]]
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <16 x float> [[TMP1]], <16 x float> [[TMP2]], <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
-; AVX-NEXT: ret <16 x float> [[TMP3]]
+; AVX_FMA-LABEL: @buildvector_mul_subadd_ps512(
+; AVX_FMA-NEXT: [[A:%.*]] = fmul <16 x float> [[C:%.*]], [[D:%.*]]
+; AVX_FMA-NEXT: [[TMP3:%.*]] = fadd <16 x float> [[A]], [[B:%.*]]
+; AVX_FMA-NEXT: [[TMP4:%.*]] = shufflevector <16 x float> [[TMP3]], <16 x float> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX_FMA-NEXT: [[TMP5:%.*]] = fsub <16 x float> [[A]], [[B]]
+; AVX_FMA-NEXT: [[TMP6:%.*]] = shufflevector <16 x float> [[TMP5]], <16 x float> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX_FMA-NEXT: [[TMP7:%.*]] = shufflevector <16 x float> [[TMP4]], <16 x float> [[TMP6]], <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
+; AVX_FMA-NEXT: ret <16 x float> [[TMP7]]
+;
+; AVX512-LABEL: @buildvector_mul_subadd_ps512(
+; AVX512-NEXT: [[A:%.*]] = fmul <16 x float> [[C:%.*]], [[D:%.*]]
+; AVX512-NEXT: [[TMP1:%.*]] = fadd <16 x float> [[A]], [[B:%.*]]
+; AVX512-NEXT: [[TMP10:%.*]] = fsub <16 x float> [[A]], [[B]]
+; AVX512-NEXT: [[VECINSERT162:%.*]] = shufflevector <16 x float> [[TMP1]], <16 x float> [[TMP10]], <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
+; AVX512-NEXT: ret <16 x float> [[VECINSERT162]]
;
%A = fmul <16 x float> %C, %D
%A0 = extractelement <16 x float> %A, i32 0
@@ -859,12 +887,21 @@ define <8 x double> @buildvector_mul_subadd_pd512(<8 x double> %C, <8 x double>
; SSE-NEXT: [[VECINSERT8:%.*]] = shufflevector <4 x double> [[TMP1]], <4 x double> [[TMP4]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
; SSE-NEXT: ret <8 x double> [[VECINSERT8]]
;
-; AVX-LABEL: @buildvector_mul_subadd_pd512(
-; AVX-NEXT: [[A:%.*]] = fmul <8 x double> [[C:%.*]], [[D:%.*]]
-; AVX-NEXT: [[TMP1:%.*]] = fadd <8 x double> [[A]], [[B:%.*]]
-; AVX-NEXT: [[TMP2:%.*]] = fsub <8 x double> [[A]], [[B]]
-; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x double> [[TMP1]], <8 x double> [[TMP2]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
-; AVX-NEXT: ret <8 x double> [[TMP3]]
+; AVX_FMA-LABEL: @buildvector_mul_subadd_pd512(
+; AVX_FMA-NEXT: [[A:%.*]] = fmul <8 x double> [[C:%.*]], [[D:%.*]]
+; AVX_FMA-NEXT: [[TMP3:%.*]] = fadd <8 x double> [[A]], [[B:%.*]]
+; AVX_FMA-NEXT: [[TMP4:%.*]] = shufflevector <8 x double> [[TMP3]], <8 x double> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX_FMA-NEXT: [[TMP5:%.*]] = fsub <8 x double> [[A]], [[B]]
+; AVX_FMA-NEXT: [[TMP6:%.*]] = shufflevector <8 x double> [[TMP5]], <8 x double> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
+; AVX_FMA-NEXT: [[TMP7:%.*]] = shufflevector <8 x double> [[TMP4]], <8 x double> [[TMP6]], <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
+; AVX_FMA-NEXT: ret <8 x double> [[TMP7]]
+;
+; AVX512-LABEL: @buildvector_mul_subadd_pd512(
+; AVX512-NEXT: [[A:%.*]] = fmul <8 x double> [[C:%.*]], [[D:%.*]]
+; AVX512-NEXT: [[TMP7:%.*]] = fadd <8 x double> [[A]], [[B:%.*]]
+; AVX512-NEXT: [[TMP2:%.*]] = fsub <8 x double> [[A]], [[B]]
+; AVX512-NEXT: [[VECINSERT8:%.*]] = shufflevector <8 x double> [[TMP7]], <8 x double> [[TMP2]], <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
+; AVX512-NEXT: ret <8 x double> [[VECINSERT8]]
;
%A = fmul <8 x double> %C, %D
%A0 = extractelement <8 x double> %A, i32 0
@@ -955,14 +992,14 @@ define <8 x double> @buildvector_mul_subadd_pd512_partial(<8 x double> %C, <8 x
;
; AVX512-LABEL: @buildvector_mul_subadd_pd512_partial(
; AVX512-NEXT: [[A:%.*]] = fmul <8 x double> [[C:%.*]], [[D:%.*]]
-; AVX512-NEXT: [[TMP8:%.*]] = fadd <8 x double> [[A]], [[B:%.*]]
; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x double> [[A]], <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[B]], <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT: [[TMP2:%.*]] = shufflevector <8 x double> [[B:%.*]], <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; AVX512-NEXT: [[TMP3:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]]
; AVX512-NEXT: [[TMP4:%.*]] = fsub <4 x double> [[TMP1]], [[TMP2]]
; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <4 x double> [[TMP3]], <4 x double> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
; AVX512-NEXT: [[TMP6:%.*]] = fsub <8 x double> [[A]], [[B]]
; AVX512-NEXT: [[TMP7:%.*]] = shufflevector <4 x double> [[TMP5]], <4 x double> <double undef, double poison, double poison, double poison>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 4, i32 poison, i32 poison>
+; AVX512-NEXT: [[TMP8:%.*]] = fadd <8 x double> [[A]], [[B]]
; AVX512-NEXT: [[TMP9:%.*]] = shufflevector <8 x double> [[TMP8]], <8 x double> poison, <8 x i32> <i32 4, i32 poison, i32 6, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX512-NEXT: [[VECINSERT71:%.*]] = shufflevector <8 x double> [[TMP7]], <8 x double> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 10, i32 poison>
; AVX512-NEXT: [[VECINSERT8:%.*]] = shufflevector <8 x double> [[VECINSERT71]], <8 x double> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
diff --git a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
index f27d752ea9cf9..9364b4efa8931 100644
--- a/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
+++ b/llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll
@@ -261,9 +261,10 @@ define <8 x half> @splatandidentity(<8 x half> %a, <8 x half> %b) {
define <8 x half> @splattwice(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: @splattwice(
-; CHECK-NEXT: [[R:%.*]] = fadd <8 x half> [[TMP1:%.*]], [[TMP2:%.*]]
-; CHECK-NEXT: [[R1:%.*]] = shufflevector <8 x half> [[R]], <8 x half> poison, <8 x i32> zeroinitializer
-; CHECK-NEXT: ret <8 x half> [[R1]]
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x half> [[A:%.*]], <8 x half> poison, <8 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x half> [[B:%.*]], <8 x half> poison, <8 x i32> zeroinitializer
+; CHECK-NEXT: [[R:%.*]] = fadd <8 x half> [[TMP1]], [[TMP2]]
+; CHECK-NEXT: ret <8 x half> [[R]]
;
%as = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> zeroinitializer
%bs = shufflevector <8 x half> %b, <8 x half> poison, <4 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll b/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll
index dc70d729ab9c0..5373f6c07be31 100644
--- a/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/permute-of-binops.ll
@@ -104,9 +104,11 @@ declare void @use_v32i8(<32 x i8>)
define <32 x i8> @max_expense_multi_use_triggered(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: define <32 x i8> @max_expense_multi_use_triggered(
; CHECK-SAME: <32 x i8> [[A:%.*]], <32 x i8> [[B:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[POST:%.*]] = add <32 x i8> [[A]], [[B]]
-; CHECK-NEXT: [[OP:%.*]] = shufflevector <32 x i8> [[POST]], <32 x i8> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[A1:%.*]] = shufflevector <32 x i8> [[A]], <32 x i8> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[B1:%.*]] = shufflevector <32 x i8> [[B]], <32 x i8> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT: [[OP:%.*]] = add <32 x i8> [[A1]], [[B1]]
; CHECK-NEXT: call void @use_v32i8(<32 x i8> [[OP]])
+; CHECK-NEXT: [[POST:%.*]] = add <32 x i8> [[A]], [[B]]
; CHECK-NEXT: ret <32 x i8> [[POST]]
;
%a1 = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll b/llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll
index a51fdb6d0ee09..ba145ecf02cb1 100644
--- a/llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll
+++ b/llvm/test/Transforms/VectorCombine/X86/shuffletoidentity-bitcast.ll
@@ -265,17 +265,18 @@ define <4 x i32> @bitcast_poison_lanes(<4 x i32> %a) {
; Negative test:
diff erent operations on halves should not fold.
define <4 x i32> @bitcast_
diff erent_ops_neg(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: @bitcast_
diff erent_ops_neg(
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x i64>
-; CHECK-NEXT: [[BC_A_LO:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> poison, <1 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[A:%.*]] to <2 x i64>
+; CHECK-NEXT: [[BC_A_LO:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <1 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>
+; CHECK-NEXT: [[BC_A_HI:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[B:%.*]] to <2 x i64>
; CHECK-NEXT: [[BC_B_LO:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> poison, <1 x i32> zeroinitializer
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>
+; CHECK-NEXT: [[BC_B_HI:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[ADD_LO:%.*]] = add <1 x i64> [[BC_A_LO]], [[BC_B_LO]]
-; CHECK-NEXT: [[DOTINNER:%.*]] = xor <4 x i32> [[A]], [[B]]
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[DOTINNER]] to <2 x i64>
-; CHECK-NEXT: [[RES_LO:%.*]] = bitcast <1 x i64> [[ADD_LO]] to <2 x i32>
-; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP4]] to <4 x i32>
-; CHECK-NEXT: [[RES_HI:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
-; CHECK-NEXT: [[RESULT:%.*]] = shufflevector <2 x i32> [[RES_LO]], <2 x i32> [[RES_HI]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[XOR_HI:%.*]] = xor <1 x i64> [[BC_A_HI]], [[BC_B_HI]]
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <1 x i64> [[ADD_LO]], <1 x i64> [[XOR_HI]], <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: [[RESULT:%.*]] = bitcast <2 x i64> [[TMP5]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[RESULT]]
;
%a_lo = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
diff --git a/llvm/test/Transforms/VectorCombine/pr197910.ll b/llvm/test/Transforms/VectorCombine/pr197910.ll
index 46519daea5acd..8a3d50faf9260 100644
--- a/llvm/test/Transforms/VectorCombine/pr197910.ll
+++ b/llvm/test/Transforms/VectorCombine/pr197910.ll
@@ -14,14 +14,15 @@ define <8 x i32> @PR197910(<8 x i32> %arg) {
; CHECK-NEXT: [[S6:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: [[S7:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> [[B]], <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 13, i32 14, i32 7>
; CHECK-NEXT: [[S8:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> [[B]], <8 x i32> <i32 8, i32 1, i32 2, i32 11, i32 12, i32 5, i32 6, i32 15>
+; CHECK-NEXT: [[U1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <8 x i32> zeroinitializer
+; CHECK-NEXT: [[U6:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: [[R12:%.*]] = add <8 x i32> [[S2]], [[S3]]
; CHECK-NEXT: [[R34:%.*]] = add <8 x i32> [[S4]], [[S5]]
; CHECK-NEXT: [[R56:%.*]] = add <8 x i32> [[S6]], [[S7]]
; CHECK-NEXT: [[R1234:%.*]] = add <8 x i32> [[R12]], [[R34]]
; CHECK-NEXT: [[R123456:%.*]] = add <8 x i32> [[R1234]], [[R56]]
; CHECK-NEXT: [[R1234567:%.*]] = add <8 x i32> [[R123456]], [[S8]]
-; CHECK-NEXT: [[TMP1:%.*]] = add <8 x i32> [[A]], [[A]]
-; CHECK-NEXT: [[RU:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
+; CHECK-NEXT: [[RU:%.*]] = add <8 x i32> [[U1]], [[U6]]
; CHECK-NEXT: [[RET:%.*]] = add <8 x i32> [[R1234567]], [[RU]]
; CHECK-NEXT: ret <8 x i32> [[RET]]
;
More information about the llvm-branch-commits
mailing list