[llvm-branch-commits] [llvm] X86: Use ProcessorAlias for duplicated processor names (PR #211953)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jul 24 23:26:02 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/211953
>From 5fb49102f2441fc4f29495b2d72769f5b21f101c Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 24 Jul 2026 19:30:39 +0200
Subject: [PATCH 1/2] X86: Use ProcessorAlias for duplicated processor names
Many X86 processors were defined multiple times under different names,
emitting an identical ProcessorModel for each spelling and duplicating
the feature masks, tune features, and scheduling model index in the subtype
table.
Define each processor once under its canonical name and express the
alternate spellings with ProcessorAlias, using the tablegen alias
mechanism. This deduplicates the redundant subtype table entries and saves
about 4.6k with the new alias table.
Co-Authored-By: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
---
llvm/lib/Target/X86/X86.td | 263 +++++++++++++++++--------------------
1 file changed, 124 insertions(+), 139 deletions(-)
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 95dafc31d6b44..cf9032c6241c1 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1899,26 +1899,24 @@ def : Proc<"i586", [FeatureX87, FeatureCX8],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"pentium", [FeatureX87, FeatureCX8],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-foreach P = ["pentium-mmx", "pentium_mmx"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX],
- [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
+def : Proc<"pentium-mmx", [FeatureX87, FeatureCX8, FeatureMMX],
+ [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"pentium_mmx", "pentium-mmx">;
def : Proc<"i686", [FeatureX87, FeatureCX8, FeatureCMOV],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-foreach P = ["pentiumpro", "pentium_pro"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, FeatureNOPL],
- [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
-foreach P = ["pentium2", "pentium_ii"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX, FeatureCMOV,
- FeatureFXSR, FeatureNOPL],
- [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
-foreach P = ["pentium3", "pentium3m", "pentium_iii_no_xmm_regs", "pentium_iii"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX,
- FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
- [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
+def : Proc<"pentiumpro", [FeatureX87, FeatureCX8, FeatureCMOV, FeatureNOPL],
+ [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"pentium_pro", "pentiumpro">;
+def : Proc<"pentium2", [FeatureX87, FeatureCX8, FeatureMMX, FeatureCMOV,
+ FeatureFXSR, FeatureNOPL],
+ [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"pentium_ii", "pentium2">;
+def : Proc<"pentium3", [FeatureX87, FeatureCX8, FeatureMMX,
+ FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
+ [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"pentium3m", "pentium3">;
+def : ProcessorAlias<"pentium_iii_no_xmm_regs", "pentium3">;
+def : ProcessorAlias<"pentium_iii", "pentium3">;
// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
// The intent is to enable it for pentium4 which is the current default
@@ -1930,19 +1928,18 @@ foreach P = ["pentium3", "pentium3m", "pentium_iii_no_xmm_regs", "pentium_iii"]
// measure to avoid performance surprises, in case clang's default cpu
// changes slightly.
-foreach P = ["pentium_m", "pentium-m"] in {
-def : ProcModel<P, GenericPostRAModel,
+def : ProcModel<"pentium_m", GenericPostRAModel,
[FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
FeatureFXSR, FeatureNOPL, FeatureCMOV],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
+def : ProcessorAlias<"pentium-m", "pentium_m">;
-foreach P = ["pentium4", "pentium4m", "pentium_4"] in {
- def : ProcModel<P, GenericPostRAModel,
- [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
- FeatureFXSR, FeatureNOPL, FeatureCMOV],
- [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
+def : ProcModel<"pentium4", GenericPostRAModel,
+ [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
+ FeatureFXSR, FeatureNOPL, FeatureCMOV],
+ [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"pentium4m", "pentium4">;
+def : ProcessorAlias<"pentium_4", "pentium4">;
// Intel Quark.
def : Proc<"lakemont", [FeatureCX8],
@@ -1955,12 +1952,11 @@ def : ProcModel<"yonah", SandyBridgeModel,
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
// NetBurst.
-foreach P = ["prescott", "pentium_4_sse3"] in {
- def : ProcModel<P, GenericPostRAModel,
- [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
- FeatureFXSR, FeatureNOPL, FeatureCMOV],
- [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
+def : ProcModel<"prescott", GenericPostRAModel,
+ [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
+ FeatureFXSR, FeatureNOPL, FeatureCMOV],
+ [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"pentium_4_sse3", "prescott">;
def : ProcModel<"nocona", GenericPostRAModel, [
FeatureX87,
FeatureCX8,
@@ -1978,8 +1974,7 @@ def : ProcModel<"nocona", GenericPostRAModel, [
]>;
// Intel Core 2 Solo/Duo.
-foreach P = ["core2", "core_2_duo_ssse3"] in {
-def : ProcModel<P, SandyBridgeModel, [
+def : ProcModel<"core2", SandyBridgeModel, [
FeatureX87,
FeatureCX8,
FeatureCMOV,
@@ -1996,9 +1991,8 @@ def : ProcModel<P, SandyBridgeModel, [
TuningSlowUAMem16,
TuningInsertVZEROUPPER
]>;
-}
-foreach P = ["penryn", "core_2_duo_sse4_1"] in {
-def : ProcModel<P, SandyBridgeModel, [
+def : ProcessorAlias<"core_2_duo_ssse3", "core2">;
+def : ProcModel<"penryn", SandyBridgeModel, [
FeatureX87,
FeatureCX8,
FeatureCMOV,
@@ -2015,77 +2009,74 @@ def : ProcModel<P, SandyBridgeModel, [
TuningSlowUAMem16,
TuningInsertVZEROUPPER
]>;
-}
+def : ProcessorAlias<"core_2_duo_sse4_1", "penryn">;
// Atom CPUs.
-foreach P = ["bonnell", "atom"] in {
- def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,
- ProcessorFeatures.AtomTuning>;
-}
+def : ProcModel<"bonnell", AtomModel, ProcessorFeatures.AtomFeatures,
+ ProcessorFeatures.AtomTuning>;
+def : ProcessorAlias<"atom", "bonnell">;
-foreach P = ["silvermont", "slm", "atom_sse4_2"] in {
- def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures,
- ProcessorFeatures.SLMTuning>;
-}
+def : ProcModel<"silvermont", SLMModel, ProcessorFeatures.SLMFeatures,
+ ProcessorFeatures.SLMTuning>;
+def : ProcessorAlias<"slm", "silvermont">;
+def : ProcessorAlias<"atom_sse4_2", "silvermont">;
def : ProcModel<"atom_sse4_2_movbe", SLMModel, ProcessorFeatures.GLMFeatures,
ProcessorFeatures.SLMTuning>;
def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,
ProcessorFeatures.GLMTuning>;
-foreach P = ["goldmont_plus", "goldmont-plus"] in {
- def : ProcModel<P, SLMModel, ProcessorFeatures.GLPFeatures,
- ProcessorFeatures.GLPTuning>;
-}
+def : ProcModel<"goldmont_plus", SLMModel, ProcessorFeatures.GLPFeatures,
+ ProcessorFeatures.GLPTuning>;
+def : ProcessorAlias<"goldmont-plus", "goldmont_plus">;
def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
ProcessorFeatures.TRMTuning>;
// "Arrandale" along with corei3 and corei5
-foreach P = ["nehalem", "corei7", "core_i7_sse4_2"] in {
- def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,
- ProcessorFeatures.NHMTuning>;
-}
+def : ProcModel<"nehalem", SandyBridgeModel, ProcessorFeatures.NHMFeatures,
+ ProcessorFeatures.NHMTuning>;
+def : ProcessorAlias<"corei7", "nehalem">;
+def : ProcessorAlias<"core_i7_sse4_2", "nehalem">;
// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
-foreach P = ["westmere", "core_aes_pclmulqdq"] in {
- def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.WSMFeatures,
- ProcessorFeatures.WSMTuning>;
-}
-
-foreach P = ["sandybridge", "corei7-avx", "core_2nd_gen_avx"] in {
- def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures,
- ProcessorFeatures.SNBTuning>;
-}
-
-foreach P = ["ivybridge", "core-avx-i", "core_3rd_gen_avx"] in {
- def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures,
- ProcessorFeatures.IVBTuning>;
-}
-
-foreach P = ["haswell", "core-avx2", "core_4th_gen_avx", "core_4th_gen_avx_tsx"] in {
- def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures,
- ProcessorFeatures.HSWTuning>;
-}
-
-foreach P = ["broadwell", "core_5th_gen_avx", "core_5th_gen_avx_tsx"] in {
- def : ProcModel<P, BroadwellModel, ProcessorFeatures.BDWFeatures,
- ProcessorFeatures.BDWTuning>;
-}
+def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures,
+ ProcessorFeatures.WSMTuning>;
+def : ProcessorAlias<"core_aes_pclmulqdq", "westmere">;
+
+def : ProcModel<"sandybridge", SandyBridgeModel, ProcessorFeatures.SNBFeatures,
+ ProcessorFeatures.SNBTuning>;
+def : ProcessorAlias<"corei7-avx", "sandybridge">;
+def : ProcessorAlias<"core_2nd_gen_avx", "sandybridge">;
+
+def : ProcModel<"ivybridge", SandyBridgeModel, ProcessorFeatures.IVBFeatures,
+ ProcessorFeatures.IVBTuning>;
+def : ProcessorAlias<"core-avx-i", "ivybridge">;
+def : ProcessorAlias<"core_3rd_gen_avx", "ivybridge">;
+
+def : ProcModel<"haswell", HaswellModel, ProcessorFeatures.HSWFeatures,
+ ProcessorFeatures.HSWTuning>;
+def : ProcessorAlias<"core-avx2", "haswell">;
+def : ProcessorAlias<"core_4th_gen_avx", "haswell">;
+def : ProcessorAlias<"core_4th_gen_avx_tsx", "haswell">;
+
+def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures,
+ ProcessorFeatures.BDWTuning>;
+def : ProcessorAlias<"core_5th_gen_avx", "broadwell">;
+def : ProcessorAlias<"core_5th_gen_avx_tsx", "broadwell">;
def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures,
ProcessorFeatures.SKLTuning>;
// FIXME: define KNL scheduler model
-foreach P = ["knl", "mic_avx512"] in {
- def : ProcModel<P, HaswellModel, ProcessorFeatures.KNLFeatures,
- ProcessorFeatures.KNLTuning>;
-}
+def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures,
+ ProcessorFeatures.KNLTuning>;
+def : ProcessorAlias<"mic_avx512", "knl">;
def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures,
ProcessorFeatures.KNLTuning>;
-foreach P = ["skylake-avx512", "skx", "skylake_avx512"] in {
- def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures,
- ProcessorFeatures.SKXTuning>;
-}
+def : ProcModel<"skylake-avx512", SkylakeServerModel, ProcessorFeatures.SKXFeatures,
+ ProcessorFeatures.SKXTuning>;
+def : ProcessorAlias<"skx", "skylake-avx512">;
+def : ProcessorAlias<"skylake_avx512", "skylake-avx512">;
def : ProcModel<"cascadelake", SkylakeServerModel,
ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>;
@@ -2093,16 +2084,14 @@ def : ProcModel<"cooperlake", SkylakeServerModel,
ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;
def : ProcModel<"cannonlake", SkylakeServerModel,
ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
-foreach P = ["icelake-client", "icelake_client"] in {
-def : ProcModel<P, IceLakeModel,
+def : ProcModel<"icelake-client", IceLakeModel,
ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
-}
+def : ProcessorAlias<"icelake_client", "icelake-client">;
def : ProcModel<"rocketlake", IceLakeModel,
ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
-foreach P = ["icelake-server", "icelake_server"] in {
-def : ProcModel<P, IceLakeModel,
+def : ProcModel<"icelake-server", IceLakeModel,
ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
-}
+def : ProcessorAlias<"icelake_server", "icelake-server">;
def : ProcModel<"tigerlake", IceLakeModel,
ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
def : ProcModel<"sapphirerapids", SapphireRapidsModel,
@@ -2112,26 +2101,23 @@ def : ProcModel<"alderlake", AlderlakePModel,
// FIXME: Use Gracemont Schedule Model when it is ready.
def : ProcModel<"gracemont", AlderlakePModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.GRTTuning>;
-foreach P = ["sierraforest", "grandridge"] in {
- def : ProcModel<P, AlderlakePModel, ProcessorFeatures.SRFFeatures,
+def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
ProcessorFeatures.GRTTuning>;
-}
+def : ProcessorAlias<"grandridge", "sierraforest">;
def : ProcModel<"raptorlake", AlderlakePModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
def : ProcModel<"meteorlake", AlderlakePModel,
ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
def : ProcModel<"arrowlake", AlderlakePModel,
ProcessorFeatures.ARLFeatures, ProcessorFeatures.ADLTuning>;
-foreach P = ["arrowlake-s", "arrowlake_s"] in {
-def : ProcModel<P, AlderlakePModel,
+def : ProcModel<"arrowlake-s", AlderlakePModel,
ProcessorFeatures.ARLSFeatures, ProcessorFeatures.ADLTuning>;
-}
+def : ProcessorAlias<"arrowlake_s", "arrowlake-s">;
def : ProcModel<"lunarlake", LunarlakePModel, ProcessorFeatures.ARLSFeatures,
ProcessorFeatures.ADLTuning>;
-foreach P = ["pantherlake", "wildcatlake"] in {
-def : ProcModel<P, AlderlakePModel,
+def : ProcModel<"pantherlake", AlderlakePModel,
ProcessorFeatures.PTLFeatures, ProcessorFeatures.ADLTuning>;
-}
+def : ProcessorAlias<"wildcatlake", "pantherlake">;
def : ProcModel<"novalake", AlderlakePModel, ProcessorFeatures.NVLFeatures,
ProcessorFeatures.NVLTuning>;
@@ -2141,10 +2127,9 @@ def : ProcModel<"emeraldrapids", SapphireRapidsModel,
ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
def : ProcModel<"graniterapids", SapphireRapidsModel,
ProcessorFeatures.GNRFeatures, ProcessorFeatures.GNRTuning>;
-foreach P = ["graniterapids-d", "graniterapids_d"] in {
-def : ProcModel<P, SapphireRapidsModel,
+def : ProcModel<"graniterapids-d", SapphireRapidsModel,
ProcessorFeatures.GNRDFeatures, ProcessorFeatures.GNRTuning>;
-}
+def : ProcessorAlias<"graniterapids_d", "graniterapids-d">;
def : ProcModel<"diamondrapids", SapphireRapidsModel,
ProcessorFeatures.DMRFeatures, ProcessorFeatures.DMRTuning>;
@@ -2157,37 +2142,38 @@ def : Proc<"k6-2", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
def : Proc<"k6-3", [FeatureX87, FeatureCX8, FeatureMMX, FeaturePRFCHW],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-foreach P = ["athlon", "athlon-tbird"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX, FeaturePRFCHW,
- FeatureNOPL],
- [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
-
-foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV,
- FeatureSSE1, FeatureMMX, FeaturePRFCHW, FeatureFXSR, FeatureNOPL],
- [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-}
-
-foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2, FeatureMMX, FeaturePRFCHW,
- FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV],
- [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
- TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
-}
-
-foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
- def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3, FeatureMMX, FeaturePRFCHW,
- FeatureFXSR, FeatureNOPL, FeatureCX16, FeatureCMOV,
- FeatureX86_64],
- [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
- TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
-}
-
-foreach P = ["amdfam10", "barcelona"] in {
- def : Proc<P, ProcessorFeatures.BarcelonaFeatures,
- ProcessorFeatures.BarcelonaTuning>;
-}
+def : Proc<"athlon", [FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX,
+ FeaturePRFCHW, FeatureNOPL],
+ [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"athlon-tbird", "athlon">;
+
+def : Proc<"athlon-4", [FeatureX87, FeatureCX8, FeatureCMOV,
+ FeatureSSE1, FeatureMMX, FeaturePRFCHW, FeatureFXSR,
+ FeatureNOPL],
+ [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"athlon-xp", "athlon-4">;
+def : ProcessorAlias<"athlon-mp", "athlon-4">;
+
+def : Proc<"k8", [FeatureX87, FeatureCX8, FeatureSSE2, FeatureMMX, FeaturePRFCHW,
+ FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV],
+ [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
+ TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"opteron", "k8">;
+def : ProcessorAlias<"athlon64", "k8">;
+def : ProcessorAlias<"athlon-fx", "k8">;
+
+def : Proc<"k8-sse3", [FeatureX87, FeatureCX8, FeatureSSE3, FeatureMMX,
+ FeaturePRFCHW, FeatureFXSR, FeatureNOPL, FeatureCX16,
+ FeatureCMOV, FeatureX86_64],
+ [TuningFastScalarShiftMasks, TuningSlowSHLD,
+ TuningSlowUAMem16, TuningSBBDepBreaking,
+ TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"opteron-sse3", "k8-sse3">;
+def : ProcessorAlias<"athlon64-sse3", "k8-sse3">;
+
+def : Proc<"amdfam10", ProcessorFeatures.BarcelonaFeatures,
+ ProcessorFeatures.BarcelonaTuning>;
+def : ProcessorAlias<"barcelona", "amdfam10">;
// Bobcat
def : Proc<"btver1", ProcessorFeatures.BtVer1Features,
@@ -2226,10 +2212,9 @@ def : ProcModel<"znver6", Znver4Model, ProcessorFeatures.ZN6Features,
// Hygon CPUs.
-foreach P = ["c86-4g-m4", "c86-4g-m6"] in {
-def : ProcModel<P, C864GM4Model, ProcessorFeatures.C864GM4Features,
+def : ProcModel<"c86-4g-m4", C864GM4Model, ProcessorFeatures.C864GM4Features,
ProcessorFeatures.C864GM4Tuning>;
-}
+def : ProcessorAlias<"c86-4g-m6", "c86-4g-m4">;
def : ProcModel<"c86-4g-m7", C864GM7Model, ProcessorFeatures.C864GM7Features,
ProcessorFeatures.C864GM7Tuning>;
def : ProcModel<"c86-4g-m8", C864GM8Model, ProcessorFeatures.C864GM8Features,
>From 790c44cfd932ad908868f2ee9b742f1b21de428c Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sat, 25 Jul 2026 08:16:11 +0200
Subject: [PATCH 2/2] pentium alias
---
llvm/lib/Target/X86/X86.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index cf9032c6241c1..ab27fb0b6aa10 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1897,8 +1897,8 @@ def : Proc<"i486", [FeatureX87],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : Proc<"i586", [FeatureX87, FeatureCX8],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
-def : Proc<"pentium", [FeatureX87, FeatureCX8],
- [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
+def : ProcessorAlias<"pentium", "i586">;
+
def : Proc<"pentium-mmx", [FeatureX87, FeatureCX8, FeatureMMX],
[TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
def : ProcessorAlias<"pentium_mmx", "pentium-mmx">;
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