[llvm-branch-commits] [RISC-V] Use an optional offset for C/Zclsd extension instruction (PR #211674)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jul 23 14:51:33 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Alexander Richardson (arichardson)
<details>
<summary>Changes</summary>
Add uimm*_optional via OptionalMemOffsetAsmOperand and use it for the
instructions to allow dropping the "(${rs1})" zero-offset aliases.
This commit was prepared with the help of AI.
---
Patch is 26.68 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/211674.diff
6 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoC.td (+82-88)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td (+12-20)
- (modified) llvm/test/MC/RISCV/insn_c.s (+5)
- (modified) llvm/test/MC/RISCV/rv32dc-invalid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32fc-invalid.s (+2-2)
- (modified) llvm/test/MC/RISCV/rv32zclsd-invalid.s (+2-4)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
index f7167a002fd9d..297595413f699 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -107,14 +107,25 @@ class RISCVUImmLsbZeroOp<int width, int zeros>
}];
}
+// Variant of RISCVUImmLsbZeroOp for memory-operand offsets that may be
+// omitted entirely, e.g. "c.lw a0, (a1)". See OptionalMemOffsetAsmOperand.
+class OptionalUImmLsbZeroOp<int width, int zeros>
+ : RISCVUImmLsbZeroOp<width, zeros> {
+ defvar Suffix0 = !foldl("", !range(zeros), acc, ignore, !strconcat(acc, "0"));
+ let ParserMatchClass =
+ OptionalMemOffsetAsmOperand<UImmAsmOperand<width, "Lsb" # Suffix0>>;
+}
+
// A 7-bit unsigned immediate where the least significant two bits are zero.
def uimm7_lsb00 : RISCVUImmLsbZeroOp<7, 2>;
+def uimm7_lsb00_optional : OptionalUImmLsbZeroOp<7, 2>;
// A 8-bit unsigned immediate where the least significant two bits are zero.
def uimm8_lsb00 : RISCVUImmLsbZeroOp<8, 2>;
+def uimm8_lsb00_optional : OptionalUImmLsbZeroOp<8, 2>;
// A 8-bit unsigned immediate where the least significant three bits are zero.
-def uimm8_lsb000 : RISCVUImmLsbZeroOp<8, 3>;
+def uimm8_lsb000_optional : OptionalUImmLsbZeroOp<8, 3>;
// A 9-bit signed immediate where the least significant bit is zero.
def bare_simm9_lsb0 : Operand<OtherVT>,
@@ -133,7 +144,7 @@ def bare_simm9_lsb0 : Operand<OtherVT>,
}
// A 9-bit unsigned immediate where the least significant three bits are zero.
-def uimm9_lsb000 : RISCVUImmLsbZeroOp<9, 3>;
+def uimm9_lsb000_optional : OptionalUImmLsbZeroOp<9, 3>;
// A 10-bit unsigned immediate where the least significant two bits are zero
// and the immediate can't be zero.
@@ -195,6 +206,11 @@ def uimm2_opcode : RISCVUImmOp<2> {
let ParserMatchClass = InsnCDirectiveOpcode;
}
+// For memory-operand offsets that may be omitted, e.g. ".insn cl 0, 2, a0, (a1)".
+def uimm5_optional : RISCVUImmLeafOp<5> {
+ let ParserMatchClass = OptionalMemOffsetAsmOperand<UImmAsmOperand<5>>;
+}
+
//===----------------------------------------------------------------------===//
// Instruction Class Templates
//===----------------------------------------------------------------------===//
@@ -278,7 +294,7 @@ def C_ADDI4SPN : RVInst16CIW<0b000, OPC_C0, (outs GPRC:$rd),
let Inst{5} = imm{3};
}
-def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
+def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00_optional>,
Sched<[WriteLDW, ReadMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
@@ -287,7 +303,7 @@ def C_LW : CLoad_ri<0b010, "c.lw", GPRC, uimm7_lsb00>,
}
let isCodeGenOnly = 1 in
-def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
+def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00_optional>,
Sched<[WriteLDW, ReadMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
@@ -296,14 +312,14 @@ def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
}
let append Predicates = [IsRV64] in
-def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000>,
+def C_LD : CLoad_ri<0b011, "c.ld", GPRC, uimm8_lsb000_optional>,
Sched<[WriteLDD, ReadMemBase]> {
bits<8> imm;
let Inst{12-10} = imm{5-3};
let Inst{6-5} = imm{7-6};
}
-def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
+def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00_optional>,
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
@@ -312,7 +328,7 @@ def C_SW : CStore_rri<0b110, "c.sw", GPRC, uimm7_lsb00>,
}
let isCodeGenOnly = 1 in
-def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
+def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00_optional>,
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
@@ -321,7 +337,7 @@ def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
}
let append Predicates = [IsRV64] in
-def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000>,
+def C_SD : CStore_rri<0b111, "c.sd", GPRC, uimm8_lsb000_optional>,
Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
bits<8> imm;
let Inst{12-10} = imm{5-3};
@@ -440,19 +456,19 @@ def C_SLLI : RVInst16CI<0b000, OPC_C2, (outs GPR:$rd_wb),
let Constraints = "$rd = $rd_wb";
}
-def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00>,
+def C_LWSP : CStackLoad<0b010, "c.lwsp", GPRNoX0, uimm8_lsb00_optional>,
Sched<[WriteLDW, ReadMemBase]> {
let Inst{3-2} = imm{7-6};
}
let isCodeGenOnly = 1 in
-def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,
+def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00_optional>,
Sched<[WriteLDW, ReadMemBase]> {
let Inst{3-2} = imm{7-6};
}
let Predicates = [HasStdExtZca, IsRV64] in
-def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
+def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000_optional>,
Sched<[WriteLDD, ReadMemBase]> {
let Inst{4-2} = imm{8-6};
}
@@ -487,19 +503,19 @@ def C_ADD : RVInst16CR<0b1001, OPC_C2, (outs GPR:$rd),
let Constraints = "$rs1 = $rd";
}
-def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00>,
+def C_SWSP : CStackStore<0b110, "c.swsp", GPR, uimm8_lsb00_optional>,
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
let Inst{8-7} = imm{7-6};
}
let isCodeGenOnly = 1 in
-def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,
+def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00_optional>,
Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
let Inst{8-7} = imm{7-6};
}
let append Predicates = [IsRV64] in
-def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000>,
+def C_SDSP : CStackStore<0b111, "c.sdsp", GPR, uimm9_lsb000_optional>,
Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
let Inst{9-7} = imm{8-6};
}
@@ -516,7 +532,7 @@ def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther>,
let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtZcf, IsRV32] in {
- def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
+ def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00_optional>,
Sched<[WriteFLD32, ReadFMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
@@ -524,7 +540,7 @@ let DecoderNamespace = "RV32Only",
let Inst{5} = imm{6};
}
- def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
+ def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00_optional>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
bits<7> imm;
let Inst{12-10} = imm{5-3};
@@ -532,38 +548,38 @@ let DecoderNamespace = "RV32Only",
let Inst{5} = imm{6};
}
- def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
+ def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00_optional>,
Sched<[WriteFLD32, ReadFMemBase]> {
let Inst{3-2} = imm{7-6};
}
- def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
+ def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00_optional>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
let Inst{8-7} = imm{7-6};
}
} // DecoderNamespace = "RV32Only", Predicates = [HasStdExtZcf, IsRV32]
let Predicates = [HasStdExtZcd] in {
- def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>,
+ def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000_optional>,
Sched<[WriteFLD64, ReadFMemBase]> {
bits<8> imm;
let Inst{12-10} = imm{5-3};
let Inst{6-5} = imm{7-6};
}
- def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>,
+ def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000_optional>,
Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
bits<8> imm;
let Inst{12-10} = imm{5-3};
let Inst{6-5} = imm{7-6};
}
- def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
+ def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000_optional>,
Sched<[WriteFLD64, ReadFMemBase]> {
let Inst{4-2} = imm{8-6};
}
- def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
+ def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000_optional>,
Sched<[WriteFST64, ReadFStoreData, ReadFMemBase]> {
let Inst{9-7} = imm{8-6};
}
@@ -606,31 +622,15 @@ def : InstAlias<"c.ntl.all", (C_ADD X0, X5)>;
let EmitPriority = 0 in {
let Predicates = [HasStdExtZca] in {
-def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRNoX0:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPR:$rs2, SPMem:$rs1, 0)>;
}
let Predicates = [HasStdExtZca, IsRV64] in {
-def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRNoX0:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPR:$rs2, SPMem:$rs1, 0)>;
}
let Predicates = [HasStdExtZcf, IsRV32] in {
-def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32:$rs2, SPMem:$rs1, 0)>;
}
let Predicates = [HasStdExtZcd] in {
-def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, BasePtrC:$rs1, 0)>;
-def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64:$rd, SPMem:$rs1, 0)>;
-def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64:$rs2, SPMem:$rs1, 0)>;
}
} // EmitPriority = 0
@@ -672,13 +672,13 @@ def InsnCSS : DirectiveInsnCSS<(outs), (ins uimm2_opcode:$opcode,
def InsnCL : DirectiveInsnCL<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
uimm3:$funct3,
AnyRegC:$rs1,
- uimm5:$imm5),
+ uimm5_optional:$imm5),
"$opcode, $funct3, $rd, ${imm5}(${rs1})">;
def InsnCS : DirectiveInsnCS<(outs), (ins uimm2_opcode:$opcode,
uimm3:$funct3,
AnyRegC:$rs2,
AnyRegC:$rs1,
- uimm5:$imm5),
+ uimm5_optional:$imm5),
"$opcode, $funct3, $rs2, ${imm5}(${rs1})">;
def InsnCA : DirectiveInsnCA<(outs AnyRegC:$rd), (ins uimm2_opcode:$opcode,
uimm6:$funct6,
@@ -714,16 +714,10 @@ def : InstAlias<".insn_css $opcode, $funct3, $rs2, $imm6",
uimm6:$imm6)>;
def : InstAlias<".insn_cl $opcode, $funct3, $rd, ${imm5}(${rs1})",
(InsnCL AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
- AnyRegC:$rs1, uimm5:$imm5)>;
-def : InstAlias<".insn_cl $opcode, $funct3, $rd, (${rs1})",
- (InsnCL AnyRegC:$rd, uimm2_opcode:$opcode, uimm3:$funct3,
- AnyRegC:$rs1, 0)>;
+ AnyRegC:$rs1, uimm5_optional:$imm5)>;
def : InstAlias<".insn_cs $opcode, $funct3, $rs2, ${imm5}(${rs1})",
(InsnCS uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs2,
- AnyRegC:$rs1, uimm5:$imm5)>;
-def : InstAlias<".insn_cs $opcode, $funct3, $rs2, (${rs1})",
- (InsnCS uimm2_opcode:$opcode, uimm3:$funct3, AnyRegC:$rs2,
- AnyRegC:$rs1, 0)>;
+ AnyRegC:$rs1, uimm5_optional:$imm5)>;
def : InstAlias<".insn_ca $opcode, $funct6, $funct2, $rd, $rs2",
(InsnCA AnyRegC:$rd, uimm2_opcode:$opcode, uimm6:$funct6,
uimm2:$funct2, AnyRegC:$rs2)>;
@@ -748,28 +742,28 @@ let Predicates = [HasStdExtZca] in {
def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
(C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>;
-def : CompressPat<(LW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm),
- (C_LW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(LW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm),
+ (C_LW GPRC:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm)>;
let isCompressOnly = true in
-def : CompressPat<(LW_INX GPRF32C:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm),
- (C_LW_INX GPRF32C:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(LW_INX GPRF32C:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm),
+ (C_LW_INX GPRF32C:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm)>;
let append Predicates = [IsRV64] in {
-def : CompressPat<(LD GPRC:$rd, BasePtrC:$rs1, uimm8_lsb000:$imm),
- (C_LD GPRC:$rd, BasePtrC:$rs1, uimm8_lsb000:$imm)>;
+def : CompressPat<(LD GPRC:$rd, BasePtrC:$rs1, uimm8_lsb000_optional:$imm),
+ (C_LD GPRC:$rd, BasePtrC:$rs1, uimm8_lsb000_optional:$imm)>;
} // append Predicates = [IsRV64]
-def : CompressPat<(SW GPRC:$rs2, BasePtrC:$rs1, uimm7_lsb00:$imm),
- (C_SW GPRC:$rs2, BasePtrC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(SW GPRC:$rs2, BasePtrC:$rs1, uimm7_lsb00_optional:$imm),
+ (C_SW GPRC:$rs2, BasePtrC:$rs1, uimm7_lsb00_optional:$imm)>;
let isCompressOnly = true in
-def : CompressPat<(SW_INX GPRF32C:$rs2, BasePtrC:$rs1, uimm7_lsb00:$imm),
- (C_SW_INX GPRF32C:$rs2, BasePtrC:$rs1, uimm7_lsb00:$imm)>;
+def : CompressPat<(SW_INX GPRF32C:$rs2, BasePtrC:$rs1, uimm7_lsb00_optional:$imm),
+ (C_SW_INX GPRF32C:$rs2, BasePtrC:$rs1, uimm7_lsb00_optional:$imm)>;
let append Predicates = [IsRV64] in {
-def : CompressPat<(SD GPRC:$rs2, BasePtrC:$rs1, uimm8_lsb000:$imm),
- (C_SD GPRC:$rs2, BasePtrC:$rs1, uimm8_lsb000:$imm)>;
+def : CompressPat<(SD GPRC:$rs2, BasePtrC:$rs1, uimm8_lsb000_optional:$imm),
+ (C_SD GPRC:$rs2, BasePtrC:$rs1, uimm8_lsb000_optional:$imm)>;
} // append Predicates = [IsRV64]
} // Predicates = [HasStdExtZca]
@@ -851,16 +845,16 @@ let Predicates = [HasStdExtZca] in {
def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
(C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>;
-def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
- (C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00_optional:$imm),
+ (C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00_optional:$imm)>;
let isCompressOnly = true in
-def : CompressPat<(LW_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
- (C_LWSP_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(LW_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00_optional:$imm),
+ (C_LWSP_INX GPRF32NoX0:$rd, SPMem:$rs1, uimm8_lsb00_optional:$imm)>;
let append Predicates = [IsRV64] in {
-def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
- (C_LDSP GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
+def : CompressPat<(LD GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000_optional:$imm),
+ (C_LDSP GPRNoX0:$rd, SPMem:$rs1, uimm9_lsb000_optional:$imm)>;
} // append Predicates = [IsRV64]
def : CompressPat<(JALR X0, GPRNoX0:$rs1, 0),
@@ -883,45 +877,45 @@ let isCompressOnly = true in
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs1),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
-def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
- (C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00_optional:$imm),
+ (C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00_optional:$imm)>;
let isCompressOnly = true in
-def : CompressPat<(SW_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
- (C_SWSP_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
+def : CompressPat<(SW_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00_optional:$imm),
+ (C_SWSP_INX GPRF32:$rs2, SPMem:$rs1, uimm8_lsb00_optional:$imm)>;
let append Predicates = [IsRV64] in {
-def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
- (C_SDSP GPR:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
+def : CompressPat<(SD GPR:$rs2, SPMem:$rs1, uimm9_lsb000_optional:$imm),
+ (C_SDSP GPR:$rs2, SPMem:$rs1, uimm9_lsb000_optional:$imm)>;
} // append Predicates = [IsRV64]
} // Predicates = [HasStdExtZca]
// Zcf Instructions
let Predicates = [HasStdExtZcf, IsRV32] in {
// Quadrant 0
- def : CompressPat<(FLW FPR32C:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm),
- (C_FLW FPR32C:$rd, BasePtrC:$rs1, uimm7_lsb00:$imm)>;
- def : CompressPat<(FSW FPR32C:$rs2, BasePtrC:$rs1, uimm7_lsb00:$imm),
- (C_FSW FPR32C:$rs2, BasePtrC:$rs1, uimm7_lsb00:$imm)>;
+ def : CompressPat<(FLW FPR32C:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm),
+ (C_FLW FPR32C:$rd, BasePtrC:$rs1, uimm7_lsb00_optional:$imm)>;
+ def : CompressPat<(FSW FPR32C:$rs2, BasePtrC:$rs1, uimm7_lsb00_optional:$imm),
+ (C_FSW FPR32C:$rs2, BasePtrC:$rs1, uimm7_lsb00_optional:$imm)>;
// Quadrant 2
- def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
- (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
- def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
- (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
+ def : CompressPat<(FLW FPR32:$rd, SPMem:$rs1, uimm8_lsb00_optional:$imm),
+ (C_FLWSP FPR32:$rd, SPMem:$rs1, uimm8_lsb00_optional:$imm)>;
+ def : CompressPat<(FSW FPR32:$rs2, SPMem:$rs1, uimm8_lsb00_optional:$imm),
+ (C_FSWSP FPR32:$rs2, SPMem:$rs1, uimm8_lsb00_optional:$imm)>;
} // Predicates = [HasStdExtZcf, IsRV32]
// Zcd Instructions
let Predicates = [HasStdExtZcd] in {
// Quadrant 0
- def : CompressPat<(FLD FPR64C:$rd, BasePtrC:$rs1, uimm8_lsb000:$imm),
- (C_FLD FPR64C:$rd, BasePtrC:$rs1, uimm8_lsb000:$imm)>;
- def : CompressPat<(FSD FPR64C:$rs2, BasePtrC:$rs1, uimm8_lsb000:$imm),
- (C_FSD FPR64C:$rs2, BasePtrC:$rs1, uimm8_lsb000:$imm)>;
+ def : CompressPat<(FLD FPR64C:$rd, BasePtrC:$rs1, uimm8_lsb000_optional:$imm),
+ (C_FLD FPR64C:$rd, BasePtrC:$rs1, uimm8_lsb000_optional:$imm)>;
+ def : CompressPat<(FSD FPR64C:$rs2, BasePtrC:$rs1, uimm8_lsb000_optional:$imm),
+ (C_FSD FPR64C:$rs2, BasePtrC:$rs1, uimm8_lsb000_optional:$imm)>;
// Quadrant 2
- def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
- (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
- def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm),
- (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>;
+ def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000_optional:$imm),
+ (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000_optional:$imm)>;
+ def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000_optional:$imm),
+ (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000_optional:$imm)>;
} // Predicates = [HasStdExtZcd]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
index f4676819665c5..16467fa424e38 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZclsd.td
@@ -46,24 +46,24 @@ def GPRPairCRV32 : RegisterOperand<GPRPairC> {
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZclsd, IsRV32], DecoderNamespace = "ZcOverlap" in {
-def C_LDSP_RV32 : CStac...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/211674
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