[llvm-branch-commits] [llvm] AMDGPU: Validate VOPD/VOPD3 physical source registers against operand RC (PR #196515)

[Petar Avramovic via llvm-branch-commits]

================
@@ -105,7 +144,8 @@ bool llvm::checkVOPDRegConstraints(const SIInstrInfo &TII,
             return false;
         } else if (MI.getOpcode() == AMDGPU::V_CNDMASK_B32_e64) {
           UniqueScalarRegs.insert(Src2->getReg());
-        } else if (!Src2->isReg() || !TRI->isVGPR(MRI, Src2->getReg())) {
+        } else if (!Src2->isReg() ||
+                   !isValidVOPDSrc(TII, VOPDOpc, CompIdx, 2, Src2->getReg())) {
           return false;
         }
----------------
petar-avramovic wrote:

Slightly less efficient way to write it without special casing only opcode that has sgpr in src2. 
```
        } else {
          if (!Src2->isReg())
            return false;
          if (!isValidVOPDSrc(TII, VOPDOpc, CompIdx, 2, Src2->getReg()))
            return false;
          if (!TRI->isVectorRegister(MRI, Src2->getReg())) {
            assert(MI.getOpcode() == AMDGPU::V_CNDMASK_B32_e64);
            UniqueScalarRegs.insert(Src2->getReg());
          }
```

https://github.com/llvm/llvm-project/pull/196515