[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper (PR #210102)
Petar Avramovic via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Jul 20 05:45:25 PDT 2026
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/210102
>From b55a911a4a351c09c07d9ea23cffbd08ec1c8253 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Thu, 16 Jul 2026 18:19:20 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Use extended LLTs in AMDGPUCombinerHelper
Here we also had to change comparisons to extended LLTs to avoid
matching bfloats. In the old scalar version, before the switch to extended
LLTs, s16 was treated as f16 and bf16 was combined as if it were f16.
---
.../Target/AMDGPU/AMDGPUCombinerHelper.cpp | 20 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 998 ++-
.../CodeGen/AMDGPU/GlobalISel/llvm.powi.ll | 86 +-
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 421 +-
.../test/CodeGen/AMDGPU/fmed3-cast-combine.ll | 355 +-
llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll | 754 ++-
llvm/test/CodeGen/AMDGPU/llvm.log.ll | 5410 +++++++++++------
llvm/test/CodeGen/AMDGPU/llvm.log10.ll | 5410 +++++++++++------
llvm/test/CodeGen/AMDGPU/llvm.log2.ll | 4035 ++++++++----
.../AMDGPU/pseudo-scalar-transcendental.ll | 212 +-
10 files changed, 12394 insertions(+), 5307 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
index a75c093a9e7ff..a325170e89e9b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp
@@ -431,7 +431,7 @@ static bool isFPExtFromF16OrConst(const MachineRegisterInfo &MRI,
const MachineInstr *Def = MRI.getVRegDef(Reg);
if (Def->getOpcode() == TargetOpcode::G_FPEXT) {
Register SrcReg = Def->getOperand(1).getReg();
- return MRI.getType(SrcReg) == LLT::scalar(16);
+ return MRI.getType(SrcReg) == LLT::float16();
}
if (Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
@@ -450,7 +450,9 @@ bool AMDGPUCombinerHelper::matchExpandPromotedF16FMed3(MachineInstr &MI,
Register Src2) const {
assert(MI.getOpcode() == TargetOpcode::G_FPTRUNC);
Register SrcReg = MI.getOperand(1).getReg();
- if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::scalar(32))
+ if (MRI.getType(MI.getOperand(0).getReg()) != LLT::float16())
+ return false;
+ if (!MRI.hasOneNonDBGUse(SrcReg) || MRI.getType(SrcReg) != LLT::float32())
return false;
return isFPExtFromF16OrConst(MRI, Src0) && isFPExtFromF16OrConst(MRI, Src1) &&
@@ -463,9 +465,9 @@ void AMDGPUCombinerHelper::applyExpandPromotedF16FMed3(MachineInstr &MI,
Register Src2) const {
// We expect fptrunc (fpext x) to fold out, and to constant fold any constant
// sources.
- Src0 = Builder.buildFPTrunc(LLT::scalar(16), Src0).getReg(0);
- Src1 = Builder.buildFPTrunc(LLT::scalar(16), Src1).getReg(0);
- Src2 = Builder.buildFPTrunc(LLT::scalar(16), Src2).getReg(0);
+ Src0 = Builder.buildFPTrunc(LLT::float16(), Src0).getReg(0);
+ Src1 = Builder.buildFPTrunc(LLT::float16(), Src1).getReg(0);
+ Src2 = Builder.buildFPTrunc(LLT::float16(), Src2).getReg(0);
LLT Ty = MRI.getType(Src0);
auto A1 = Builder.buildFMinNumIEEE(Ty, Src0, Src1);
@@ -487,8 +489,8 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
LLT ScalarDestTy = DestTy.getScalarType();
// TODO: Expected float type in ScalarDestTy
- if ((ScalarDestTy != LLT::scalar(64) && ScalarDestTy != LLT::scalar(32) &&
- ScalarDestTy != LLT::scalar(16)) ||
+ if ((ScalarDestTy != LLT::float64() && ScalarDestTy != LLT::float32() &&
+ ScalarDestTy != LLT::float16()) ||
!MRI.hasOneNonDBGUse(Sel.getOperand(0).getReg()))
return false;
@@ -510,7 +512,7 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
// For f32, only non-inline constants should be transformed.
// TODO: Expected float32
- if (ScalarDestTy == LLT::scalar(32) && TII.isInlineConstant(*SelectTrueVal) &&
+ if (ScalarDestTy == LLT::float32() && TII.isInlineConstant(*SelectTrueVal) &&
TII.isInlineConstant(*SelectFalseVal))
return false;
@@ -522,7 +524,7 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
return false;
MatchInfo = [=, &MI](MachineIRBuilder &Builder) {
- LLT IntDestTy = DestTy.changeElementType(LLT::scalar(32));
+ LLT IntDestTy = DestTy.changeElementType(LLT::integer(32));
auto NewSel = Builder.buildSelect(
IntDestTy, SelectCondReg,
Builder.buildConstant(IntDestTy, SelectTrueLog2Val),
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
index fc7c4a57fe32e..0e5b3b25c51b0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
@@ -1,52 +1,126 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GFX6 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03 < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define float @v_pow_f32(float %x, float %y) {
; GFX6-LABEL: v_pow_f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -56,57 +130,190 @@ define <2 x float> @v_pow_v2f32(<2 x float> %x, <2 x float> %y) {
; GFX6-LABEL: v_pow_v2f32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v4, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX6-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v5
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v4
; GFX6-NEXT: v_log_f32_e32 v1, v1
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v6
+; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX6-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX6-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX6-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v7
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_add_f32_e32 v1, v1, v2
; GFX6-NEXT: v_exp_f32_e32 v1, v1
+; GFX6-NEXT: v_not_b32_e32 v4, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_v2f32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v4, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v4
; GFX8-NEXT: v_log_f32_e32 v1, v1
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX8-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX8-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX8-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v7
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v2
; GFX8-NEXT: v_exp_f32_e32 v1, v1
+; GFX8-NEXT: v_not_b32_e32 v4, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_v2f32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 5, v4
; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v4
; GFX9-NEXT: v_log_f32_e32 v1, v1
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
+; GFX9-NEXT: v_mov_b32_e32 v5, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v5, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, v5, s[4:5]
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
+; GFX9-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v6, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v6, vcc
+; GFX9-NEXT: v_cmp_lt_f32_e64 s[4:5], v1, v2
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v7
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v6, s[4:5]
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v2
; GFX9-NEXT: v_exp_f32_e32 v1, v1
+; GFX9-NEXT: v_not_b32_e32 v4, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v4, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v4, s[4:5]
+; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_v2f32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 5, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v4
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s4
; GFX10-NEXT: v_log_f32_e32 v0, v0
; GFX10-NEXT: v_log_f32_e32 v1, v1
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v2, v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v3, v1
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v4
+; GFX10-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v1, v1, v3
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0xc2fc0000, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s4
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s4
; GFX10-NEXT: v_exp_f32_e32 v0, v0
; GFX10-NEXT: v_exp_f32_e32 v1, v1
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_v2f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, v1
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v5
+; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s0
; GFX11-NEXT: v_log_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_dual_mul_dx9_zero_f32 v0, v2, v0 :: v_dual_mul_dx9_zero_f32 v1, v3, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: v_dual_sub_f32 v1, v1, v5 :: v_dual_lshlrev_b32 v4, 5, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v4
+; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, vcc_lo
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v1, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v1, v1, v3
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v1, v1
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%pow = call <2 x float> @llvm.pow.v2f32(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
@@ -812,43 +1019,117 @@ define float @v_pow_f32_fabs_lhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_lhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e64 v0, |v0|
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e64 v0, |v0|
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e64 v0, |v0|
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e64 v0, |v0|
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e64 v0, |v0|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%pow = call float @llvm.pow.f32(float %fabs.x, float %y)
@@ -859,43 +1140,117 @@ define float @v_pow_f32_fabs_rhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.y = call float @llvm.fabs.f32(float %y)
%pow = call float @llvm.pow.f32(float %x, float %fabs.y)
@@ -906,43 +1261,117 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e64 v0, |v0|
-; GFX6-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e64 v0, |v0|
-; GFX8-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e64 v0, |v0|
-; GFX9-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e64 v0, |v0|
-; GFX10-NEXT: v_mul_legacy_f32_e64 v0, |v1|, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, |v1|
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fabs_lhs_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e64 v0, |v0|
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, |v1|, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, |v1|
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call float @llvm.fabs.f32(float %x)
%fabs.y = call float @llvm.fabs.f32(float %y)
@@ -953,39 +1382,127 @@ define float @v_pow_f32_fabs_lhs_rhs(float %x, float %y) {
define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
; GFX6-LABEL: v_pow_f32_sgpr_vgpr:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_log_f32_e32 v1, s0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: s_cselect_b32 s2, 1, 0
+; GFX6-NEXT: s_cselect_b32 s1, 1, 0
+; GFX6-NEXT: s_lshl_b32 s2, s2, 5
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-NEXT: v_ldexp_f32_e32 v1, s0, v1
+; GFX6-NEXT: v_log_f32_e32 v1, v1
+; GFX6-NEXT: s_cmp_lg_u32 s1, 0
+; GFX6-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_subrev_f32_e32 v1, s0, v1
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_sgpr_vgpr:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_log_f32_e32 v1, s0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: s_cselect_b32 s2, 1, 0
+; GFX8-NEXT: s_cselect_b32 s1, 1, 0
+; GFX8-NEXT: s_lshl_b32 s2, s2, 5
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX8-NEXT: v_log_f32_e32 v1, v1
+; GFX8-NEXT: s_cmp_lg_u32 s1, 0
+; GFX8-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_subrev_f32_e32 v1, s0, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_sgpr_vgpr:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_log_f32_e32 v1, s0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_cselect_b32 s1, 1, 0
+; GFX9-NEXT: s_lshl_b32 s2, s2, 5
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX9-NEXT: v_log_f32_e32 v1, v1
+; GFX9-NEXT: s_cmp_lg_u32 s1, 0
+; GFX9-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_subrev_f32_e32 v1, s0, v1
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_vgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_log_f32_e32 v1, s0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_cselect_b32 s1, 1, 0
+; GFX10-NEXT: s_lshl_b32 s2, s2, 5
+; GFX10-NEXT: s_cmp_lg_u32 s1, 0
+; GFX10-NEXT: v_ldexp_f32 v1, s0, s2
+; GFX10-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX10-NEXT: v_log_f32_e32 v1, v1
+; GFX10-NEXT: v_subrev_f32_e32 v1, s0, v1
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_vgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_log_f32_e32 v1, s0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_cselect_b32 s1, 1, 0
+; GFX11-NEXT: s_lshl_b32 s2, s2, 5
+; GFX11-NEXT: s_cmp_lg_u32 s1, 0
+; GFX11-NEXT: v_ldexp_f32 v1, s0, s2
+; GFX11-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v1, v1
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_subrev_f32_e32 v1, s0, v1
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -994,39 +1511,113 @@ define amdgpu_ps float @v_pow_f32_sgpr_vgpr(float inreg %x, float %y) {
define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
; GFX6-LABEL: v_pow_f32_vgpr_sgpr:
; GFX6: ; %bb.0:
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_vgpr_sgpr:
; GFX8: ; %bb.0:
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_vgpr_sgpr:
; GFX9: ; %bb.0:
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_vgpr_sgpr:
; GFX10: ; %bb.0:
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s0, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_vgpr_sgpr:
; GFX11: ; %bb.0:
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -1035,39 +1626,126 @@ define amdgpu_ps float @v_pow_f32_vgpr_sgpr(float %x, float inreg %y) {
define amdgpu_ps float @v_pow_f32_sgpr_sgpr(float inreg %x, float inreg %y) {
; GFX6-LABEL: v_pow_f32_sgpr_sgpr:
; GFX6: ; %bb.0:
-; GFX6-NEXT: v_log_f32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX6-NEXT: s_or_b64 s[2:3], vcc, vcc
+; GFX6-NEXT: s_cselect_b32 s3, 1, 0
+; GFX6-NEXT: s_cselect_b32 s2, 1, 0
+; GFX6-NEXT: s_lshl_b32 s3, s3, 5
+; GFX6-NEXT: v_mov_b32_e32 v0, s3
+; GFX6-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: s_cmp_lg_u32 s2, 0
+; GFX6-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX6-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: s_or_b64 s[0:1], vcc, vcc
+; GFX6-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX6-NEXT: v_add_f32_e32 v0, s0, v0
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: v_pow_f32_sgpr_sgpr:
; GFX8: ; %bb.0:
-; GFX8-NEXT: v_log_f32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: s_cselect_b32 s3, 1, 0
+; GFX8-NEXT: s_cselect_b32 s2, 1, 0
+; GFX8-NEXT: s_lshl_b32 s3, s3, 5
+; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: s_cmp_lg_u32 s2, 0
+; GFX8-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX8-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX8-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX8-NEXT: v_add_f32_e32 v0, s0, v0
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX8-NEXT: v_ldexp_f32 v0, v0, s0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_pow_f32_sgpr_sgpr:
; GFX9: ; %bb.0:
-; GFX9-NEXT: v_log_f32_e32 v0, s0
+; GFX9-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_lshl_b32 s3, s3, 5
+; GFX9-NEXT: v_mov_b32_e32 v0, s3
+; GFX9-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: s_cmp_lg_u32 s2, 0
+; GFX9-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX9-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX9-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX9-NEXT: v_add_f32_e32 v0, s0, v0
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
+; GFX9-NEXT: v_ldexp_f32 v0, v0, s0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: v_pow_f32_sgpr_sgpr:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_log_f32_e32 v0, s0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
+; GFX10-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10-NEXT: s_cselect_b32 s3, 1, 0
+; GFX10-NEXT: s_cselect_b32 s2, 1, 0
+; GFX10-NEXT: s_lshl_b32 s3, s3, 5
+; GFX10-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10-NEXT: v_ldexp_f32 v0, s0, s3
+; GFX10-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX10-NEXT: v_mul_legacy_f32_e32 v0, s1, v0
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX10-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX10-NEXT: v_add_f32_e32 v0, s0, v0
+; GFX10-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, s0
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: v_pow_f32_sgpr_sgpr:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_log_f32_e32 v0, s0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s0
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: s_cselect_b32 s3, 1, 0
+; GFX11-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-NEXT: s_lshl_b32 s3, s3, 5
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: v_ldexp_f32 v0, s0, s3
+; GFX11-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_subrev_f32_e32 v0, s0, v0
; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, s1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: s_cmp_lg_u32 vcc_lo, 0
+; GFX11-NEXT: s_cselect_b32 s0, 0x42800000, 0
+; GFX11-NEXT: v_add_f32_e32 v0, s0, v0
+; GFX11-NEXT: s_cselect_b32 s0, 0xffffffc0, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, s0
; GFX11-NEXT: ; return to shader part epilog
%pow = call float @llvm.pow.f32(float %x, float %y)
ret float %pow
@@ -1077,43 +1755,117 @@ define float @v_pow_f32_fneg_lhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fneg_lhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT: v_log_f32_e64 v0, -v0
-; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e64 v0, -v0, v2
+; GFX6-NEXT: v_log_f32_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fneg_lhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_log_f32_e64 v0, -v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v0, -v0, v2
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fneg_lhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_log_f32_e64 v0, -v0
-; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v0, -v0, v2
+; GFX9-NEXT: v_log_f32_e32 v0, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fneg_lhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_log_f32_e64 v0, -v0
-; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
+; GFX10-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, -v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v0, -v0, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s4
+; GFX10-NEXT: v_log_f32_e32 v0, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fneg_lhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e64 v0, -v0
+; GFX11-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_ldexp_f32 v0, -v0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s0
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg float %x
%pow = call float @llvm.pow.f32(float %neg.x, float %y)
@@ -1124,43 +1876,117 @@ define float @v_pow_f32_fneg_rhs(float %x, float %y) {
; GFX6-LABEL: v_pow_f32_fneg_rhs:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
; GFX6-NEXT: v_log_f32_e32 v0, v0
-; GFX6-NEXT: v_mul_legacy_f32_e64 v0, -v1, v0
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX6-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX6-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX6-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
+; GFX6-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX6-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX6-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX6-NEXT: v_add_f32_e32 v0, v0, v1
; GFX6-NEXT: v_exp_f32_e32 v0, v0
+; GFX6-NEXT: v_not_b32_e32 v1, 63
+; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_pow_f32_fneg_rhs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e64 v0, -v1, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_pow_f32_fneg_rhs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
; GFX9-NEXT: v_log_f32_e32 v0, v0
-; GFX9-NEXT: v_mul_legacy_f32_e64 v0, -v1, v0
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX9-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX9-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX9-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v1
; GFX9-NEXT: v_exp_f32_e32 v0, v0
+; GFX9-NEXT: v_not_b32_e32 v1, 63
+; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_pow_f32_fneg_rhs:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
; GFX10-NEXT: v_log_f32_e32 v0, v0
-; GFX10-NEXT: v_mul_legacy_f32_e64 v0, -v1, v0
+; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_legacy_f32_e64 v0, v0, -v1
+; GFX10-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
; GFX10-NEXT: v_exp_f32_e32 v0, v0
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v1
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_pow_f32_fneg_rhs:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, -v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: v_mul_dx9_zero_f32_e64 v0, v0, -v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.y = fneg float %y
%pow = call float @llvm.pow.f32(float %x, float %neg.y)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index 1914250370219..6ac395372ddae 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu7.01-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX78,GFX7 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX78,GFX8 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu7.01-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX78,GFX7 %s
+; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX78,GFX8 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX7-LABEL: v_powi_f16:
@@ -75,24 +75,80 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
}
define float @v_powi_f32(float %l, i32 %r) {
-; GFX78-LABEL: v_powi_f32:
-; GFX78: ; %bb.0:
-; GFX78-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX78-NEXT: v_log_f32_e32 v0, v0
-; GFX78-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX78-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX78-NEXT: v_exp_f32_e32 v0, v0
-; GFX78-NEXT: s_setpc_b64 s[30:31]
+; GFX7-LABEL: v_powi_f32:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX7-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; GFX7-NEXT: v_log_f32_e32 v0, v0
+; GFX7-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX7-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX7-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX7-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX7-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX7-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX7-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX7-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX7-NEXT: v_exp_f32_e32 v0, v0
+; GFX7-NEXT: v_not_b32_e32 v1, 63
+; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX7-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_powi_f32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX8-NEXT: v_log_f32_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42000000
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
+; GFX8-NEXT: v_mov_b32_e32 v2, 0x42800000
+; GFX8-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_not_b32_e32 v1, 63
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_powi_f32:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_log_f32_e32 v0, v0
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 5, v2
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_log_f32_e32 v0, v0
; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
+; GFX11-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%res = call float @llvm.powi.f32.i32(float %l, i32 %r)
ret float %res
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index fdfdb56db0f82..c462dd3c9f52f 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -1549,21 +1549,42 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: fmul_select_f16_test1:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: fmul_select_f16_test1:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: fmul_select_f16_test1:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: fmul_select_f16_test1:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: fmul_select_f16_test1:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: fmul_select_f16_test1:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test1:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -1587,8 +1608,10 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1596,8 +1619,10 @@ define half @fmul_select_f16_test1(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
@@ -1617,26 +1642,47 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: fmul_select_f16_test2:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
-; GFX9-NEXT: s_movk_i32 s4, 0x8000
-; GFX9-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2
-; GFX9-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: fmul_select_f16_test2:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x8000
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX9-SDAG-NEXT: v_med3_i32 v1, v1, s4, v2
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: fmul_select_f16_test2:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-NEXT: s_movk_i32 s4, 0x8000
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
-; GFX10-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
-; GFX10-NEXT: v_ldexp_f16_e32 v0, v0, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: fmul_select_f16_test2:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: fmul_select_f16_test2:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x8000
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-SDAG-NEXT: v_med3_i32 v1, v1, s4, 0x7fff
+; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: fmul_select_f16_test2:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test2:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -1664,10 +1710,10 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-TRUE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1675,10 +1721,10 @@ define half @fmul_select_f16_test2(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: s_movk_i32 s0, 0x8000
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, v1, s0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
@@ -1730,30 +1776,62 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: fmul_select_v2f16_test3:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x3c00
-; GFX9-NEXT: v_mov_b32_e32 v6, 0x4000
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_pack_b32_f16 v1, v1, v2
-; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: fmul_select_v2f16_test3:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x3c00
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x4000
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX9-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: fmul_select_v2f16_test3:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v5, 0x4000
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
-; GFX10-NEXT: v_pack_b32_f16 v1, v1, v2
-; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: fmul_select_v2f16_test3:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4
+; GFX9-GISEL-NEXT: v_med3_i32 v2, v2, v3, v4
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
+; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: fmul_select_v2f16_test3:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0x4000
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX10-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: fmul_select_v2f16_test3:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
+; GFX10-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_v2f16_test3:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -1785,28 +1863,37 @@ define <2 x half> @fmul_select_v2f16_test3(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2f16_test3:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x3c00
-; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v1, v3
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0x4000, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, 0x4000, s0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fmul_select_v2f16_test3:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v5, 0x4000
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v2
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
%y = select <2 x i1> %bool, <2 x half> <half 2.000000e+00, half 2.000000e+00>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
@@ -1857,30 +1944,62 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX7-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: fmul_select_v2f16_test4:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x3c00
-; GFX9-NEXT: v_mov_b32_e32 v6, 0x3800
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
-; GFX9-NEXT: v_pack_b32_f16 v1, v1, v2
-; GFX9-NEXT: v_pk_mul_f16 v0, v0, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: fmul_select_v2f16_test4:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x3c00
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v6, 0x3800
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v5, v6, vcc
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX9-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: fmul_select_v2f16_test4:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v5, 0x3800
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX10-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
-; GFX10-NEXT: v_pack_b32_f16 v1, v1, v2
-; GFX10-NEXT: v_pk_mul_f16 v0, v0, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: fmul_select_v2f16_test4:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v2, v4
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4
+; GFX9-GISEL-NEXT: v_med3_i32 v2, v2, v3, v4
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
+; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: fmul_select_v2f16_test4:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v5, 0x3800
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
+; GFX10-SDAG-NEXT: v_pack_b32_f16 v1, v1, v2
+; GFX10-SDAG-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: fmul_select_v2f16_test4:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v1, v0, v1
+; GFX10-GISEL-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX10-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_v2f16_test4:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -1912,28 +2031,37 @@ define <2 x half> @fmul_select_v2f16_test4(<2 x half> %x, <2 x i32> %bool.arg1,
; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2f16_test4:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, 0x3c00
-; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v1, v3
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v1.h, v2.l, 0x3800, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v1.l, v2.l, 0x3800, s0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v0.h, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: fmul_select_v2f16_test4:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v5, 0x3800
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v2, 0x3c00, v5, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x3c00, v5, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v1, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT: v_pk_mul_f16 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v2, 0xffff8000, v2, v3
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v2
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq <2 x i32> %bool.arg1, %bool.arg2
%y = select <2 x i1> %bool, <2 x half> <half 5.000000e-01, half 5.000000e-01>, <2 x half> <half 1.000000e+00, half 1.000000e+00>
@@ -2334,21 +2462,44 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX7-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX9-LABEL: fmul_select_f16_test9:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc
-; GFX9-NEXT: v_ldexp_f16_e64 v0, -v0, v1
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: fmul_select_f16_test9:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc
+; GFX9-SDAG-NEXT: v_ldexp_f16_e64 v0, -v0, v1
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: fmul_select_f16_test9:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX10-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo
-; GFX10-NEXT: v_ldexp_f16_e64 v0, -v0, v1
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: fmul_select_f16_test9:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 5, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v2, v3
+; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: fmul_select_f16_test9:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo
+; GFX10-SDAG-NEXT: v_ldexp_f16_e64 v0, -v0, v1
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: fmul_select_f16_test9:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 5, v1
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
+; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v0, v1
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: fmul_select_f16_test9:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -2372,7 +2523,11 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 5, v1
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v0.l, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -2381,7 +2536,11 @@ define half @fmul_select_f16_test9(half %x, i32 %bool.arg1, i32 %bool.arg2) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 5, 4, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 5, v1
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v2
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, -v0, v1
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll b/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
index 3031c4835ce10..e86fa2a7c68f1 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll
@@ -27,14 +27,23 @@ define half @fmed3_f32_fpext_f16(half %arg0, half %arg1, half %arg2) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16:
; GFX9: ; %bb.0:
@@ -64,14 +73,23 @@ define half @fmed3_f32_fpext_f16_flags(half %arg0, half %arg1, half %arg2) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_flags:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_flags:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_flags:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_flags:
; GFX9: ; %bb.0:
@@ -145,14 +163,23 @@ define half @fmed3_f32_fpext_f16_k0(half %arg1, half %arg2) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_k0:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e32 v2, 2.0, v0
-; GFX8-NEXT: v_min_f16_e32 v0, 2.0, v0
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v2, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e32 v2, 2.0, v0
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, 2.0, v0
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e32 v2, 2.0, v0
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, 2.0, v0
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v2, v1
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_k0:
; GFX9: ; %bb.0:
@@ -179,14 +206,23 @@ define half @fmed3_f32_fpext_f16_k1(half %arg0, half %arg2) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_k1:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e32 v2, 2.0, v0
-; GFX8-NEXT: v_min_f16_e32 v0, 2.0, v0
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v2, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k1:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e32 v2, 2.0, v0
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, 2.0, v0
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k1:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e32 v2, 2.0, v0
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, 2.0, v0
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v2, v1
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_k1:
; GFX9: ; %bb.0:
@@ -213,14 +249,23 @@ define half @fmed3_f32_fpext_f16_k2(half %arg0, half %arg1) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_k2:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e32 v2, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0
-; GFX8-NEXT: v_min_f16_e32 v0, v2, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k2:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e32 v2, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, 2.0, v0
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k2:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e32 v2, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, 2.0, v2
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_k2:
; GFX9: ; %bb.0:
@@ -247,15 +292,25 @@ define half @fmed3_f32_fpext_f16_k0_k1(half %arg2) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_k0_k1:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x4c00
-; GFX8-NEXT: v_max_f16_e32 v2, 0, v1
-; GFX8-NEXT: v_min_f16_e32 v1, 0, v1
-; GFX8-NEXT: v_max_f16_e32 v0, v1, v0
-; GFX8-NEXT: v_min_f16_e32 v0, v2, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k0_k1:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_mov_b32_e32 v1, 0x4c00
+; GFX8-SDAG-NEXT: v_max_f16_e32 v2, 0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v1, 0, v1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k0_k1:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_mov_b32_e32 v1, 0x4c00
+; GFX8-GISEL-NEXT: v_min_f16_e32 v2, 0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, 0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v2, v0
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_k0_k1:
; GFX9: ; %bb.0:
@@ -280,14 +335,23 @@ define half @fmed3_f32_fpext_f16_k0_k2(half %arg1) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_k0_k2:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e32 v1, 0, v0
-; GFX8-NEXT: v_min_f16_e32 v0, 0, v0
-; GFX8-NEXT: v_max_f16_e32 v0, 2.0, v0
-; GFX8-NEXT: v_min_f16_e32 v0, v1, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_k0_k2:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e32 v1, 0, v0
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, 0, v0
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, 2.0, v0
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_k0_k2:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e32 v1, 0, v0
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, 0, v0
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, 2.0, v1
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_k0_k2:
; GFX9: ; %bb.0:
@@ -313,14 +377,23 @@ define half @fmed3_f32_fpext_f16_fabs(half %arg0, half %arg1, half %arg2) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_fabs:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e64 v3, |v0|, |v1|
-; GFX8-NEXT: v_min_f16_e64 v0, |v0|, |v1|
-; GFX8-NEXT: v_max_f16_e64 v0, v0, |v2|
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_fabs:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e64 v3, |v0|, |v1|
+; GFX8-SDAG-NEXT: v_min_f16_e64 v0, |v0|, |v1|
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, v0, |v2|
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fabs:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e64 v3, |v0|, |v1|
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, |v0|, |v1|
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, v3, |v2|
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_fabs:
; GFX9: ; %bb.0:
@@ -404,14 +477,23 @@ define half @fmed3_f32_fpext_f16_fneg(half %arg0, half %arg1, half %arg2) #1 {
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_fneg:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e64 v3, -v0, -v1
-; GFX8-NEXT: v_min_f16_e64 v0, -v0, -v1
-; GFX8-NEXT: v_max_f16_e64 v0, v0, -v2
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_fneg:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e64 v3, -v0, -v1
+; GFX8-SDAG-NEXT: v_min_f16_e64 v0, -v0, -v1
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, v0, -v2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fneg:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e64 v3, -v0, -v1
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, -v0, -v1
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, v3, -v2
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_fneg:
; GFX9: ; %bb.0:
@@ -465,14 +547,23 @@ define half @fmed3_f32_fpext_f16_fneg_fabs(half %arg0, half %arg1, half %arg2) #
; GFX7-NEXT: v_cvt_f16_f32_e32 v0, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_fneg_fabs:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_max_f16_e64 v3, -|v0|, -|v1|
-; GFX8-NEXT: v_min_f16_e64 v0, -|v0|, -|v1|
-; GFX8-NEXT: v_max_f16_e64 v0, v0, -|v2|
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_fneg_fabs:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_max_f16_e64 v3, -|v0|, -|v1|
+; GFX8-SDAG-NEXT: v_min_f16_e64 v0, -|v0|, -|v1|
+; GFX8-SDAG-NEXT: v_max_f16_e64 v0, v0, -|v2|
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_fneg_fabs:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_min_f16_e64 v3, -|v0|, -|v1|
+; GFX8-GISEL-NEXT: v_max_f16_e64 v0, -|v0|, -|v1|
+; GFX8-GISEL-NEXT: v_max_f16_e64 v1, v3, -|v2|
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_fneg_fabs:
; GFX9: ; %bb.0:
@@ -617,17 +708,29 @@ define half @fmed3_f32_fpext_f16_multi_use_0(half %arg0, half %arg1, half %arg2,
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_multi_use_0:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v0
-; GFX8-NEXT: flat_store_dword v[3:4], v5
-; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_multi_use_0:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v5, v0
+; GFX8-SDAG-NEXT: flat_store_dword v[3:4], v5
+; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_multi_use_0:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v5, v0
+; GFX8-GISEL-NEXT: flat_store_dword v[3:4], v5
+; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_0:
; GFX9: ; %bb.0:
@@ -662,17 +765,29 @@ define half @fmed3_f32_fpext_f16_multi_use_1(half %arg0, half %arg1, half %arg2,
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_multi_use_1:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v1
-; GFX8-NEXT: flat_store_dword v[3:4], v5
-; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_multi_use_1:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX8-SDAG-NEXT: flat_store_dword v[3:4], v5
+; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_multi_use_1:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v5, v1
+; GFX8-GISEL-NEXT: flat_store_dword v[3:4], v5
+; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_1:
; GFX9: ; %bb.0:
@@ -707,17 +822,29 @@ define half @fmed3_f32_fpext_f16_multi_use_2(half %arg0, half %arg1, half %arg2,
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
-; GFX8-LABEL: fmed3_f32_fpext_f16_multi_use_2:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_e32 v5, v2
-; GFX8-NEXT: flat_store_dword v[3:4], v5
-; GFX8-NEXT: v_max_f16_e32 v3, v0, v1
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v1
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v2
-; GFX8-NEXT: v_min_f16_e32 v0, v3, v0
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: s_setpc_b64 s[30:31]
+; GFX8-SDAG-LABEL: fmed3_f32_fpext_f16_multi_use_2:
+; GFX8-SDAG: ; %bb.0:
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-SDAG-NEXT: v_cvt_f32_f16_e32 v5, v2
+; GFX8-SDAG-NEXT: flat_store_dword v[3:4], v5
+; GFX8-SDAG-NEXT: v_max_f16_e32 v3, v0, v1
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_max_f16_e32 v0, v0, v2
+; GFX8-SDAG-NEXT: v_min_f16_e32 v0, v3, v0
+; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0)
+; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-GISEL-LABEL: fmed3_f32_fpext_f16_multi_use_2:
+; GFX8-GISEL: ; %bb.0:
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-GISEL-NEXT: v_cvt_f32_f16_e32 v5, v2
+; GFX8-GISEL-NEXT: flat_store_dword v[3:4], v5
+; GFX8-GISEL-NEXT: v_min_f16_e32 v3, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_max_f16_e32 v1, v3, v2
+; GFX8-GISEL-NEXT: v_min_f16_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: fmed3_f32_fpext_f16_multi_use_2:
; GFX9: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
index 2ce2efcfe49ec..24f035bd85e5c 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu10.30-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.30-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu10.30-amd-amdpal < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX1011,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
; Test fmul by power of 2 which is better emitted as ldexp
@@ -5828,21 +5828,44 @@ define half @v_mul_f16_select_n1_n64(i32 %arg, half %x) {
}
define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
-; GFX9-LABEL: v_mul_f16_select_128_64:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc
-; GFX9-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_mul_f16_select_128_64:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc
+; GFX9-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_mul_f16_select_128_64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
-; GFX10-NEXT: v_ldexp_f16_e32 v0, v1, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_mul_f16_select_128_64:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v2, v3
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_mul_f16_select_128_64:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX10-SDAG-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_mul_f16_select_128_64:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_128_64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -5864,7 +5887,10 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5872,7 +5898,10 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
@@ -5882,21 +5911,44 @@ define half @v_mul_f16_select_128_64(i32 %arg, half %x) {
}
define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
-; GFX9-LABEL: v_mul_f16_select_n128_n64:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc
-; GFX9-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_mul_f16_select_n128_n64:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc
+; GFX9-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_mul_f16_select_n128_n64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
-; GFX10-NEXT: v_ldexp_f16_e64 v0, -v1, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_mul_f16_select_n128_n64:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v2, v3
+; GFX9-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_mul_f16_select_n128_n64:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX10-SDAG-NEXT: v_ldexp_f16_e64 v0, -v1, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_mul_f16_select_n128_n64:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
+; GFX10-GISEL-NEXT: v_ldexp_f16_e64 v0, -v1, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_mul_f16_select_n128_n64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -5918,7 +5970,10 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e64 v0.l, -v1.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -5926,7 +5981,10 @@ define half @v_mul_f16_select_n128_n64(i32 %arg, half %x) {
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 6, 7, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v2
; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e64 v0, -v1, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
@@ -6310,24 +6368,49 @@ define half @v_contract_mul_add_f16_select_n1_n64(i32 %arg, half %x, half %y) {
}
define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
-; GFX9-LABEL: v_contract_mul_add_f16_select_128_64:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x5400
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x5800
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x5400
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x5800
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_contract_mul_add_f16_select_128_64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v3, 0x5800
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x5800
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_128_64:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_128_64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6350,19 +6433,25 @@ define half @v_contract_mul_add_f16_select_128_64(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_128_64:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x5400
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0x5800, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_128_64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x5800
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select i1 %cond, half 128.0, half 64.0
@@ -6452,24 +6541,49 @@ define half @v_contract_mul_add_f16_select_128_4(i32 %arg, half %x, half %y) {
}
define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
-; GFX9-LABEL: v_contract_mul_add_f16_select_2_4:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x4400
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x4000
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x4400
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4000
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_contract_mul_add_f16_select_2_4:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v3, 0x4000
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
-; GFX10-NEXT: v_fma_f16 v0, v1, v0, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 2, v0
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x4000
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_contract_mul_add_f16_select_2_4:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v0, v2
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_f16_select_2_4:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6492,19 +6606,25 @@ define half @v_contract_mul_add_f16_select_2_4(i32 %arg, half %x, half %y) {
; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_f16_select_2_4:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x4400
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0x4000, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_fma_f16 v0.l, v1.l, v0.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v2.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_f16_select_2_4:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x4000
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v3, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_fma_f16 v0, v1, v0, v2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v0, v2
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq i32 %arg, 0
%select.pow2 = select i1 %cond, half 2.0, half 4.0
@@ -6910,30 +7030,66 @@ define <2 x half> @v_mul_v2f16_select_n1_n64(<2 x i32> %arg, <2 x half> %x) {
}
define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) {
-; GFX9-LABEL: v_mul_v2f16_select_128_64:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, 0x5400
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x5800
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX9-NEXT: v_pk_mul_f16 v0, v2, v0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_mul_v2f16_select_128_64:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0x5400
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x5800
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-SDAG-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_mul_v2f16_select_128_64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v3, 0x5800
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x5400, v3, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX10-NEXT: v_pk_mul_f16 v0, v2, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_mul_v2f16_select_128_64:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0
+; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 6, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_mul_v2f16_select_128_64:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0x5800
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x5400, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX10-SDAG-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_mul_v2f16_select_128_64:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_128_64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -6961,24 +7117,35 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_128_64:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0x5400
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0x5800, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0x5800, s0
-; GFX11-GISEL-TRUE16-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_128_64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x5800
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x5400, v3, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x5400, v3, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
%select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 64.0, half 64.0>
@@ -6987,30 +7154,68 @@ define <2 x half> @v_mul_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x) {
}
define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) {
-; GFX9-LABEL: v_mul_v2f16_select_n128_n64:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v3, 0xd400
-; GFX9-NEXT: v_mov_b32_e32 v4, 0xd800
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX9-NEXT: v_pk_mul_f16 v0, v2, v0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v3, 0xd400
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0xd800
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v3, v4, vcc
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-SDAG-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_mul_v2f16_select_n128_n64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v3, 0xd800
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0xd400, v3, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
-; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX10-NEXT: v_pk_mul_f16 v0, v2, v0
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0
+; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 6, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX9-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v3, v4
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v3, v4
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v3, 0xd800
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0xd400, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
+; GFX10-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX10-SDAG-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_mul_v2f16_select_n128_n64:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX10-GISEL-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_mul_v2f16_select_n128_n64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -7038,24 +7243,37 @@ define <2 x half> @v_mul_v2f16_select_n128_n64(<2 x i32> %arg, <2 x half> %x) {
; GFX11-GISEL-TRUE16-LABEL: v_mul_v2f16_select_n128_n64:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, 0xd400
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.h, v3.l, 0xd800, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, 0xd800, s0
-; GFX11-GISEL-TRUE16-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x7fff :: v_dual_add_nc_u32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_mul_v2f16_select_n128_n64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0xd800
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0xd400, v3, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0xd400, v3, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_pk_mul_f16 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_xor_b32_e32 v2, 0x80008000, v2
+; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v3, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v1, 6, v1
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v3
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v4, v1
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
%select.pow2 = select <2 x i1> %cond, <2 x half> <half -128.0, half -128.0>, <2 x half> <half -64.0, half -64.0>
@@ -7616,30 +7834,68 @@ define <2 x half> @v_contract_mul_add_v2f16_select_n1_n64(<2 x i32> %arg, <2 x h
}
define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x half> %x, <2 x half> %y) {
-; GFX9-LABEL: v_contract_mul_add_v2f16_select_128_64:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x5400
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x5800
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX9-NEXT: v_pk_fma_f16 v0, v2, v0, v3
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x5400
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x5800
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_contract_mul_add_v2f16_select_128_64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v4, 0x5800
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x5400, v4, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x5400, v4, vcc_lo
-; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX10-NEXT: v_pk_fma_f16 v0, v2, v0, v3
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 6, v0
+; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 6, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v4, v5
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v4, v5
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v4, 0x5800
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x5400, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x5400, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX10-SDAG-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_128_64:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 6, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_128_64:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -7667,24 +7923,36 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_64(<2 x i32> %arg, <2 x h
; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_128_64:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x5400
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, 0x5800, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, 0x5800, s0
-; GFX11-GISEL-TRUE16-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_128_64:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v4, 0x5800
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x5400, v4, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x5400, v4, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 6, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 6, v1
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v5, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
%select.pow2 = select <2 x i1> %cond, <2 x half> <half 128.0, half 128.0>, <2 x half> <half 64.0, half 64.0>
@@ -7803,30 +8071,68 @@ define <2 x half> @v_contract_mul_add_v2f16_select_128_4(<2 x i32> %arg, <2 x ha
}
define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half> %x, <2 x half> %y) {
-; GFX9-LABEL: v_contract_mul_add_v2f16_select_2_4:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v4, 0x4400
-; GFX9-NEXT: v_mov_b32_e32 v5, 0x4000
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
-; GFX9-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX9-NEXT: v_pk_fma_f16 v0, v2, v0, v3
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX9-SDAG-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX9-SDAG: ; %bb.0:
+; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v4, 0x4400
+; GFX9-SDAG-NEXT: v_mov_b32_e32 v5, 0x4000
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; GFX9-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc
+; GFX9-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_contract_mul_add_v2f16_select_2_4:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v4, 0x4000
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_cndmask_b32_e32 v0, 0x4400, v4, vcc_lo
-; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX10-NEXT: v_pk_fma_f16 v0, v2, v0, v3
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX9-GISEL-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX9-GISEL: ; %bb.0:
+; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
+; GFX9-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX9-GISEL-NEXT: v_add_u32_e32 v0, 2, v0
+; GFX9-GISEL-NEXT: v_add_u32_e32 v1, 2, v1
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v4, 0xffff8000
+; GFX9-GISEL-NEXT: v_mov_b32_e32 v5, 0x7fff
+; GFX9-GISEL-NEXT: v_med3_i32 v0, v0, v4, v5
+; GFX9-GISEL-NEXT: v_med3_i32 v1, v1, v4, v5
+; GFX9-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX9-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
+; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-SDAG-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX10-SDAG: ; %bb.0:
+; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-SDAG-NEXT: v_mov_b32_e32 v4, 0x4000
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-SDAG-NEXT: v_cndmask_b32_e32 v0, 0x4400, v4, vcc_lo
+; GFX10-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
+; GFX10-SDAG-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-GISEL-LABEL: v_contract_mul_add_v2f16_select_2_4:
+; GFX10-GISEL: ; %bb.0:
+; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-GISEL-NEXT: v_mov_b32_e32 v4, 0x7fff
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX10-GISEL-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX10-GISEL-NEXT: v_add_nc_u32_e32 v1, 2, v1
+; GFX10-GISEL-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX10-GISEL-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX10-GISEL-NEXT: v_ldexp_f16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX10-GISEL-NEXT: v_pk_add_f16 v0, v0, v3
+; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-TRUE16-LABEL: v_contract_mul_add_v2f16_select_2_4:
; GFX11-SDAG-TRUE16: ; %bb.0:
@@ -7854,24 +8160,36 @@ define <2 x half> @v_contract_mul_add_v2f16_select_2_4(<2 x i32> %arg, <2 x half
; GFX11-GISEL-TRUE16-LABEL: v_contract_mul_add_v2f16_select_2_4:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0x4400
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, 0x4000, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, 0x4000, s0
-; GFX11-GISEL-TRUE16-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-GISEL-TRUE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-TRUE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.l, v2.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_ldexp_f16_e32 v0.h, v2.h, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_contract_mul_add_v2f16_select_2_4:
; GFX11-GISEL-FAKE16: ; %bb.0:
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v4, 0x4000
-; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v1, 0x4400, v4, vcc_lo
; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, 0x4400, v4, vcc_lo
-; GFX11-GISEL-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT: v_pk_fma_f16 v0, v2, v0, v3
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_add_nc_u32_e32 v0, 2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v4, 0x7fff :: v_dual_add_nc_u32 v1, 2, v1
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v0, 0xffff8000, v0, v4
+; GFX11-GISEL-FAKE16-NEXT: v_med3_i32 v1, 0xffff8000, v1, v4
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v0, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_ldexp_f16_e32 v1, v5, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-GISEL-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_pk_add_f16 v0, v0, v3
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cond = icmp eq <2 x i32> %arg, zeroinitializer
%select.pow2 = select <2 x i1> %cond, <2 x half> <half 2.0, half 2.0>, <2 x half> <half 4.0, half 4.0>
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log.ll b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
index 3fcec611b218b..73c5ff59e769b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log.ll
@@ -14,122 +14,266 @@
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s2
-; SI-NEXT: v_ldexp_f32_e32 v1, s6, v1
-; SI-NEXT: v_log_f32_e32 v1, v1
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
-; SI-NEXT: v_fma_f32 v3, v1, s4, -v2
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v3, v1, s4, v3
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-NEXT: s_cselect_b32 s0, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s0
-; VI-NEXT: v_ldexp_f32 v1, s2, v1
-; VI-NEXT: v_log_f32_e32 v1, v1
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_mov_b32 s2, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e32 v3, v1, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v5, 0x3f317000, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v3
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-NEXT: v_add_f32_e32 v3, v5, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v1, v0
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX900-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-NEXT: v_ldexp_f32 v1, s6, v1
-; GFX900-NEXT: v_log_f32_e32 v1, v1
-; GFX900-NEXT: s_mov_b32 s2, 0x3f317217
-; GFX900-NEXT: s_mov_b32 s3, 0x3377d1cf
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3f317217, v1
-; GFX900-NEXT: v_fma_f32 v4, v1, s2, -v3
-; GFX900-NEXT: v_fma_f32 v4, v1, s3, v4
-; GFX900-NEXT: s_mov_b32 s2, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX900-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s1
-; GFX1100-NEXT: s_and_b32 s1, s1, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s1, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v1, s0, s1
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-NEXT: v_fma_f32 v3, 0x3f317217, v1, -v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v3, v1, 0x3377d1cf, v3
-; GFX1100-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s6, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, -v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, v3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317000, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v5, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v1, v0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3f317217
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v1
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s2, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s3, v4
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s1
+; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3f317217, v1, -v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3377d1cf, v3
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_f32:
; R600: ; %bb.0:
@@ -203,122 +347,266 @@ define amdgpu_kernel void @s_log_f32(ptr addrspace(1) %out, float %in) {
}
define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log_contract_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s2
-; SI-NEXT: v_ldexp_f32_e32 v1, s6, v1
-; SI-NEXT: v_log_f32_e32 v1, v1
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
-; SI-NEXT: v_fma_f32 v3, v1, s4, -v2
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v3, v1, s4, v3
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log_contract_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-NEXT: s_cselect_b32 s0, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s0
-; VI-NEXT: v_ldexp_f32 v1, s2, v1
-; VI-NEXT: v_log_f32_e32 v1, v1
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_mov_b32 s2, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e32 v3, v1, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v5, 0x3f317000, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v3
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-NEXT: v_add_f32_e32 v3, v5, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v1, v0
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log_contract_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX900-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-NEXT: v_ldexp_f32 v1, s6, v1
-; GFX900-NEXT: v_log_f32_e32 v1, v1
-; GFX900-NEXT: s_mov_b32 s2, 0x3f317217
-; GFX900-NEXT: s_mov_b32 s3, 0x3377d1cf
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3f317217, v1
-; GFX900-NEXT: v_fma_f32 v4, v1, s2, -v3
-; GFX900-NEXT: v_fma_f32 v4, v1, s3, v4
-; GFX900-NEXT: s_mov_b32 s2, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX900-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log_contract_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s1
-; GFX1100-NEXT: s_and_b32 s1, s1, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s1, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v1, s0, s1
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-NEXT: v_fma_f32 v3, 0x3f317217, v1, -v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v3, v1, 0x3377d1cf, v3
-; GFX1100-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log_contract_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s6, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, -v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, v3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log_contract_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log_contract_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317000, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v5, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v1, v0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log_contract_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log_contract_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3f317217
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v1
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s2, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s3, v4
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log_contract_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log_contract_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s1
+; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3f317217, v1, -v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3377d1cf, v3
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log_contract_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_contract_f32:
; R600: ; %bb.0:
@@ -394,176 +682,404 @@ define amdgpu_kernel void @s_log_contract_f32(ptr addrspace(1) %out, float %in)
; FIXME: We should be able to merge these packets together on Cayman so we
; have a maximum of 4 instructions.
define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
-; SI-LABEL: s_log_v2f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: s_mov_b32 s8, 0x3f317217
-; SI-NEXT: s_mov_b32 s9, 0x7f800000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_mov_b32_e32 v3, s2
-; SI-NEXT: v_ldexp_f32_e32 v3, s5, v3
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v4, 0x3f317217, v3
-; SI-NEXT: s_cselect_b32 s6, 32, 0
-; SI-NEXT: s_mov_b32 s5, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v5, v3, s8, -v4
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s6
-; SI-NEXT: v_fma_f32 v5, v3, s5, v5
-; SI-NEXT: v_ldexp_f32_e32 v1, s4, v1
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_log_f32_e32 v5, v1
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
-; SI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; SI-NEXT: v_sub_f32_e32 v1, v1, v2
-; SI-NEXT: v_mul_f32_e32 v2, 0x3f317217, v5
-; SI-NEXT: v_fma_f32 v3, v5, s8, -v2
-; SI-NEXT: v_fma_f32 v3, v5, s5, v3
-; SI-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s9
-; SI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v0, v2, v0
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log_v2f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: s_cselect_b32 s4, 32, 0
-; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: v_ldexp_f32 v3, s3, v3
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
-; VI-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
-; VI-NEXT: s_cselect_b32 s4, 32, 0
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_ldexp_f32 v1, s2, v1
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_log_f32_e32 v5, v1
-; VI-NEXT: s_mov_b32 s3, 0x7f800000
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v1, v1, v2
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v5
-; VI-NEXT: v_sub_f32_e32 v3, v5, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3f317000, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v3
-; VI-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v2
-; VI-NEXT: v_add_f32_e32 v3, v6, v3
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
-; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v2, v0
-; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v2, s0
-; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log_v2f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: s_mov_b32 s6, 0x3377d1cf
-; GFX900-NEXT: s_mov_b32 s7, 0x7f800000
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_mov_b32_e32 v4, s4
-; GFX900-NEXT: v_ldexp_f32 v4, s3, v4
-; GFX900-NEXT: v_log_f32_e32 v4, v4
-; GFX900-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_mov_b32 s3, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3f317217, v4
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_fma_f32 v6, v4, s3, -v5
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s4
-; GFX900-NEXT: v_fma_f32 v6, v4, s6, v6
-; GFX900-NEXT: v_ldexp_f32 v1, s2, v1
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_log_f32_e32 v6, v1
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s7
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; GFX900-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3f317217, v6
-; GFX900-NEXT: v_fma_f32 v4, v6, s3, -v3
-; GFX900-NEXT: v_fma_f32 v4, v6, s6, v4
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-NEXT: v_sub_f32_e32 v0, v3, v0
-; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log_v2f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s4
-; GFX1100-NEXT: s_and_b32 s4, s4, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s5
-; GFX1100-NEXT: v_ldexp_f32 v1, s3, s4
-; GFX1100-NEXT: s_and_b32 s5, s5, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s5, 32, 0
-; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_ldexp_f32 v3, s2, s5
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1100-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
-; GFX1100-NEXT: v_fma_f32 v6, 0x3f317217, v1, -v4
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v7, 0x3f317217, v3, -v5
-; GFX1100-NEXT: v_dual_fmac_f32 v6, 0x3377d1cf, v1 :: v_dual_fmac_f32 v7, 0x3377d1cf, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
-; GFX1100-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_mov_b32 v4, 0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1100-NEXT: v_dual_sub_f32 v1, v1, v0 :: v_dual_sub_f32 v0, v3, v2
-; GFX1100-NEXT: global_store_b64 v4, v[0:1], s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log_v2f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: s_mov_b32 s8, 0x3f317217
+; SI-SDAG-NEXT: s_mov_b32 s9, 0x7f800000
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s5, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v3
+; SI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s8, -v4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s6
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s5, v5
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s4, v1
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_log_f32_e32 v5, v1
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v5
+; SI-SDAG-NEXT: v_fma_f32 v3, v5, s8, -v2
+; SI-SDAG-NEXT: v_fma_f32 v3, v5, s5, v3
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log_v2f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log_v2f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
+; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_log_f32_e32 v5, v1
+; VI-SDAG-NEXT: s_mov_b32 s3, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v5
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v5, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v6, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log_v2f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log_v2f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x3377d1cf
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x7f800000
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX900-SDAG-NEXT: v_ldexp_f32 v4, s3, v4
+; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v4
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s3, -v5
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s6, v6
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v1
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s7
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s3, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s6, v4
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
+; GFX900-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log_v2f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log_v2f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s4
+; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x41b17218, s5
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
+; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
+; GFX1100-SDAG-NEXT: v_fma_f32 v6, 0x3f317217, v1, -v4
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3f317217, v3, -v5
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v6, 0x3377d1cf, v1 :: v_dual_fmac_f32 v7, 0x3377d1cf, v3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_mov_b32 v4, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v1, v0 :: v_dual_sub_f32 v0, v3, v2
+; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log_v2f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s5
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, s6, s5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s6
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s5, s4
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s3, s2
+; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_v2f32:
; R600: ; %bb.0:
@@ -676,242 +1192,571 @@ define amdgpu_kernel void @s_log_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
}
define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
-; SI-LABEL: s_log_v3f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v2, 0x41b17218
-; SI-NEXT: s_mov_b32 s6, 0x3f317217
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_mov_b32_e32 v3, s2
-; SI-NEXT: v_ldexp_f32_e32 v3, s9, v3
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_mul_f32_e32 v4, 0x3f317217, v3
-; SI-NEXT: v_mov_b32_e32 v6, s4
-; SI-NEXT: v_fma_f32 v5, v3, s6, -v4
-; SI-NEXT: s_mov_b32 s7, 0x3377d1cf
-; SI-NEXT: v_ldexp_f32_e32 v6, s8, v6
-; SI-NEXT: v_fma_f32 v5, v3, s7, v5
-; SI-NEXT: s_mov_b32 s9, 0x7f800000
-; SI-NEXT: v_log_f32_e32 v6, v6
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, 0, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_sub_f32_e32 v1, v3, v1
-; SI-NEXT: v_mul_f32_e32 v3, 0x3f317217, v6
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_fma_f32 v4, v6, s6, -v3
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: v_fma_f32 v4, v6, s7, v4
-; SI-NEXT: v_ldexp_f32_e32 v0, s10, v0
-; SI-NEXT: v_add_f32_e32 v3, v3, v4
-; SI-NEXT: v_log_f32_e32 v4, v0
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s9
-; SI-NEXT: v_cndmask_b32_e32 v0, v6, v3, vcc
-; SI-NEXT: v_mul_f32_e32 v3, 0x3f317217, v4
-; SI-NEXT: v_sub_f32_e32 v0, v0, v5
-; SI-NEXT: v_fma_f32 v5, v4, s6, -v3
-; SI-NEXT: v_fma_f32 v5, v4, s7, v5
-; SI-NEXT: v_add_f32_e32 v3, v3, v5
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s9
-; SI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v2, v3, v2
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log_v3f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: s_cselect_b32 s3, 32, 0
-; VI-NEXT: v_mov_b32_e32 v3, s3
-; VI-NEXT: v_ldexp_f32 v3, s2, v3
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
-; VI-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
-; VI-NEXT: s_cselect_b32 s4, 32, 0
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s4
-; VI-NEXT: v_ldexp_f32 v6, s1, v6
-; VI-NEXT: v_log_f32_e32 v6, v6
-; VI-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: s_mov_b32 s6, 0x7f800000
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s6
-; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v3, v2
-; VI-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-NEXT: v_sub_f32_e32 v4, v6, v3
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mul_f32_e32 v7, 0x3f317000, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v4
-; VI-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v3
-; VI-NEXT: s_cselect_b32 s1, 32, 0
-; VI-NEXT: v_add_f32_e32 v4, v8, v4
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_f32_e32 v4, v7, v4
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-NEXT: v_ldexp_f32 v1, s0, v1
-; VI-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-NEXT: v_log_f32_e32 v4, v1
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s6
-; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
-; VI-NEXT: v_sub_f32_e32 v1, v1, v5
-; VI-NEXT: v_and_b32_e32 v3, 0xfffff000, v4
-; VI-NEXT: v_sub_f32_e32 v5, v4, v3
-; VI-NEXT: v_mul_f32_e32 v6, 0x3f317000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
-; VI-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v3
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
-; VI-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s6
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v3, v0
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v4, s3
-; VI-NEXT: v_mov_b32_e32 v3, s2
-; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log_v3f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: s_mov_b32 s8, 0x7f800000
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-NEXT: v_mov_b32_e32 v3, s3
-; GFX900-NEXT: v_ldexp_f32 v3, s2, v3
-; GFX900-NEXT: v_log_f32_e32 v3, v3
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
-; GFX900-NEXT: v_mov_b32_e32 v7, s2
-; GFX900-NEXT: s_mov_b32 s5, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v6, v3, s4, -v5
-; GFX900-NEXT: v_ldexp_f32 v7, s1, v7
-; GFX900-NEXT: v_fma_f32 v6, v3, s5, v6
-; GFX900-NEXT: v_log_f32_e32 v7, v7
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3f317217, v7
-; GFX900-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-NEXT: v_fma_f32 v5, v7, s4, -v3
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-NEXT: v_fma_f32 v5, v7, s5, v5
-; GFX900-NEXT: v_ldexp_f32 v1, s0, v1
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX900-NEXT: v_log_f32_e32 v5, v1
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
-; GFX900-NEXT: v_sub_f32_e32 v1, v1, v6
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3f317217, v5
-; GFX900-NEXT: v_fma_f32 v6, v5, s4, -v3
-; GFX900-NEXT: v_fma_f32 v6, v5, s5, v6
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s8
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-NEXT: v_sub_f32_e32 v0, v3, v0
-; GFX900-NEXT: global_store_dwordx3 v4, v[0:2], s[6:7]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log_v3f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s3
-; GFX1100-NEXT: s_and_b32 s3, s3, exec_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s6
-; GFX1100-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v2, s2, s3
-; GFX1100-NEXT: v_ldexp_f32 v4, s1, s6
-; GFX1100-NEXT: v_cndmask_b32_e64 v3, 0, 0x41b17218, s7
-; GFX1100-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-NEXT: v_log_f32_e32 v4, v4
-; GFX1100-NEXT: v_ldexp_f32 v5, s0, s2
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v5, v5
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_dual_mul_f32 v6, 0x3f317217, v2 :: v_dual_mul_f32 v7, 0x3f317217, v4
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-NEXT: v_fma_f32 v9, 0x3f317217, v2, -v6
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v10, 0x3f317217, v4, -v7
-; GFX1100-NEXT: v_dual_fmac_f32 v9, 0x3377d1cf, v2 :: v_dual_fmac_f32 v10, 0x3377d1cf, v4
-; GFX1100-NEXT: v_mul_f32_e32 v8, 0x3f317217, v5
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v7, v7, v10
-; GFX1100-NEXT: v_fma_f32 v11, 0x3f317217, v5, -v8
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
-; GFX1100-NEXT: v_dual_fmac_f32 v11, 0x3377d1cf, v5 :: v_dual_sub_f32 v2, v2, v0
-; GFX1100-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-NEXT: v_add_f32_e32 v8, v8, v11
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v5|
-; GFX1100-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_sub_f32 v1, v4, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v5, v3
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b96 v6, v[0:2], s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log_v3f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x41b17218
+; SI-SDAG-NEXT: s_mov_b32 s6, 0x3f317217
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s9, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v3
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s6, -v4
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x3377d1cf
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v6, s8, v6
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s7, v5
+; SI-SDAG-NEXT: s_mov_b32 s9, 0x7f800000
+; SI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v6
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s6, -v3
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s7, v4
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, s10, v0
+; SI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; SI-SDAG-NEXT: v_log_f32_e32 v4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v3, vcc
+; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v4
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v5
+; SI-SDAG-NEXT: v_fma_f32 v5, v4, s6, -v3
+; SI-SDAG-NEXT: v_fma_f32 v5, v4, s7, v5
+; SI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; SI-SDAG-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log_v3f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s8, s8, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s1, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
+; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s3, s7, s3
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s8, v5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v6
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v6
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log_v3f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
+; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; VI-SDAG-NEXT: v_ldexp_f32 v6, s1, v6
+; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: s_mov_b32 s6, 0x7f800000
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v3
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v3
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v8, v4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v7, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-SDAG-NEXT: v_log_f32_e32 v4, v1
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
+; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v4
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3f317000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s3
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log_v3f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s6, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; VI-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0
+; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log_v3f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
+; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s2
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s4, -v5
+; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s5, v6
+; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v7
+; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s4, -v3
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s5, v5
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-SDAG-NEXT: v_log_f32_e32 v5, v1
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v6
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3f317217, v5
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s4, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s5, v6
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s8
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
+; GFX900-SDAG-NEXT: global_store_dwordx3 v4, v[0:2], s[6:7]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log_v3f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
+; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3f317217, v6
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log_v3f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s3
+; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s6
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x41b17218, s7
+; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v6, 0x3f317217, v2 :: v_dual_mul_f32 v7, 0x3f317217, v4
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
+; GFX1100-SDAG-NEXT: v_fma_f32 v9, 0x3f317217, v2, -v6
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v10, 0x3f317217, v4, -v7
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v9, 0x3377d1cf, v2 :: v_dual_fmac_f32 v10, 0x3377d1cf, v4
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v8, 0x3f317217, v5
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v7, v7, v10
+; GFX1100-SDAG-NEXT: v_fma_f32 v11, 0x3f317217, v5, -v8
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v11, 0x3377d1cf, v5 :: v_dual_sub_f32 v2, v2, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v8, v11
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v5|
+; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_sub_f32 v1, v4, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v5, v3
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b96 v6, v[0:2], s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log_v3f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s6
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s6, s3
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s7, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s9, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s3
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log_v3f32:
; R600: ; %bb.0:
@@ -1065,333 +1910,752 @@ define amdgpu_kernel void @s_log_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
; FIXME: We should be able to merge these packets together on Cayman so we
; have a maximum of 4 instructions.
define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
-; SI-LABEL: s_log_v4f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: s_mov_b32 s6, 0x3f317217
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s11, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_mov_b32_e32 v3, s2
-; SI-NEXT: v_ldexp_f32_e32 v3, s11, v3
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v4, 0x3f317217, v3
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_fma_f32 v5, v3, s6, -v4
-; SI-NEXT: s_mov_b32 s7, 0x3377d1cf
-; SI-NEXT: v_mov_b32_e32 v6, s4
-; SI-NEXT: v_fma_f32 v5, v3, s7, v5
-; SI-NEXT: s_mov_b32 s11, 0x7f800000
-; SI-NEXT: v_ldexp_f32_e32 v6, s10, v6
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; SI-NEXT: v_log_f32_e32 v6, v6
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s11
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_sub_f32_e32 v3, v3, v2
-; SI-NEXT: v_mul_f32_e32 v2, 0x3f317217, v6
-; SI-NEXT: v_mov_b32_e32 v7, s4
-; SI-NEXT: v_fma_f32 v4, v6, s6, -v2
-; SI-NEXT: v_ldexp_f32_e32 v7, s9, v7
-; SI-NEXT: v_fma_f32 v4, v6, s7, v4
-; SI-NEXT: v_log_f32_e32 v7, v7
-; SI-NEXT: v_add_f32_e32 v2, v2, v4
-; SI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
-; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_sub_f32_e32 v2, v2, v5
-; SI-NEXT: v_mul_f32_e32 v5, 0x3f317217, v7
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_fma_f32 v6, v7, s6, -v5
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s4
-; SI-NEXT: v_fma_f32 v6, v7, s7, v6
-; SI-NEXT: v_ldexp_f32_e32 v1, s8, v1
-; SI-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-NEXT: v_log_f32_e32 v6, v1
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s11
-; SI-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
-; SI-NEXT: v_sub_f32_e32 v1, v1, v4
-; SI-NEXT: v_mul_f32_e32 v4, 0x3f317217, v6
-; SI-NEXT: v_fma_f32 v5, v6, s6, -v4
-; SI-NEXT: v_fma_f32 v5, v6, s7, v5
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
-; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v0, v4, v0
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log_v4f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: s_mov_b32 s8, 0x7f800000
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: s_cselect_b32 s6, 32, 0
-; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_ldexp_f32 v3, s3, v3
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
-; VI-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
-; VI-NEXT: s_cselect_b32 s3, 32, 0
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s3
-; VI-NEXT: v_ldexp_f32 v6, s2, v6
-; VI-NEXT: v_log_f32_e32 v6, v6
-; VI-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
-; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v3, v3, v2
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v6
-; VI-NEXT: v_sub_f32_e32 v4, v6, v2
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-NEXT: v_mul_f32_e32 v7, 0x3f317000, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v4
-; VI-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_add_f32_e32 v4, v8, v4
-; VI-NEXT: s_cselect_b32 s2, 32, 0
-; VI-NEXT: v_add_f32_e32 v4, v7, v4
-; VI-NEXT: v_mov_b32_e32 v7, s2
-; VI-NEXT: v_ldexp_f32 v7, s1, v7
-; VI-NEXT: v_log_f32_e32 v7, v7
-; VI-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
-; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v2, v5
-; VI-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-NEXT: v_sub_f32_e32 v6, v7, v5
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_mul_f32_e32 v8, 0x3f317000, v6
-; VI-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v6
-; VI-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5
-; VI-NEXT: s_cselect_b32 s1, 32, 0
-; VI-NEXT: v_add_f32_e32 v6, v9, v6
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_f32_e32 v6, v8, v6
-; VI-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
-; VI-NEXT: v_ldexp_f32 v1, s0, v1
-; VI-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-NEXT: v_log_f32_e32 v6, v1
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
-; VI-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
-; VI-NEXT: v_sub_f32_e32 v1, v1, v4
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v6
-; VI-NEXT: v_sub_f32_e32 v5, v6, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
-; VI-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v4
-; VI-NEXT: v_add_f32_e32 v5, v8, v5
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
-; VI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v4, v0
-; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: v_mov_b32_e32 v5, s5
-; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log_v4f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: s_mov_b32 s8, 0x3f317217
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_mov_b32_e32 v3, s4
-; GFX900-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX900-NEXT: v_log_f32_e32 v3, v3
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
-; GFX900-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-NEXT: s_mov_b32 s9, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v6, v3, s8, -v5
-; GFX900-NEXT: v_mov_b32_e32 v7, s3
-; GFX900-NEXT: v_fma_f32 v6, v3, s9, v6
-; GFX900-NEXT: s_mov_b32 s10, 0x7f800000
-; GFX900-NEXT: v_ldexp_f32 v7, s2, v7
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX900-NEXT: v_log_f32_e32 v7, v7
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX900-NEXT: v_mul_f32_e32 v2, 0x3f317217, v7
-; GFX900-NEXT: v_mov_b32_e32 v8, s2
-; GFX900-NEXT: v_fma_f32 v5, v7, s8, -v2
-; GFX900-NEXT: v_ldexp_f32 v8, s1, v8
-; GFX900-NEXT: v_fma_f32 v5, v7, s9, v5
-; GFX900-NEXT: v_log_f32_e32 v8, v8
-; GFX900-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX900-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_sub_f32_e32 v2, v2, v6
-; GFX900-NEXT: v_mul_f32_e32 v6, 0x3f317217, v8
-; GFX900-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-NEXT: v_fma_f32 v7, v8, s8, -v6
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-NEXT: v_fma_f32 v7, v8, s9, v7
-; GFX900-NEXT: v_ldexp_f32 v1, s0, v1
-; GFX900-NEXT: v_add_f32_e32 v6, v6, v7
-; GFX900-NEXT: v_log_f32_e32 v7, v1
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
-; GFX900-NEXT: v_sub_f32_e32 v1, v1, v5
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3f317217, v7
-; GFX900-NEXT: v_fma_f32 v6, v7, s8, -v5
-; GFX900-NEXT: v_fma_f32 v6, v7, s9, v6
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-NEXT: v_sub_f32_e32 v0, v5, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log_v4f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s6
-; GFX1100-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s7
-; GFX1100-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-NEXT: v_ldexp_f32 v2, s3, s6
-; GFX1100-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s8
-; GFX1100-NEXT: s_cselect_b32 s7, 32, 0
-; GFX1100-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-NEXT: s_and_b32 s6, s9, exec_lo
-; GFX1100-NEXT: v_ldexp_f32 v3, s2, s7
-; GFX1100-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v6, s1, s3
-; GFX1100-NEXT: v_ldexp_f32 v7, s0, s2
-; GFX1100-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: v_log_f32_e32 v6, v6
-; GFX1100-NEXT: v_log_f32_e32 v7, v7
-; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s9
-; GFX1100-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-NEXT: v_dual_mul_f32 v8, 0x3f317217, v2 :: v_dual_mul_f32 v9, 0x3f317217, v3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_dual_mul_f32 v10, 0x3f317217, v6 :: v_dual_mul_f32 v11, 0x3f317217, v7
-; GFX1100-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v8
-; GFX1100-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v9
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1100-NEXT: v_fma_f32 v14, 0x3f317217, v6, -v10
-; GFX1100-NEXT: v_fma_f32 v15, 0x3f317217, v7, -v11
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3
-; GFX1100-NEXT: v_dual_fmac_f32 v14, 0x3377d1cf, v6 :: v_dual_fmac_f32 v15, 0x3377d1cf, v7
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_add_f32 v8, v8, v12 :: v_dual_add_f32 v9, v9, v13
-; GFX1100-NEXT: v_dual_add_f32 v10, v10, v14 :: v_dual_add_f32 v11, v11, v15
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1100-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-NEXT: v_dual_cndmask_b32 v8, v3, v9 :: v_dual_mov_b32 v9, 0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
-; GFX1100-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
-; GFX1100-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; GFX1100-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b128 v9, v[0:3], s[0:1]
-; GFX1100-NEXT: s_endpgm
-;
-; R600-LABEL: s_log_v4f32:
-; R600: ; %bb.0:
-; R600-NEXT: ALU 76, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z,
-; R600-NEXT: SETGT * T1.W, literal.x, KC0[4].X,
-; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
-; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x,
-; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
-; R600-NEXT: MUL_IEEE T0.Z, KC0[3].Z, PV.W,
-; R600-NEXT: SETGT T2.W, literal.x, KC0[3].W,
-; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.y,
-; R600-NEXT: 8388608(1.175494e-38), 1333788672(4.294967e+09)
-; R600-NEXT: MUL_IEEE T1.Z, KC0[4].X, PS,
-; R600-NEXT: CNDE T3.W, PV.W, 1.0, literal.x,
-; R600-NEXT: LOG_IEEE * T0.X, PV.Z,
-; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
-; R600-NEXT: MUL_IEEE T0.Z, KC0[3].W, PV.W,
-; R600-NEXT: SETGT T3.W, literal.x, KC0[3].Y,
-; R600-NEXT: LOG_IEEE * T0.Y, PV.Z,
-; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
-; R600-NEXT: AND_INT T1.Y, PS, literal.x,
-; R600-NEXT: AND_INT T1.Z, T0.X, literal.x,
-; R600-NEXT: CNDE T4.W, PV.W, 1.0, literal.y,
-; R600-NEXT: LOG_IEEE * T0.Z, PV.Z,
-; R600-NEXT: -4096(nan), 1333788672(4.294967e+09)
-; R600-NEXT: MUL_IEEE T2.Y, KC0[3].Y, PV.W,
-; R600-NEXT: ADD T2.Z, T0.X, -PV.Z,
-; R600-NEXT: AND_INT T4.W, PS, literal.x,
-; R600-NEXT: ADD * T5.W, T0.Y, -PV.Y,
-; R600-NEXT: -4096(nan), 0(0.000000e+00)
-; R600-NEXT: MUL_IEEE T3.Y, PS, literal.x,
-; R600-NEXT: ADD T3.Z, T0.Z, -PV.W,
+; SI-SDAG-LABEL: s_log_v4f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: s_mov_b32 s6, 0x3f317217
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s11, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s11, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v3
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s6, -v4
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x3377d1cf
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s7, v5
+; SI-SDAG-NEXT: s_mov_b32 s11, 0x7f800000
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v6, s10, v6
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v6
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, s4
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s6, -v2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v7, s9, v7
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s7, v4
+; SI-SDAG-NEXT: v_log_f32_e32 v7, v7
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v5
+; SI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v7
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_fma_f32 v6, v7, s6, -v5
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; SI-SDAG-NEXT: v_fma_f32 v6, v7, s7, v6
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s8, v1
+; SI-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; SI-SDAG-NEXT: v_log_f32_e32 v6, v1
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v4
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317217, v6
+; SI-SDAG-NEXT: v_fma_f32 v5, v6, s6, -v4
+; SI-SDAG-NEXT: v_fma_f32 v5, v6, s7, v5
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log_v4f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s9, s9, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s1, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s7, s10, s7
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v2
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
+; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s10, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s7, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v7
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s9, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log_v4f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
+; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s6
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s3
+; VI-SDAG-NEXT: v_ldexp_f32 v6, s2, v6
+; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v6
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v2
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v8, v4
+; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v7, v4
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, s2
+; VI-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
+; VI-SDAG-NEXT: v_log_f32_e32 v7, v7
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v5
+; VI-SDAG-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v6, v7, v5
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3f317000, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x3805fdf4, v5
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v6, v9, v6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_add_f32_e32 v6, v8, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317000, v5
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-SDAG-NEXT: v_log_f32_e32 v6, v1
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v6
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v6, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3f317000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3805fdf4, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v8, v5
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3f317000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
+; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log_v4f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3805fdf4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3f317000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s6, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; VI-GISEL-NEXT: s_and_b32 s4, s9, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s4, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3805fdf4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v7, s4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v9, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317000, v7
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s2, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x3805fdf4, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317000, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log_v4f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x3f317217
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v3
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s8, -v5
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s3
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s9, v6
+; GFX900-SDAG-NEXT: s_mov_b32 s10, 0x7f800000
+; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s2, v7
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3f317217, v7
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s8, -v2
+; GFX900-SDAG-NEXT: v_ldexp_f32 v8, s1, v8
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s9, v5
+; GFX900-SDAG-NEXT: v_log_f32_e32 v8, v8
+; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, 0x3f317217, v8
+; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s8, -v6
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s9, v7
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v1
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3f317217, v7
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s8, -v5
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s9, v6
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v5, v0
+; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log_v4f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v7, 0x3f317217, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
+; GFX900-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v7, v1
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3f317217, v7
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x41b17218, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log_v4f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x41b17218, s6
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s7
+; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s6
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x41b17218, s8
+; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s9, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s7
+; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s3
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v6, v6
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x41b17218, s9
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v8, 0x3f317217, v2 :: v_dual_mul_f32 v9, 0x3f317217, v3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v10, 0x3f317217, v6 :: v_dual_mul_f32 v11, 0x3f317217, v7
+; GFX1100-SDAG-NEXT: v_fma_f32 v12, 0x3f317217, v2, -v8
+; GFX1100-SDAG-NEXT: v_fma_f32 v13, 0x3f317217, v3, -v9
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_fma_f32 v14, 0x3f317217, v6, -v10
+; GFX1100-SDAG-NEXT: v_fma_f32 v15, 0x3f317217, v7, -v11
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v12, 0x3377d1cf, v2 :: v_dual_fmac_f32 v13, 0x3377d1cf, v3
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v14, 0x3377d1cf, v6 :: v_dual_fmac_f32 v15, 0x3377d1cf, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v8, v8, v12 :: v_dual_add_f32 v9, v9, v13
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v10, v10, v14 :: v_dual_add_f32 v11, v11, v15
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v8, v3, v9 :: v_dual_mov_b32 v9, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log_v4f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s8
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, s9, s8
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s10, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s10, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s10, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s7, s6
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s10
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s8, s9
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s11, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x41b17218, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v3, s3, s4
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
+;
+; R600-LABEL: s_log_v4f32:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 76, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z,
+; R600-NEXT: SETGT * T1.W, literal.x, KC0[4].X,
+; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT: MUL_IEEE T0.Z, KC0[3].Z, PV.W,
+; R600-NEXT: SETGT T2.W, literal.x, KC0[3].W,
+; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.y,
+; R600-NEXT: 8388608(1.175494e-38), 1333788672(4.294967e+09)
+; R600-NEXT: MUL_IEEE T1.Z, KC0[4].X, PS,
+; R600-NEXT: CNDE T3.W, PV.W, 1.0, literal.x,
+; R600-NEXT: LOG_IEEE * T0.X, PV.Z,
+; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT: MUL_IEEE T0.Z, KC0[3].W, PV.W,
+; R600-NEXT: SETGT T3.W, literal.x, KC0[3].Y,
+; R600-NEXT: LOG_IEEE * T0.Y, PV.Z,
+; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT: AND_INT T1.Y, PS, literal.x,
+; R600-NEXT: AND_INT T1.Z, T0.X, literal.x,
+; R600-NEXT: CNDE T4.W, PV.W, 1.0, literal.y,
+; R600-NEXT: LOG_IEEE * T0.Z, PV.Z,
+; R600-NEXT: -4096(nan), 1333788672(4.294967e+09)
+; R600-NEXT: MUL_IEEE T2.Y, KC0[3].Y, PV.W,
+; R600-NEXT: ADD T2.Z, T0.X, -PV.Z,
+; R600-NEXT: AND_INT T4.W, PS, literal.x,
+; R600-NEXT: ADD * T5.W, T0.Y, -PV.Y,
+; R600-NEXT: -4096(nan), 0(0.000000e+00)
+; R600-NEXT: MUL_IEEE T3.Y, PS, literal.x,
+; R600-NEXT: ADD T3.Z, T0.Z, -PV.W,
; R600-NEXT: MUL_IEEE T6.W, PV.Z, literal.x,
; R600-NEXT: LOG_IEEE * T1.X, PV.Y,
; R600-NEXT: 939916788(3.194618e-05), 0(0.000000e+00)
@@ -1539,27 +2803,50 @@ define amdgpu_kernel void @s_log_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
}
define float @v_log_f32(float %in) {
-; SI-LABEL: v_log_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32:
; VI: ; %bb.0:
@@ -1586,49 +2873,95 @@ define float @v_log_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32:
; R600: ; %bb.0:
@@ -1644,29 +2977,52 @@ define float @v_log_f32(float %in) {
}
define float @v_log_fabs_f32(float %in) {
-; SI-LABEL: v_log_fabs_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_fabs_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log_fabs_f32:
+; SI-GISEL-LABEL: v_log_fabs_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_log_fabs_f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x800000
@@ -1691,49 +3047,96 @@ define float @v_log_fabs_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_fabs_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, |v0|, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_fabs_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_fabs_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
-; GFX1100-NEXT: v_ldexp_f32 v0, |v0|, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_fabs_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_fabs_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_fabs_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fabs_f32:
; R600: ; %bb.0:
@@ -1750,27 +3153,50 @@ define float @v_log_fabs_f32(float %in) {
}
define float @v_log_fneg_fabs_f32(float %in) {
-; SI-LABEL: v_log_fneg_fabs_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x80800000
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_fneg_fabs_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_fneg_fabs_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_fneg_fabs_f32:
; VI: ; %bb.0:
@@ -1797,49 +3223,96 @@ define float @v_log_fneg_fabs_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_fneg_fabs_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x80800000
-; GFX900-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, -|v0|, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_fneg_fabs_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_fneg_fabs_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_lt_f32_e64 s0, 0x80800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
-; GFX1100-NEXT: v_ldexp_f32 v0, -|v0|, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_fneg_fabs_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_fneg_fabs_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_lt_f32_e64 s0, 0x80800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_fneg_fabs_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -|v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fneg_fabs_f32:
; R600: ; %bb.0:
@@ -1857,27 +3330,50 @@ define float @v_log_fneg_fabs_f32(float %in) {
}
define float @v_log_fneg_f32(float %in) {
-; SI-LABEL: v_log_fneg_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x80800000
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, -v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_fneg_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, -v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_fneg_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_fneg_f32:
; VI: ; %bb.0:
@@ -1904,49 +3400,96 @@ define float @v_log_fneg_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_fneg_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x80800000
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, -v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_fneg_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_fneg_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x80800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, -v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_fneg_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_fneg_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x80800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_fneg_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_fneg_f32:
; R600: ; %bb.0:
@@ -2078,27 +3621,50 @@ define float @v_log_f32_fast(float %in) {
}
define float @v_log_f32_ninf(float %in) {
-; SI-LABEL: v_log_f32_ninf:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32_ninf:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_ninf:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32_ninf:
; VI: ; %bb.0:
@@ -2125,49 +3691,95 @@ define float @v_log_f32_ninf(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32_ninf:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32_ninf:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32_ninf:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32_ninf:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_ninf:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_ninf:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_ninf:
; R600: ; %bb.0:
@@ -2623,156 +4235,225 @@ define float @v_log_f32_daz(float %in) #0 {
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-GISEL-LABEL: v_log_f32_daz:
+; GFX900-GISEL-LABEL: v_log_f32_daz:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_daz:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_daz:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: v_log_f32_daz:
+; R600: ; %bb.0:
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; CM-LABEL: v_log_f32_daz:
+; CM: ; %bb.0:
+; CM-NEXT: CF_END
+; CM-NEXT: PAD
+ %result = call float @llvm.log.f32(float %in)
+ ret float %result
+}
+
+define float @v_log_f32_nnan(float %in) {
+; SI-SDAG-LABEL: v_log_f32_nnan:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_nnan:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_log_f32_nnan:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, 0x800000
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-NEXT: v_log_f32_e32 v0, v0
+; VI-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
+; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
+; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
+; VI-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
+; VI-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log_f32_nnan:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log_f32_nnan:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3377d1cf
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3f317217, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
-; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-SDAG-LABEL: v_log_f32_daz:
+; GFX1100-SDAG-LABEL: v_log_f32_nnan:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-GISEL-LABEL: v_log_f32_daz:
+; GFX1100-GISEL-LABEL: v_log_f32_nnan:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; R600-LABEL: v_log_f32_daz:
-; R600: ; %bb.0:
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-;
-; CM-LABEL: v_log_f32_daz:
-; CM: ; %bb.0:
-; CM-NEXT: CF_END
-; CM-NEXT: PAD
- %result = call float @llvm.log.f32(float %in)
- ret float %result
-}
-
-define float @v_log_f32_nnan(float %in) {
-; SI-LABEL: v_log_f32_nnan:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_log_f32_nnan:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3f317000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x3805fdf4, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3805fdf4, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3f317000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-LABEL: v_log_f32_nnan:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: v_log_f32_nnan:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
; R600-LABEL: v_log_f32_nnan:
; R600: ; %bb.0:
; R600-NEXT: CF_END
@@ -2909,27 +4590,50 @@ define float @v_log_f32_nnan_daz(float %in) #0 {
}
define float @v_log_f32_nnan_dynamic(float %in) #1 {
-; SI-LABEL: v_log_f32_nnan_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32_nnan_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_nnan_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32_nnan_dynamic:
; VI: ; %bb.0:
@@ -2956,49 +4660,95 @@ define float @v_log_f32_nnan_dynamic(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32_nnan_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32_nnan_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32_nnan_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32_nnan_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_nnan_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_nnan_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_nnan_dynamic:
; R600: ; %bb.0:
@@ -3136,27 +4886,50 @@ define float @v_log_f32_ninf_daz(float %in) #0 {
}
define float @v_log_f32_ninf_dynamic(float %in) #1 {
-; SI-LABEL: v_log_f32_ninf_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32_ninf_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_ninf_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32_ninf_dynamic:
; VI: ; %bb.0:
@@ -3183,49 +4956,95 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32_ninf_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32_ninf_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32_ninf_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32_ninf_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_ninf_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_ninf_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_ninf_dynamic:
; R600: ; %bb.0:
@@ -3241,24 +5060,44 @@ define float @v_log_f32_ninf_dynamic(float %in) #1 {
}
define float @v_log_f32_nnan_ninf(float %in) {
-; SI-LABEL: v_log_f32_nnan_ninf:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v0, v0, s4, v2
-; SI-NEXT: v_add_f32_e32 v0, v1, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32_nnan_ninf:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_nnan_ninf:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32_nnan_ninf:
; VI: ; %bb.0:
@@ -3282,43 +5121,84 @@ define float @v_log_f32_nnan_ninf(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32_nnan_ninf:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v0, v0, s4, v2
-; GFX900-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32_nnan_ninf:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32_nnan_ninf:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v0, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32_nnan_ninf:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_nnan_ninf:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_nnan_ninf:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_nnan_ninf:
; R600: ; %bb.0:
@@ -3437,24 +5317,44 @@ define float @v_log_f32_nnan_ninf_daz(float %in) #0 {
}
define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 {
-; SI-LABEL: v_log_f32_nnan_ninf_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v0, v0, s4, v2
-; SI-NEXT: v_add_f32_e32 v0, v1, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32_nnan_ninf_dynamic:
; VI: ; %bb.0:
@@ -3478,43 +5378,84 @@ define float @v_log_f32_nnan_ninf_dynamic(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32_nnan_ninf_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v0, v0, s4, v2
-; GFX900-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32_nnan_ninf_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v0, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_nnan_ninf_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_nnan_ninf_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_nnan_ninf_dynamic:
; R600: ; %bb.0:
@@ -3559,27 +5500,50 @@ define float @v_log_f32_fast_daz(float %in) #0 {
}
define float @v_log_f32_dynamic_mode(float %in) #1 {
-; SI-LABEL: v_log_f32_dynamic_mode:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3f317217
-; SI-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3377d1cf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log_f32_dynamic_mode:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log_f32_dynamic_mode:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log_f32_dynamic_mode:
; VI: ; %bb.0:
@@ -3606,49 +5570,95 @@ define float @v_log_f32_dynamic_mode(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log_f32_dynamic_mode:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3f317217
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3377d1cf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x41b17218
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log_f32_dynamic_mode:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3f317217
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3377d1cf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log_f32_dynamic_mode:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log_f32_dynamic_mode:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3f317217
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3377d1cf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3f317217, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x41b17218
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log_f32_dynamic_mode:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3377d1cf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log_f32_dynamic_mode:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3f317217, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3f317217, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3377d1cf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x41b17218, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log_f32_dynamic_mode:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
index fc27dd6f7619b..b2eaf80900463 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log10.ll
@@ -14,122 +14,266 @@
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log10_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s2
-; SI-NEXT: v_ldexp_f32_e32 v1, s6, v1
-; SI-NEXT: v_log_f32_e32 v1, v1
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
-; SI-NEXT: v_fma_f32 v3, v1, s4, -v2
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v3, v1, s4, v3
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log10_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-NEXT: s_cselect_b32 s0, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s0
-; VI-NEXT: v_ldexp_f32 v1, s2, v1
-; VI-NEXT: v_log_f32_e32 v1, v1
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_mov_b32 s2, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e32 v3, v1, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v3
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-NEXT: v_add_f32_e32 v3, v5, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v1, v0
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log10_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX900-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-NEXT: v_ldexp_f32 v1, s6, v1
-; GFX900-NEXT: v_log_f32_e32 v1, v1
-; GFX900-NEXT: s_mov_b32 s2, 0x3e9a209a
-; GFX900-NEXT: s_mov_b32 s3, 0x3284fbcf
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v1
-; GFX900-NEXT: v_fma_f32 v4, v1, s2, -v3
-; GFX900-NEXT: v_fma_f32 v4, v1, s3, v4
-; GFX900-NEXT: s_mov_b32 s2, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX900-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log10_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s1
-; GFX1100-NEXT: s_and_b32 s1, s1, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s1, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v1, s0, s1
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-NEXT: v_fma_f32 v3, 0x3e9a209a, v1, -v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v3, v1, 0x3284fbcf, v3
-; GFX1100-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log10_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s6, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, -v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, v3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log10_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log10_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v5, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v1, v0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log10_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a2000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log10_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3e9a209a
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v1
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s2, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s3, v4
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log10_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log10_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s1
+; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3e9a209a, v1, -v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3284fbcf, v3
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log10_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_f32:
; R600: ; %bb.0:
@@ -203,122 +347,266 @@ define amdgpu_kernel void @s_log10_f32(ptr addrspace(1) %out, float %in) {
}
define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log10_contract_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s2
-; SI-NEXT: v_ldexp_f32_e32 v1, s6, v1
-; SI-NEXT: v_log_f32_e32 v1, v1
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
-; SI-NEXT: v_fma_f32 v3, v1, s4, -v2
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v3, v1, s4, v3
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log10_contract_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[0:1], vcc, exec
-; VI-NEXT: s_cselect_b32 s0, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s0
-; VI-NEXT: v_ldexp_f32 v1, s2, v1
-; VI-NEXT: v_log_f32_e32 v1, v1
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: s_mov_b32 s2, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
-; VI-NEXT: v_sub_f32_e32 v3, v1, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v3
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-NEXT: v_add_f32_e32 v3, v5, v3
-; VI-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v1, v0
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log10_contract_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX900-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-NEXT: v_ldexp_f32 v1, s6, v1
-; GFX900-NEXT: v_log_f32_e32 v1, v1
-; GFX900-NEXT: s_mov_b32 s2, 0x3e9a209a
-; GFX900-NEXT: s_mov_b32 s3, 0x3284fbcf
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v1
-; GFX900-NEXT: v_fma_f32 v4, v1, s2, -v3
-; GFX900-NEXT: v_fma_f32 v4, v1, s3, v4
-; GFX900-NEXT: s_mov_b32 s2, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX900-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log10_contract_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b32 s0, s[4:5], 0x2c
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s1
-; GFX1100-NEXT: s_and_b32 s1, s1, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s1, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v1, s0, s1
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-NEXT: v_fma_f32 v3, 0x3e9a209a, v1, -v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v3, v1, 0x3284fbcf, v3
-; GFX1100-NEXT: v_add_f32_e32 v2, v2, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log10_contract_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s6, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, -v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v3, v1, s4, v3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log10_contract_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; SI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log10_contract_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s0
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v5, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v1, v0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log10_contract_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a2000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log10_contract_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x3e9a209a
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v1
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s2, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v1, s3, v4
+; GFX900-SDAG-NEXT: s_mov_b32 s2, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v1|, s2
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log10_contract_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v0|, v3
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log10_contract_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s1
+; GFX1100-SDAG-NEXT: s_and_b32 s1, s1, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s0, s1
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: v_fma_f32 v3, 0x3e9a209a, v1, -v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v3, v1, 0x3284fbcf, v3
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log10_contract_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s3, s2
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_contract_f32:
; R600: ; %bb.0:
@@ -394,176 +682,404 @@ define amdgpu_kernel void @s_log10_contract_f32(ptr addrspace(1) %out, float %in
; FIXME: We should be able to merge these packets together on Cayman so we
; have a maximum of 4 instructions.
define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
-; SI-LABEL: s_log10_v2f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: s_mov_b32 s8, 0x3e9a209a
-; SI-NEXT: s_mov_b32 s9, 0x7f800000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_mov_b32_e32 v3, s2
-; SI-NEXT: v_ldexp_f32_e32 v3, s5, v3
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v3
-; SI-NEXT: s_cselect_b32 s6, 32, 0
-; SI-NEXT: s_mov_b32 s5, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v5, v3, s8, -v4
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s6
-; SI-NEXT: v_fma_f32 v5, v3, s5, v5
-; SI-NEXT: v_ldexp_f32_e32 v1, s4, v1
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_log_f32_e32 v5, v1
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
-; SI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; SI-NEXT: v_sub_f32_e32 v1, v1, v2
-; SI-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v5
-; SI-NEXT: v_fma_f32 v3, v5, s8, -v2
-; SI-NEXT: v_fma_f32 v3, v5, s5, v3
-; SI-NEXT: v_add_f32_e32 v2, v2, v3
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s9
-; SI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v0, v2, v0
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log10_v2f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: s_cselect_b32 s4, 32, 0
-; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: v_ldexp_f32 v3, s3, v3
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
-; VI-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
-; VI-NEXT: s_cselect_b32 s4, 32, 0
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s4
-; VI-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_ldexp_f32 v1, s2, v1
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_log_f32_e32 v5, v1
-; VI-NEXT: s_mov_b32 s3, 0x7f800000
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
-; VI-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v1, v1, v2
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v5
-; VI-NEXT: v_sub_f32_e32 v3, v5, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v3
-; VI-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v3
-; VI-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v2
-; VI-NEXT: v_add_f32_e32 v3, v6, v3
-; VI-NEXT: v_add_f32_e32 v3, v4, v3
-; VI-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-NEXT: v_add_f32_e32 v2, v2, v3
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
-; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v2, v0
-; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v2, s0
-; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log10_v2f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: s_mov_b32 s6, 0x3284fbcf
-; GFX900-NEXT: s_mov_b32 s7, 0x7f800000
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_mov_b32_e32 v4, s4
-; GFX900-NEXT: v_ldexp_f32 v4, s3, v4
-; GFX900-NEXT: v_log_f32_e32 v4, v4
-; GFX900-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_mov_b32 s3, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v4
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_fma_f32 v6, v4, s3, -v5
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s4
-; GFX900-NEXT: v_fma_f32 v6, v4, s6, v6
-; GFX900-NEXT: v_ldexp_f32 v1, s2, v1
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_log_f32_e32 v6, v1
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s7
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
-; GFX900-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v6
-; GFX900-NEXT: v_fma_f32 v4, v6, s3, -v3
-; GFX900-NEXT: v_fma_f32 v4, v6, s6, v4
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v4
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-NEXT: v_sub_f32_e32 v0, v3, v0
-; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log10_v2f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s4
-; GFX1100-NEXT: s_and_b32 s4, s4, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s5
-; GFX1100-NEXT: v_ldexp_f32 v1, s3, s4
-; GFX1100-NEXT: s_and_b32 s5, s5, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s5, 32, 0
-; GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_ldexp_f32 v3, s2, s5
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1100-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
-; GFX1100-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
-; GFX1100-NEXT: v_fma_f32 v6, 0x3e9a209a, v1, -v4
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v7, 0x3e9a209a, v3, -v5
-; GFX1100-NEXT: v_dual_fmac_f32 v6, 0x3284fbcf, v1 :: v_dual_fmac_f32 v7, 0x3284fbcf, v3
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
-; GFX1100-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_mov_b32 v4, 0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX1100-NEXT: v_dual_sub_f32 v1, v1, v0 :: v_dual_sub_f32 v0, v3, v2
-; GFX1100-NEXT: global_store_b64 v4, v[0:1], s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log10_v2f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: s_mov_b32 s8, 0x3e9a209a
+; SI-SDAG-NEXT: s_mov_b32 s9, 0x7f800000
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b64 s[4:5], s[2:3]
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s5, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v3
+; SI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s8, -v4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s6
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s5, v5
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s4, v1
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_log_f32_e32 v5, v1
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v5
+; SI-SDAG-NEXT: v_fma_f32 v3, v5, s8, -v2
+; SI-SDAG-NEXT: v_fma_f32 v3, v5, s5, v3
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log10_v2f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log10_v2f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
+; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_log_f32_e32 v5, v1
+; VI-SDAG-NEXT: s_mov_b32 s3, 0x7f800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v2
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v5
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v5, v2
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v6, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log10_v2f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a2000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s7, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log10_v2f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0x3284fbcf
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0x7f800000
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; GFX900-SDAG-NEXT: v_ldexp_f32 v4, s3, v4
+; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_mov_b32 s3, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v4
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s3, -v5
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v4, s6, v6
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v1
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s7
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v6
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s3, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v4, v6, s6, v4
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s7
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
+; GFX900-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log10_v2f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s7, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v1, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log10_v2f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s4
+; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x411a209b, s5
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
+; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
+; GFX1100-SDAG-NEXT: v_fma_f32 v6, 0x3e9a209a, v1, -v4
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v7, 0x3e9a209a, v3, -v5
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v6, 0x3284fbcf, v1 :: v_dual_fmac_f32 v7, 0x3284fbcf, v3
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v1, v1, v4 :: v_dual_mov_b32 v4, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v1, v0 :: v_dual_sub_f32 v0, v3, v2
+; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log10_v2f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s5
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, s6, s5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s6
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s5, s4
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_mov_b32 v2, 0
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s3, s2
+; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_v2f32:
; R600: ; %bb.0:
@@ -676,242 +1192,571 @@ define amdgpu_kernel void @s_log10_v2f32(ptr addrspace(1) %out, <2 x float> %in)
}
define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
-; SI-LABEL: s_log10_v3f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v2, 0x411a209b
-; SI-NEXT: s_mov_b32 s6, 0x3e9a209a
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_mov_b32_e32 v3, s2
-; SI-NEXT: v_ldexp_f32_e32 v3, s9, v3
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v3
-; SI-NEXT: v_mov_b32_e32 v6, s4
-; SI-NEXT: v_fma_f32 v5, v3, s6, -v4
-; SI-NEXT: s_mov_b32 s7, 0x3284fbcf
-; SI-NEXT: v_ldexp_f32_e32 v6, s8, v6
-; SI-NEXT: v_fma_f32 v5, v3, s7, v5
-; SI-NEXT: s_mov_b32 s9, 0x7f800000
-; SI-NEXT: v_log_f32_e32 v6, v6
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, 0, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_sub_f32_e32 v1, v3, v1
-; SI-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v6
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_fma_f32 v4, v6, s6, -v3
-; SI-NEXT: v_mov_b32_e32 v0, s4
-; SI-NEXT: v_fma_f32 v4, v6, s7, v4
-; SI-NEXT: v_ldexp_f32_e32 v0, s10, v0
-; SI-NEXT: v_add_f32_e32 v3, v3, v4
-; SI-NEXT: v_log_f32_e32 v4, v0
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s9
-; SI-NEXT: v_cndmask_b32_e32 v0, v6, v3, vcc
-; SI-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v4
-; SI-NEXT: v_sub_f32_e32 v0, v0, v5
-; SI-NEXT: v_fma_f32 v5, v4, s6, -v3
-; SI-NEXT: v_fma_f32 v5, v4, s7, v5
-; SI-NEXT: v_add_f32_e32 v3, v3, v5
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s9
-; SI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v2, v3, v2
-; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log10_v3f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: s_cselect_b32 s3, 32, 0
-; VI-NEXT: v_mov_b32_e32 v3, s3
-; VI-NEXT: v_ldexp_f32 v3, s2, v3
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
-; VI-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
-; VI-NEXT: s_cselect_b32 s4, 32, 0
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s4
-; VI-NEXT: v_ldexp_f32 v6, s1, v6
-; VI-NEXT: v_log_f32_e32 v6, v6
-; VI-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: s_mov_b32 s6, 0x7f800000
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s6
-; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v3, v2
-; VI-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-NEXT: v_sub_f32_e32 v4, v6, v3
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v4
-; VI-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v3
-; VI-NEXT: s_cselect_b32 s1, 32, 0
-; VI-NEXT: v_add_f32_e32 v4, v8, v4
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_f32_e32 v4, v7, v4
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-NEXT: v_ldexp_f32 v1, s0, v1
-; VI-NEXT: v_add_f32_e32 v3, v3, v4
-; VI-NEXT: v_log_f32_e32 v4, v1
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s6
-; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
-; VI-NEXT: v_sub_f32_e32 v1, v1, v5
-; VI-NEXT: v_and_b32_e32 v3, 0xfffff000, v4
-; VI-NEXT: v_sub_f32_e32 v5, v4, v3
-; VI-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
-; VI-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v3
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
-; VI-NEXT: v_add_f32_e32 v3, v3, v5
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s6
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v3, v0
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v4, s3
-; VI-NEXT: v_mov_b32_e32 v3, s2
-; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log10_v3f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: s_mov_b32 s8, 0x7f800000
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-NEXT: v_mov_b32_e32 v3, s3
-; GFX900-NEXT: v_ldexp_f32 v3, s2, v3
-; GFX900-NEXT: v_log_f32_e32 v3, v3
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
-; GFX900-NEXT: v_mov_b32_e32 v7, s2
-; GFX900-NEXT: s_mov_b32 s5, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v6, v3, s4, -v5
-; GFX900-NEXT: v_ldexp_f32 v7, s1, v7
-; GFX900-NEXT: v_fma_f32 v6, v3, s5, v6
-; GFX900-NEXT: v_log_f32_e32 v7, v7
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v7
-; GFX900-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-NEXT: v_fma_f32 v5, v7, s4, -v3
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-NEXT: v_fma_f32 v5, v7, s5, v5
-; GFX900-NEXT: v_ldexp_f32 v1, s0, v1
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX900-NEXT: v_log_f32_e32 v5, v1
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
-; GFX900-NEXT: v_sub_f32_e32 v1, v1, v6
-; GFX900-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v5
-; GFX900-NEXT: v_fma_f32 v6, v5, s4, -v3
-; GFX900-NEXT: v_fma_f32 v6, v5, s5, v6
-; GFX900-NEXT: v_add_f32_e32 v3, v3, v6
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s8
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-NEXT: v_sub_f32_e32 v0, v3, v0
-; GFX900-NEXT: global_store_dwordx3 v4, v[0:2], s[6:7]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log10_v3f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s3
-; GFX1100-NEXT: s_and_b32 s3, s3, exec_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s6
-; GFX1100-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v2, s2, s3
-; GFX1100-NEXT: v_ldexp_f32 v4, s1, s6
-; GFX1100-NEXT: v_cndmask_b32_e64 v3, 0, 0x411a209b, s7
-; GFX1100-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-NEXT: v_log_f32_e32 v4, v4
-; GFX1100-NEXT: v_ldexp_f32 v5, s0, s2
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v5, v5
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_dual_mul_f32 v6, 0x3e9a209a, v2 :: v_dual_mul_f32 v7, 0x3e9a209a, v4
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-NEXT: v_fma_f32 v9, 0x3e9a209a, v2, -v6
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v10, 0x3e9a209a, v4, -v7
-; GFX1100-NEXT: v_dual_fmac_f32 v9, 0x3284fbcf, v2 :: v_dual_fmac_f32 v10, 0x3284fbcf, v4
-; GFX1100-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v5
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v7, v7, v10
-; GFX1100-NEXT: v_fma_f32 v11, 0x3e9a209a, v5, -v8
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
-; GFX1100-NEXT: v_dual_fmac_f32 v11, 0x3284fbcf, v5 :: v_dual_sub_f32 v2, v2, v0
-; GFX1100-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1100-NEXT: v_add_f32_e32 v8, v8, v11
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v5|
-; GFX1100-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_sub_f32 v1, v4, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v5, v3
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b96 v6, v[0:2], s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log10_v3f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x411a209b
+; SI-SDAG-NEXT: s_mov_b32 s6, 0x3e9a209a
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s9, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v3
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s6, -v4
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x3284fbcf
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v6, s8, v6
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s7, v5
+; SI-SDAG-NEXT: s_mov_b32 s9, 0x7f800000
+; SI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v3, v1
+; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v6
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s6, -v3
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s4
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s7, v4
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, s10, v0
+; SI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; SI-SDAG-NEXT: v_log_f32_e32 v4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v3, vcc
+; SI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v4
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v5
+; SI-SDAG-NEXT: v_fma_f32 v5, v4, s6, -v3
+; SI-SDAG-NEXT: v_fma_f32 v5, v4, s7, v5
+; SI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s9
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; SI-SDAG-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log10_v3f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; SI-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; SI-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s8, s8, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s1, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; SI-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
+; SI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v6
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s3, s7, s3
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s8, v5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v6
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; SI-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v6
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: buffer_store_dword v2, off, s[0:3], 0 offset:8
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log10_v3f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
+; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; VI-SDAG-NEXT: v_ldexp_f32 v6, s1, v6
+; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: s_mov_b32 s6, 0x7f800000
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v6
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v3
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v3
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v8, v4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v7, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v4
+; VI-SDAG-NEXT: v_log_f32_e32 v4, v1
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
+; VI-SDAG-NEXT: v_and_b32_e32 v3, 0xfffff000, v4
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v4, v3
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v3
+; VI-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v4|, s6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s3
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log10_v3f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a2000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v4, s6, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v4
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v4, v6, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; VI-GISEL-NEXT: s_and_b32 s4, s3, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s4, v1
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; VI-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v6, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v5, s2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v5
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s0
+; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log10_v3f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
+; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s2
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s4, -v5
+; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s5, v6
+; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v7
+; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s4, -v3
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s5, v5
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX900-SDAG-NEXT: v_log_f32_e32 v5, v1
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v3, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v6
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, 0x3e9a209a, v5
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s4, -v3
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v5, s5, v6
+; GFX900-SDAG-NEXT: v_add_f32_e32 v3, v3, v6
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v5|, s8
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v3, v0
+; GFX900-SDAG-NEXT: global_store_dwordx3 v4, v[0:2], s[6:7]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log10_v3f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x7f800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v1, v2, -v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v1|, v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v1, v3, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v5, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s8, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, s3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v1
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v2, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v7, v1, v3, v7
+; GFX900-GISEL-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v1|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s3, v1
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s8, v6
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, s8, s3
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v6, v0
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v6
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v2, -v5
+; GFX900-GISEL-NEXT: v_fma_f32 v2, v6, v3, v2
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v5, v2
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v6|, v4
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log10_v3f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s3
+; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s6
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x411a209b, s7
+; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v6, 0x3e9a209a, v2 :: v_dual_mul_f32 v7, 0x3e9a209a, v4
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
+; GFX1100-SDAG-NEXT: v_fma_f32 v9, 0x3e9a209a, v2, -v6
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v10, 0x3e9a209a, v4, -v7
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v9, 0x3284fbcf, v2 :: v_dual_fmac_f32 v10, 0x3284fbcf, v4
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v8, 0x3e9a209a, v5
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v6, v6, v9 :: v_dual_add_f32 v7, v7, v10
+; GFX1100-SDAG-NEXT: v_fma_f32 v11, 0x3e9a209a, v5, -v8
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc_lo
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v11, 0x3284fbcf, v5 :: v_dual_sub_f32 v2, v2, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v8, v8, v11
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v5|
+; GFX1100-SDAG-NEXT: v_dual_mov_b32 v6, 0 :: v_dual_sub_f32 v1, v4, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v5, v3
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b96 v6, v[0:2], s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log10_v3f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s6
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, s7, s6
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s2, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s6, s3
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s7, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s9, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s3
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log10_v3f32:
; R600: ; %bb.0:
@@ -1065,333 +1910,752 @@ define amdgpu_kernel void @s_log10_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; FIXME: We should be able to merge these packets together on Cayman so we
; have a maximum of 4 instructions.
define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
-; SI-LABEL: s_log10_v4f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: s_mov_b32 s6, 0x3e9a209a
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s11, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_mov_b32_e32 v3, s2
-; SI-NEXT: v_ldexp_f32_e32 v3, s11, v3
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v3
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_fma_f32 v5, v3, s6, -v4
-; SI-NEXT: s_mov_b32 s7, 0x3284fbcf
-; SI-NEXT: v_mov_b32_e32 v6, s4
-; SI-NEXT: v_fma_f32 v5, v3, s7, v5
-; SI-NEXT: s_mov_b32 s11, 0x7f800000
-; SI-NEXT: v_ldexp_f32_e32 v6, s10, v6
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; SI-NEXT: v_log_f32_e32 v6, v6
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s11
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_sub_f32_e32 v3, v3, v2
-; SI-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v6
-; SI-NEXT: v_mov_b32_e32 v7, s4
-; SI-NEXT: v_fma_f32 v4, v6, s6, -v2
-; SI-NEXT: v_ldexp_f32_e32 v7, s9, v7
-; SI-NEXT: v_fma_f32 v4, v6, s7, v4
-; SI-NEXT: v_log_f32_e32 v7, v7
-; SI-NEXT: v_add_f32_e32 v2, v2, v4
-; SI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
-; SI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_sub_f32_e32 v2, v2, v5
-; SI-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v7
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_fma_f32 v6, v7, s6, -v5
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s4
-; SI-NEXT: v_fma_f32 v6, v7, s7, v6
-; SI-NEXT: v_ldexp_f32_e32 v1, s8, v1
-; SI-NEXT: v_add_f32_e32 v5, v5, v6
-; SI-NEXT: v_log_f32_e32 v6, v1
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s11
-; SI-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
-; SI-NEXT: v_sub_f32_e32 v1, v1, v4
-; SI-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v6
-; SI-NEXT: v_fma_f32 v5, v6, s6, -v4
-; SI-NEXT: v_fma_f32 v5, v6, s7, v5
-; SI-NEXT: v_add_f32_e32 v4, v4, v5
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
-; SI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v0, v4, v0
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log10_v4f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: s_mov_b32 s8, 0x7f800000
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: s_cselect_b32 s6, 32, 0
-; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_ldexp_f32 v3, s3, v3
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
-; VI-NEXT: v_sub_f32_e32 v5, v3, v4
-; VI-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
-; VI-NEXT: s_cselect_b32 s3, 32, 0
-; VI-NEXT: v_add_f32_e32 v5, v6, v5
-; VI-NEXT: v_mov_b32_e32 v6, s3
-; VI-NEXT: v_ldexp_f32 v6, s2, v6
-; VI-NEXT: v_log_f32_e32 v6, v6
-; VI-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
-; VI-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v3, v3, v2
-; VI-NEXT: v_and_b32_e32 v2, 0xfffff000, v6
-; VI-NEXT: v_sub_f32_e32 v4, v6, v2
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v4
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v4
-; VI-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_add_f32_e32 v4, v8, v4
-; VI-NEXT: s_cselect_b32 s2, 32, 0
-; VI-NEXT: v_add_f32_e32 v4, v7, v4
-; VI-NEXT: v_mov_b32_e32 v7, s2
-; VI-NEXT: v_ldexp_f32 v7, s1, v7
-; VI-NEXT: v_log_f32_e32 v7, v7
-; VI-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
-; VI-NEXT: v_add_f32_e32 v2, v2, v4
-; VI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
-; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
-; VI-NEXT: v_sub_f32_e32 v2, v2, v5
-; VI-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-NEXT: v_sub_f32_e32 v6, v7, v5
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_mul_f32_e32 v8, 0x3e9a2000, v6
-; VI-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v6
-; VI-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5
-; VI-NEXT: s_cselect_b32 s1, 32, 0
-; VI-NEXT: v_add_f32_e32 v6, v9, v6
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_add_f32_e32 v6, v8, v6
-; VI-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
-; VI-NEXT: v_ldexp_f32 v1, s0, v1
-; VI-NEXT: v_add_f32_e32 v5, v5, v6
-; VI-NEXT: v_log_f32_e32 v6, v1
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
-; VI-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
-; VI-NEXT: v_sub_f32_e32 v1, v1, v4
-; VI-NEXT: v_and_b32_e32 v4, 0xfffff000, v6
-; VI-NEXT: v_sub_f32_e32 v5, v6, v4
-; VI-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
-; VI-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
-; VI-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v4
-; VI-NEXT: v_add_f32_e32 v5, v8, v5
-; VI-NEXT: v_add_f32_e32 v5, v7, v5
-; VI-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
-; VI-NEXT: v_add_f32_e32 v4, v4, v5
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
-; VI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v4, v0
-; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: v_mov_b32_e32 v5, s5
-; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log10_v4f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: s_mov_b32 s8, 0x3e9a209a
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_mov_b32_e32 v3, s4
-; GFX900-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX900-NEXT: v_log_f32_e32 v3, v3
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
-; GFX900-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-NEXT: s_mov_b32 s9, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v6, v3, s8, -v5
-; GFX900-NEXT: v_mov_b32_e32 v7, s3
-; GFX900-NEXT: v_fma_f32 v6, v3, s9, v6
-; GFX900-NEXT: s_mov_b32 s10, 0x7f800000
-; GFX900-NEXT: v_ldexp_f32 v7, s2, v7
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; GFX900-NEXT: v_log_f32_e32 v7, v7
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX900-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v7
-; GFX900-NEXT: v_mov_b32_e32 v8, s2
-; GFX900-NEXT: v_fma_f32 v5, v7, s8, -v2
-; GFX900-NEXT: v_ldexp_f32 v8, s1, v8
-; GFX900-NEXT: v_fma_f32 v5, v7, s9, v5
-; GFX900-NEXT: v_log_f32_e32 v8, v8
-; GFX900-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX900-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_sub_f32_e32 v2, v2, v6
-; GFX900-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v8
-; GFX900-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-NEXT: v_fma_f32 v7, v8, s8, -v6
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-NEXT: v_fma_f32 v7, v8, s9, v7
-; GFX900-NEXT: v_ldexp_f32 v1, s0, v1
-; GFX900-NEXT: v_add_f32_e32 v6, v6, v7
-; GFX900-NEXT: v_log_f32_e32 v7, v1
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
-; GFX900-NEXT: v_sub_f32_e32 v1, v1, v5
-; GFX900-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v7
-; GFX900-NEXT: v_fma_f32 v6, v7, s8, -v5
-; GFX900-NEXT: v_fma_f32 v6, v7, s9, v6
-; GFX900-NEXT: v_add_f32_e32 v5, v5, v6
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
-; GFX900-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-NEXT: v_sub_f32_e32 v0, v5, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log10_v4f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s6
-; GFX1100-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s7
-; GFX1100-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-NEXT: v_ldexp_f32 v2, s3, s6
-; GFX1100-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s8
-; GFX1100-NEXT: s_cselect_b32 s7, 32, 0
-; GFX1100-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-NEXT: s_and_b32 s6, s9, exec_lo
-; GFX1100-NEXT: v_ldexp_f32 v3, s2, s7
-; GFX1100-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v6, s1, s3
-; GFX1100-NEXT: v_ldexp_f32 v7, s0, s2
-; GFX1100-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: v_log_f32_e32 v6, v6
-; GFX1100-NEXT: v_log_f32_e32 v7, v7
-; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s9
-; GFX1100-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-NEXT: v_dual_mul_f32 v8, 0x3e9a209a, v2 :: v_dual_mul_f32 v9, 0x3e9a209a, v3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_dual_mul_f32 v10, 0x3e9a209a, v6 :: v_dual_mul_f32 v11, 0x3e9a209a, v7
-; GFX1100-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v8
-; GFX1100-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v9
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1100-NEXT: v_fma_f32 v14, 0x3e9a209a, v6, -v10
-; GFX1100-NEXT: v_fma_f32 v15, 0x3e9a209a, v7, -v11
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3
-; GFX1100-NEXT: v_dual_fmac_f32 v14, 0x3284fbcf, v6 :: v_dual_fmac_f32 v15, 0x3284fbcf, v7
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_add_f32 v8, v8, v12 :: v_dual_add_f32 v9, v9, v13
-; GFX1100-NEXT: v_dual_add_f32 v10, v10, v14 :: v_dual_add_f32 v11, v11, v15
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1100-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
-; GFX1100-NEXT: v_dual_cndmask_b32 v8, v3, v9 :: v_dual_mov_b32 v9, 0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
-; GFX1100-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
-; GFX1100-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; GFX1100-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b128 v9, v[0:3], s[0:1]
-; GFX1100-NEXT: s_endpgm
-;
-; R600-LABEL: s_log10_v4f32:
-; R600: ; %bb.0:
-; R600-NEXT: ALU 76, @4, KC0[CB0:0-32], KC1[]
-; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-; R600-NEXT: ALU clause starting at 4:
-; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z,
-; R600-NEXT: SETGT * T1.W, literal.x, KC0[4].X,
-; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
-; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x,
-; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
-; R600-NEXT: MUL_IEEE T0.Z, KC0[3].Z, PV.W,
-; R600-NEXT: SETGT T2.W, literal.x, KC0[3].W,
-; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.y,
-; R600-NEXT: 8388608(1.175494e-38), 1333788672(4.294967e+09)
-; R600-NEXT: MUL_IEEE T1.Z, KC0[4].X, PS,
-; R600-NEXT: CNDE T3.W, PV.W, 1.0, literal.x,
-; R600-NEXT: LOG_IEEE * T0.X, PV.Z,
-; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
-; R600-NEXT: MUL_IEEE T0.Z, KC0[3].W, PV.W,
-; R600-NEXT: SETGT T3.W, literal.x, KC0[3].Y,
-; R600-NEXT: LOG_IEEE * T0.Y, PV.Z,
-; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
-; R600-NEXT: AND_INT T1.Y, PS, literal.x,
-; R600-NEXT: AND_INT T1.Z, T0.X, literal.x,
-; R600-NEXT: CNDE T4.W, PV.W, 1.0, literal.y,
-; R600-NEXT: LOG_IEEE * T0.Z, PV.Z,
-; R600-NEXT: -4096(nan), 1333788672(4.294967e+09)
-; R600-NEXT: MUL_IEEE T2.Y, KC0[3].Y, PV.W,
-; R600-NEXT: ADD T2.Z, T0.X, -PV.Z,
-; R600-NEXT: AND_INT T4.W, PS, literal.x,
-; R600-NEXT: ADD * T5.W, T0.Y, -PV.Y,
-; R600-NEXT: -4096(nan), 0(0.000000e+00)
-; R600-NEXT: MUL_IEEE T3.Y, PS, literal.x,
-; R600-NEXT: ADD T3.Z, T0.Z, -PV.W,
+; SI-SDAG-LABEL: s_log10_v4f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: s_mov_b32 s6, 0x3e9a209a
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s11, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s11, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v3
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s6, -v4
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x3284fbcf
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; SI-SDAG-NEXT: v_fma_f32 v5, v3, s7, v5
+; SI-SDAG-NEXT: s_mov_b32 s11, 0x7f800000
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v6, s10, v6
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; SI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s9, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; SI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v6
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, s4
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s6, -v2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v7, s9, v7
+; SI-SDAG-NEXT: v_fma_f32 v4, v6, s7, v4
+; SI-SDAG-NEXT: v_log_f32_e32 v7, v7
+; SI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s8, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v5
+; SI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v7
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_fma_f32 v6, v7, s6, -v5
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s4
+; SI-SDAG-NEXT: v_fma_f32 v6, v7, s7, v6
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s8, v1
+; SI-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; SI-SDAG-NEXT: v_log_f32_e32 v6, v1
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v4
+; SI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v6
+; SI-SDAG-NEXT: v_fma_f32 v5, v6, s6, -v4
+; SI-SDAG-NEXT: v_fma_f32 v5, v6, s7, v5
+; SI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s11
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log10_v4f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s0, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], s[6:7], s[6:7]
+; SI-GISEL-NEXT: s_cselect_b32 s9, s9, s0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; SI-GISEL-NEXT: s_cselect_b32 s8, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[6:7], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s1, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; SI-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
+; SI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; SI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s7, s10, s7
+; SI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s10, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, s6
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s8
+; SI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v2
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; SI-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
+; SI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; SI-GISEL-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s10, 0
+; SI-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s3, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; SI-GISEL-NEXT: v_sub_f32_e32 v1, s7, v6
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s6
+; SI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; SI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v7
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; SI-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; SI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; SI-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; SI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; SI-GISEL-NEXT: s_or_b64 s[2:3], s[2:3], s[2:3]
+; SI-GISEL-NEXT: s_cselect_b32 s2, s6, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, s9, v0
+; SI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log10_v4f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-SDAG-NEXT: s_mov_b32 s8, 0x7f800000
+; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s6
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v3
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v3, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v6, v5
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, s3
+; VI-SDAG-NEXT: v_ldexp_f32 v6, s2, v6
+; VI-SDAG-NEXT: v_log_f32_e32 v6, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-SDAG-NEXT: v_and_b32_e32 v2, 0xfffff000, v6
+; VI-SDAG-NEXT: v_sub_f32_e32 v4, v6, v2
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v2
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v8, v4
+; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v7, v4
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, s2
+; VI-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
+; VI-SDAG-NEXT: v_log_f32_e32 v7, v7
+; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-SDAG-NEXT: v_add_f32_e32 v2, v2, v4
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v5
+; VI-SDAG-NEXT: v_and_b32_e32 v5, 0xfffff000, v7
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: v_sub_f32_e32 v6, v7, v5
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x3e9a2000, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v9, 0x369a84fb, v5
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; VI-SDAG-NEXT: v_add_f32_e32 v6, v9, v6
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_add_f32_e32 v6, v8, v6
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a2000, v5
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; VI-SDAG-NEXT: v_log_f32_e32 v6, v1
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v4
+; VI-SDAG-NEXT: v_and_b32_e32 v4, 0xfffff000, v6
+; VI-SDAG-NEXT: v_sub_f32_e32 v5, v6, v4
+; VI-SDAG-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x369a84fb, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v8, v5
+; VI-SDAG-NEXT: v_add_f32_e32 v5, v7, v5
+; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3e9a2000, v4
+; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v6|, s8
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
+; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log10_v4f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x369a84fb
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3e9a2000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; VI-GISEL-NEXT: s_and_b32 s6, s0, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s6, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v5, s6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v5, v5, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s6, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v5
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; VI-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; VI-GISEL-NEXT: s_and_b32 s4, s9, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s4, v0
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x369a84fb, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v6, v7, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a2000, v2
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v2, v6, v2
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; VI-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; VI-GISEL-NEXT: s_and_b32 s4, s2, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v7, s4, v2
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v9, s4, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v8, v9, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a2000, v7
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, s4, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v7, v8, v7
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v7, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; VI-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; VI-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; VI-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; VI-GISEL-NEXT: s_and_b32 s2, s4, 0xfffff000
+; VI-GISEL-NEXT: v_subrev_f32_e32 v6, s2, v7
+; VI-GISEL-NEXT: v_mul_f32_e32 v8, 0x369a84fb, v6
+; VI-GISEL-NEXT: v_mul_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v3, v8
+; VI-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a2000, v6
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; VI-GISEL-NEXT: v_mul_f32_e32 v4, s2, v4
+; VI-GISEL-NEXT: v_add_f32_e32 v3, v4, v3
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; VI-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; VI-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; VI-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s0
+; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log10_v4f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: s_mov_b32 s8, 0x3e9a209a
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v3
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s9, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s8, -v5
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, s3
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v3, s9, v6
+; GFX900-SDAG-NEXT: s_mov_b32 s10, 0x7f800000
+; GFX900-SDAG-NEXT: v_ldexp_f32 v7, s2, v7
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v3|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v7
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s8, -v2
+; GFX900-SDAG-NEXT: v_ldexp_f32 v8, s1, v8
+; GFX900-SDAG-NEXT: v_fma_f32 v5, v7, s9, v5
+; GFX900-SDAG-NEXT: v_log_f32_e32 v8, v8
+; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v2, v5
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, v7, v2, vcc
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v2, v6
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v8
+; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s8, -v6
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-SDAG-NEXT: v_fma_f32 v7, v8, s9, v7
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-SDAG-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX900-SDAG-NEXT: v_log_f32_e32 v7, v1
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v8|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v1, v5
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v5, 0x3e9a209a, v7
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s8, -v5
+; GFX900-SDAG-NEXT: v_fma_f32 v6, v7, s9, v6
+; GFX900-SDAG-NEXT: v_add_f32_e32 v5, v5, v6
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v7|, s10
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v5, v0
+; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log10_v4f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x7f800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[6:7], |v0|, v5
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[6:7], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, s9, s0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s7, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s1, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v1
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v3, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v6, v0, v4, v6
+; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s9, v0
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s10, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s9, s10, s9
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, s6, v0
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v7, 0x3e9a209a, v2
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v3, -v7
+; GFX900-GISEL-NEXT: v_fma_f32 v8, v2, v4, v8
+; GFX900-GISEL-NEXT: v_add_f32_e32 v7, v7, v8
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v2|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v7
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s8, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s6
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s3, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v7, v1
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, s9, v6
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s4
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v2, s2, v2
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v6, 0x3e9a209a, v7
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v3, -v6
+; GFX900-GISEL-NEXT: v_fma_f32 v3, v7, v4, v3
+; GFX900-GISEL-NEXT: v_add_f32_e32 v3, v6, v3
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |v7|, v5
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s4, v7
+; GFX900-GISEL-NEXT: v_readfirstlane_b32 s6, v3
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, s6, s4
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s3, 0x411a209b, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v3, s2, v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log10_v4f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x411a209b, s6
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s7
+; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s6
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x411a209b, s8
+; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s9, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s7
+; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s3
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v6, v6
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x411a209b, s9
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v8, 0x3e9a209a, v2 :: v_dual_mul_f32 v9, 0x3e9a209a, v3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_mul_f32 v10, 0x3e9a209a, v6 :: v_dual_mul_f32 v11, 0x3e9a209a, v7
+; GFX1100-SDAG-NEXT: v_fma_f32 v12, 0x3e9a209a, v2, -v8
+; GFX1100-SDAG-NEXT: v_fma_f32 v13, 0x3e9a209a, v3, -v9
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_fma_f32 v14, 0x3e9a209a, v6, -v10
+; GFX1100-SDAG-NEXT: v_fma_f32 v15, 0x3e9a209a, v7, -v11
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v12, 0x3284fbcf, v2 :: v_dual_fmac_f32 v13, 0x3284fbcf, v3
+; GFX1100-SDAG-NEXT: v_dual_fmac_f32 v14, 0x3284fbcf, v6 :: v_dual_fmac_f32 v15, 0x3284fbcf, v7
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v8, v8, v12 :: v_dual_add_f32 v9, v9, v13
+; GFX1100-SDAG-NEXT: v_dual_add_f32 v10, v10, v14 :: v_dual_add_f32 v11, v11, v15
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
+; GFX1100-SDAG-NEXT: v_dual_cndmask_b32 v8, v3, v9 :: v_dual_mov_b32 v9, 0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v7|
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log10_v4f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s7
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s7, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, s8, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s1, s8
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s8, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, s9, s8
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s9, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s3
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s10, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, s10, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s10, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s3, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v0, s7, s6
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v2, s2, s10
+; GFX1100-GISEL-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v1, s8, s9
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, s5, s4
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s11, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x411a209b, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e64 v3, s3, s4
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
+;
+; R600-LABEL: s_log10_v4f32:
+; R600: ; %bb.0:
+; R600-NEXT: ALU 76, @4, KC0[CB0:0-32], KC1[]
+; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+; R600-NEXT: ALU clause starting at 4:
+; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z,
+; R600-NEXT: SETGT * T1.W, literal.x, KC0[4].X,
+; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT: CNDE * T2.W, PV.W, 1.0, literal.x,
+; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT: MUL_IEEE T0.Z, KC0[3].Z, PV.W,
+; R600-NEXT: SETGT T2.W, literal.x, KC0[3].W,
+; R600-NEXT: CNDE * T3.W, T1.W, 1.0, literal.y,
+; R600-NEXT: 8388608(1.175494e-38), 1333788672(4.294967e+09)
+; R600-NEXT: MUL_IEEE T1.Z, KC0[4].X, PS,
+; R600-NEXT: CNDE T3.W, PV.W, 1.0, literal.x,
+; R600-NEXT: LOG_IEEE * T0.X, PV.Z,
+; R600-NEXT: 1333788672(4.294967e+09), 0(0.000000e+00)
+; R600-NEXT: MUL_IEEE T0.Z, KC0[3].W, PV.W,
+; R600-NEXT: SETGT T3.W, literal.x, KC0[3].Y,
+; R600-NEXT: LOG_IEEE * T0.Y, PV.Z,
+; R600-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
+; R600-NEXT: AND_INT T1.Y, PS, literal.x,
+; R600-NEXT: AND_INT T1.Z, T0.X, literal.x,
+; R600-NEXT: CNDE T4.W, PV.W, 1.0, literal.y,
+; R600-NEXT: LOG_IEEE * T0.Z, PV.Z,
+; R600-NEXT: -4096(nan), 1333788672(4.294967e+09)
+; R600-NEXT: MUL_IEEE T2.Y, KC0[3].Y, PV.W,
+; R600-NEXT: ADD T2.Z, T0.X, -PV.Z,
+; R600-NEXT: AND_INT T4.W, PS, literal.x,
+; R600-NEXT: ADD * T5.W, T0.Y, -PV.Y,
+; R600-NEXT: -4096(nan), 0(0.000000e+00)
+; R600-NEXT: MUL_IEEE T3.Y, PS, literal.x,
+; R600-NEXT: ADD T3.Z, T0.Z, -PV.W,
; R600-NEXT: MUL_IEEE T6.W, PV.Z, literal.x,
; R600-NEXT: LOG_IEEE * T1.X, PV.Y,
; R600-NEXT: 916096251(4.605039e-06), 0(0.000000e+00)
@@ -1539,27 +2803,50 @@ define amdgpu_kernel void @s_log10_v4f32(ptr addrspace(1) %out, <4 x float> %in)
}
define float @v_log10_f32(float %in) {
-; SI-LABEL: v_log10_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32:
; VI: ; %bb.0:
@@ -1586,49 +2873,95 @@ define float @v_log10_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32:
; R600: ; %bb.0:
@@ -1644,29 +2977,52 @@ define float @v_log10_f32(float %in) {
}
define float @v_log10_fabs_f32(float %in) {
-; SI-LABEL: v_log10_fabs_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_fabs_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log10_fabs_f32:
+; SI-GISEL-LABEL: v_log10_fabs_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_log10_fabs_f32:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, 0x800000
@@ -1691,49 +3047,96 @@ define float @v_log10_fabs_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_fabs_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, |v0|, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_fabs_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_fabs_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
-; GFX1100-NEXT: v_ldexp_f32 v0, |v0|, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_fabs_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_fabs_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_fabs_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fabs_f32:
; R600: ; %bb.0:
@@ -1750,27 +3153,50 @@ define float @v_log10_fabs_f32(float %in) {
}
define float @v_log10_fneg_fabs_f32(float %in) {
-; SI-LABEL: v_log10_fneg_fabs_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x80800000
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_fneg_fabs_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_fneg_fabs_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_fneg_fabs_f32:
; VI: ; %bb.0:
@@ -1797,49 +3223,96 @@ define float @v_log10_fneg_fabs_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_fneg_fabs_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x80800000
-; GFX900-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, -|v0|, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_fneg_fabs_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_fneg_fabs_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_lt_f32_e64 s0, 0x80800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
-; GFX1100-NEXT: v_ldexp_f32 v0, -|v0|, v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_fneg_fabs_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_fneg_fabs_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_lt_f32_e64 s0, 0x80800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, s0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_fneg_fabs_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -|v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fneg_fabs_f32:
; R600: ; %bb.0:
@@ -1857,27 +3330,50 @@ define float @v_log10_fneg_fabs_f32(float %in) {
}
define float @v_log10_fneg_f32(float %in) {
-; SI-LABEL: v_log10_fneg_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x80800000
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, -v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_fneg_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, -v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_fneg_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_fneg_f32:
; VI: ; %bb.0:
@@ -1904,49 +3400,96 @@ define float @v_log10_fneg_f32(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_fneg_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x80800000
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, -v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_fneg_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_fneg_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x80800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, -v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_fneg_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_fneg_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x80800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_fneg_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, s0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_fneg_f32:
; R600: ; %bb.0:
@@ -2078,27 +3621,50 @@ define float @v_log10_f32_fast(float %in) {
}
define float @v_log10_f32_ninf(float %in) {
-; SI-LABEL: v_log10_f32_ninf:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32_ninf:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_ninf:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32_ninf:
; VI: ; %bb.0:
@@ -2125,49 +3691,95 @@ define float @v_log10_f32_ninf(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32_ninf:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32_ninf:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_ninf:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32_ninf:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_ninf:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_ninf:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_ninf:
; R600: ; %bb.0:
@@ -2623,156 +4235,225 @@ define float @v_log10_f32_daz(float %in) #0 {
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-GISEL-LABEL: v_log10_f32_daz:
+; GFX900-GISEL-LABEL: v_log10_f32_daz:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_daz:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_daz:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; R600-LABEL: v_log10_f32_daz:
+; R600: ; %bb.0:
+; R600-NEXT: CF_END
+; R600-NEXT: PAD
+;
+; CM-LABEL: v_log10_f32_daz:
+; CM: ; %bb.0:
+; CM-NEXT: CF_END
+; CM-NEXT: PAD
+ %result = call float @llvm.log10.f32(float %in)
+ ret float %result
+}
+
+define float @v_log10_f32_nnan(float %in) {
+; SI-SDAG-LABEL: v_log10_f32_nnan:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_nnan:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-LABEL: v_log10_f32_nnan:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, 0x800000
+; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; VI-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-NEXT: v_log_f32_e32 v0, v0
+; VI-NEXT: s_mov_b32 s4, 0x7f800000
+; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
+; VI-NEXT: v_sub_f32_e32 v2, v0, v1
+; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
+; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
+; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
+; VI-NEXT: v_add_f32_e32 v2, v4, v2
+; VI-NEXT: v_add_f32_e32 v2, v3, v2
+; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
+; VI-NEXT: v_add_f32_e32 v1, v1, v2
+; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log10_f32_nnan:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log10_f32_nnan:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x3284fbcf
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
-; GFX900-GISEL-NEXT: v_mul_f32_e32 v4, 0x3e9a209a, v0
-; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v4
-; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v2, v1
-; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v4, v1
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v3
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-SDAG-LABEL: v_log10_f32_daz:
+; GFX1100-SDAG-LABEL: v_log10_f32_nnan:
; GFX1100-SDAG: ; %bb.0:
; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-GISEL-LABEL: v_log10_f32_daz:
+; GFX1100-GISEL-LABEL: v_log10_f32_nnan:
; GFX1100-GISEL: ; %bb.0:
; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; R600-LABEL: v_log10_f32_daz:
-; R600: ; %bb.0:
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-;
-; CM-LABEL: v_log10_f32_daz:
-; CM: ; %bb.0:
-; CM-NEXT: CF_END
-; CM-NEXT: PAD
- %result = call float @llvm.log10.f32(float %in)
- ret float %result
-}
-
-define float @v_log10_f32_nnan(float %in) {
-; SI-LABEL: v_log10_f32_nnan:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_log10_f32_nnan:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x7f800000
-; VI-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
-; VI-NEXT: v_sub_f32_e32 v2, v0, v1
-; VI-NEXT: v_mul_f32_e32 v3, 0x3e9a2000, v2
-; VI-NEXT: v_mul_f32_e32 v2, 0x369a84fb, v2
-; VI-NEXT: v_mul_f32_e32 v4, 0x369a84fb, v1
-; VI-NEXT: v_add_f32_e32 v2, v4, v2
-; VI-NEXT: v_add_f32_e32 v2, v3, v2
-; VI-NEXT: v_mul_f32_e32 v1, 0x3e9a2000, v1
-; VI-NEXT: v_add_f32_e32 v1, v1, v2
-; VI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; VI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-LABEL: v_log10_f32_nnan:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-LABEL: v_log10_f32_nnan:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
-;
; R600-LABEL: v_log10_f32_nnan:
; R600: ; %bb.0:
; R600-NEXT: CF_END
@@ -2909,27 +4590,50 @@ define float @v_log10_f32_nnan_daz(float %in) #0 {
}
define float @v_log10_f32_nnan_dynamic(float %in) #1 {
-; SI-LABEL: v_log10_f32_nnan_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32_nnan_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_nnan_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32_nnan_dynamic:
; VI: ; %bb.0:
@@ -2956,49 +4660,95 @@ define float @v_log10_f32_nnan_dynamic(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32_nnan_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32_nnan_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_nnan_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32_nnan_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_nnan_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_nnan_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_nnan_dynamic:
; R600: ; %bb.0:
@@ -3136,27 +4886,50 @@ define float @v_log10_f32_ninf_daz(float %in) #0 {
}
define float @v_log10_f32_ninf_dynamic(float %in) #1 {
-; SI-LABEL: v_log10_f32_ninf_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32_ninf_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_ninf_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32_ninf_dynamic:
; VI: ; %bb.0:
@@ -3183,49 +4956,95 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32_ninf_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32_ninf_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_ninf_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32_ninf_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_ninf_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_ninf_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_ninf_dynamic:
; R600: ; %bb.0:
@@ -3241,24 +5060,44 @@ define float @v_log10_f32_ninf_dynamic(float %in) #1 {
}
define float @v_log10_f32_nnan_ninf(float %in) {
-; SI-LABEL: v_log10_f32_nnan_ninf:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v0, v0, s4, v2
-; SI-NEXT: v_add_f32_e32 v0, v1, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32_nnan_ninf:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_nnan_ninf:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32_nnan_ninf:
; VI: ; %bb.0:
@@ -3282,43 +5121,84 @@ define float @v_log10_f32_nnan_ninf(float %in) {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32_nnan_ninf:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v0, v0, s4, v2
-; GFX900-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32_nnan_ninf:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_nnan_ninf:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v0, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32_nnan_ninf:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_nnan_ninf:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_nnan_ninf:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_nnan_ninf:
; R600: ; %bb.0:
@@ -3437,24 +5317,44 @@ define float @v_log10_f32_nnan_ninf_daz(float %in) #0 {
}
define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 {
-; SI-LABEL: v_log10_f32_nnan_ninf_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v0, v0, s4, v2
-; SI-NEXT: v_add_f32_e32 v0, v1, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32_nnan_ninf_dynamic:
; VI: ; %bb.0:
@@ -3478,43 +5378,84 @@ define float @v_log10_f32_nnan_ninf_dynamic(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32_nnan_ninf_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v0, v0, s4, v2
-; GFX900-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v0, v0, s4, v2
+; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_nnan_ninf_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v0, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v0, v1, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v0, v0, v3, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v0, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_nnan_ninf_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v0, v1, v2
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_nnan_ninf_dynamic:
; R600: ; %bb.0:
@@ -3559,27 +5500,50 @@ define float @v_log10_f32_fast_daz(float %in) #0 {
}
define float @v_log10_f32_dynamic_mode(float %in) #1 {
-; SI-LABEL: v_log10_f32_dynamic_mode:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x3e9a209a
-; SI-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; SI-NEXT: v_fma_f32 v2, v0, s4, -v1
-; SI-NEXT: s_mov_b32 s4, 0x3284fbcf
-; SI-NEXT: v_fma_f32 v2, v0, s4, v2
-; SI-NEXT: s_mov_b32 s4, 0x7f800000
-; SI-NEXT: v_add_f32_e32 v1, v1, v2
-; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; SI-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log10_f32_dynamic_mode:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_log10_f32_dynamic_mode:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; SI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; SI-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; SI-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_log10_f32_dynamic_mode:
; VI: ; %bb.0:
@@ -3606,49 +5570,95 @@ define float @v_log10_f32_dynamic_mode(float %in) #1 {
; VI-NEXT: v_sub_f32_e32 v0, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log10_f32_dynamic_mode:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3e9a209a
-; GFX900-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, -v1
-; GFX900-NEXT: s_mov_b32 s4, 0x3284fbcf
-; GFX900-NEXT: v_fma_f32 v2, v0, s4, v2
-; GFX900-NEXT: s_mov_b32 s4, 0x7f800000
-; GFX900-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX900-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x411a209b
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; GFX900-SDAG-LABEL: v_log10_f32_dynamic_mode:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3e9a209a
+; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3284fbcf
+; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7f800000
+; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log10_f32_dynamic_mode:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
-; GFX1100-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_add_f32_e32 v1, v1, v2
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; GFX900-GISEL-LABEL: v_log10_f32_dynamic_mode:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x3e9a209a
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3284fbcf
+; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, 0x3e9a209a, v0
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v1, -v2
+; GFX900-GISEL-NEXT: v_fma_f32 v1, v0, v3, v1
+; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x411a209b
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log10_f32_dynamic_mode:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-SDAG-NEXT: v_fmamk_f32 v2, v0, 0x3284fbcf, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log10_f32_dynamic_mode:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_mul_f32_e32 v1, 0x3e9a209a, v0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x7f800000, |v0|
+; GFX1100-GISEL-NEXT: v_fma_f32 v2, 0x3e9a209a, v0, -v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_fmac_f32_e32 v2, 0x3284fbcf, v0
+; GFX1100-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v1, s0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x411a209b, vcc_lo
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log10_f32_dynamic_mode:
; R600: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index f47bc253a34ad..49e815d8400c5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -14,83 +14,171 @@
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
-; SI-LABEL: s_log2_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dword s6, s[4:5], 0xb
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-NEXT: s_and_b64 s[2:3], vcc, exec
-; SI-NEXT: s_cselect_b32 s2, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s2
-; SI-NEXT: v_ldexp_f32_e32 v1, s6, v1
-; SI-NEXT: v_log_f32_e32 v1, v1
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v0, v1, v0
-; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log2_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dword s6, s[4:5], 0x2c
-; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: s_cselect_b32 s2, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s2
-; VI-NEXT: v_ldexp_f32 v1, s6, v1
-; VI-NEXT: v_log_f32_e32 v1, v1
-; VI-NEXT: v_sub_f32_e32 v2, v1, v0
-; VI-NEXT: v_mov_b32_e32 v0, s0
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: flat_store_dword v[0:1], v2
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log2_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dword s6, s[4:5], 0x2c
-; GFX900-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_mov_b32_e32 v2, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s2
-; GFX900-NEXT: v_ldexp_f32 v1, s6, v1
-; GFX900-NEXT: v_log_f32_e32 v1, v1
-; GFX900-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX900-NEXT: global_store_dword v2, v0, s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log2_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1100-NEXT: v_mov_b32_e32 v2, 0
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s0
-; GFX1100-NEXT: s_and_b32 s0, s0, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1100-NEXT: v_ldexp_f32 v1, s2, s3
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v1, v0
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: global_store_b32 v2, v0, s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log2_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s6, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log2_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dword s6, s[4:5], 0xb
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s6, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; SI-GISEL-NEXT: s_cselect_b32 s3, 0x42000000, 0
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log2_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v1, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v1, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log2_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s2, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s2, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log2_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dword s6, s[4:5], 0x2c
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s2
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s6, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log2_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v0
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log2_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1100-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, s2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s0
+; GFX1100-SDAG-NEXT: s_and_b32 s0, s0, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s2, s3
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v1, v0
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log2_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2c
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s1, 0x800000, s0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s1
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_f32:
; R600: ; %bb.0:
@@ -140,109 +228,233 @@ define amdgpu_kernel void @s_log2_f32(ptr addrspace(1) %out, float %in) {
; FIXME: We should be able to merge these packets together on Cayman so we
; have a maximum of 4 instructions.
define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
-; SI-LABEL: s_log2_v2f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; SI-NEXT: s_cselect_b32 s4, 32, 0
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; SI-NEXT: v_mov_b32_e32 v3, s4
-; SI-NEXT: s_and_b64 s[4:5], vcc, exec
-; SI-NEXT: v_ldexp_f32_e32 v3, s3, v3
-; SI-NEXT: s_cselect_b32 s3, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s3
-; SI-NEXT: v_ldexp_f32_e32 v1, s2, v1
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_log_f32_e32 v4, v1
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: v_sub_f32_e32 v1, v3, v2
-; SI-NEXT: v_sub_f32_e32 v0, v4, v0
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log2_v2f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: s_cselect_b32 s4, 32, 0
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: s_and_b64 s[4:5], vcc, exec
-; VI-NEXT: v_ldexp_f32 v3, s3, v3
-; VI-NEXT: s_cselect_b32 s3, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s3
-; VI-NEXT: v_ldexp_f32 v1, s2, v1
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_log_f32_e32 v4, v1
-; VI-NEXT: v_sub_f32_e32 v1, v3, v2
-; VI-NEXT: v_sub_f32_e32 v0, v4, v0
-; VI-NEXT: v_mov_b32_e32 v3, s1
-; VI-NEXT: v_mov_b32_e32 v2, s0
-; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log2_v2f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_mov_b32_e32 v5, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: v_mov_b32_e32 v3, s4
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX900-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s3
-; GFX900-NEXT: v_ldexp_f32 v1, s2, v1
-; GFX900-NEXT: v_log_f32_e32 v3, v3
-; GFX900-NEXT: v_log_f32_e32 v4, v1
-; GFX900-NEXT: v_sub_f32_e32 v1, v3, v2
-; GFX900-NEXT: v_sub_f32_e32 v0, v4, v0
-; GFX900-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log2_v2f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s4
-; GFX1100-NEXT: s_and_b32 s4, s4, exec_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s5
-; GFX1100-NEXT: s_cselect_b32 s4, 32, 0
-; GFX1100-NEXT: s_and_b32 s5, s5, exec_lo
-; GFX1100-NEXT: s_cselect_b32 s5, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v1, s3, s4
-; GFX1100-NEXT: v_ldexp_f32 v3, s2, s5
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_log_f32_e32 v1, v1
-; GFX1100-NEXT: v_log_f32_e32 v3, v3
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_sub_f32 v1, v1, v0
-; GFX1100-NEXT: v_sub_f32_e32 v0, v3, v2
-; GFX1100-NEXT: global_store_b64 v4, v[0:1], s[0:1]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log2_v2f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; SI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s3, v3
+; SI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s2, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v4, v1
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v3, v2
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log2_v2f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[4:5], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s3, v0
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v1
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log2_v2f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; VI-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v4, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v3, v2
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log2_v2f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v0
+; VI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v1
+; VI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log2_v2f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s3
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s2, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT: v_log_f32_e32 v4, v1
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v3, v2
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v4, v0
+; GFX900-SDAG-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log2_v2f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s2, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s3, v0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v0
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log2_v2f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s4
+; GFX1100-SDAG-NEXT: s_and_b32 s4, s4, exec_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 0x42000000, s5
+; GFX1100-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s5, s5, exec_lo
+; GFX1100-SDAG-NEXT: s_cselect_b32 s5, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v1, s3, s4
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s5
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_sub_f32 v1, v1, v0
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v3, v2
+; GFX1100-SDAG-NEXT: global_store_b64 v4, v[0:1], s[0:1]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log2_v2f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s4, 0x800000, s2
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s5, 0x800000, s3
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s6, s6, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s2, s6
+; GFX1100-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s3, s7
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s5, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_dual_subrev_f32 v0, s4, v0 :: v_dual_subrev_f32 v1, s2, v1
+; GFX1100-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v2f32:
; R600: ; %bb.0:
@@ -308,147 +520,320 @@ define amdgpu_kernel void @s_log2_v2f32(ptr addrspace(1) %out, <2 x float> %in)
}
define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
-; SI-LABEL: s_log2_v3f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
-; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: s_mov_b32 s7, 0xf000
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; SI-NEXT: s_and_b64 s[8:9], vcc, exec
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; SI-NEXT: s_cselect_b32 s3, 32, 0
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; SI-NEXT: v_mov_b32_e32 v3, s3
-; SI-NEXT: s_and_b64 s[8:9], vcc, exec
-; SI-NEXT: v_ldexp_f32_e32 v3, s1, v3
-; SI-NEXT: s_cselect_b32 s1, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v5, s1
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; SI-NEXT: v_ldexp_f32_e32 v5, s0, v5
-; SI-NEXT: s_and_b64 s[0:1], vcc, exec
-; SI-NEXT: s_cselect_b32 s0, 32, 0
-; SI-NEXT: v_mov_b32_e32 v0, s0
-; SI-NEXT: v_ldexp_f32_e32 v0, s2, v0
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_log_f32_e32 v7, v0
-; SI-NEXT: v_log_f32_e32 v5, v5
-; SI-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: v_sub_f32_e32 v1, v3, v2
-; SI-NEXT: v_sub_f32_e32 v2, v7, v6
-; SI-NEXT: v_sub_f32_e32 v0, v5, v4
-; SI-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
-; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log2_v3f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: s_cselect_b32 s3, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v3, s3
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-NEXT: v_ldexp_f32 v3, s2, v3
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-NEXT: s_cselect_b32 s2, 32, 0
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-NEXT: v_mov_b32_e32 v5, s2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_ldexp_f32 v5, s1, v5
-; VI-NEXT: s_cselect_b32 s1, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_ldexp_f32 v1, s0, v1
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_log_f32_e32 v5, v5
-; VI-NEXT: v_log_f32_e32 v6, v1
-; VI-NEXT: v_sub_f32_e32 v2, v3, v2
-; VI-NEXT: v_sub_f32_e32 v1, v5, v4
-; VI-NEXT: v_sub_f32_e32 v0, v6, v0
-; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: v_mov_b32_e32 v4, s5
-; VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log2_v3f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_mov_b32_e32 v7, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v3, s3
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-NEXT: v_ldexp_f32 v3, s2, v3
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-NEXT: v_mov_b32_e32 v5, s2
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_ldexp_f32 v5, s1, v5
-; GFX900-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-NEXT: v_ldexp_f32 v1, s0, v1
-; GFX900-NEXT: v_log_f32_e32 v3, v3
-; GFX900-NEXT: v_log_f32_e32 v5, v5
-; GFX900-NEXT: v_log_f32_e32 v6, v1
-; GFX900-NEXT: v_sub_f32_e32 v2, v3, v2
-; GFX900-NEXT: v_sub_f32_e32 v1, v5, v4
-; GFX900-NEXT: v_sub_f32_e32 v0, v6, v0
-; GFX900-NEXT: global_store_dwordx3 v7, v[0:2], s[6:7]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log2_v3f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_clause 0x1
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s3
-; GFX1100-NEXT: s_and_b32 s3, s3, exec_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s6
-; GFX1100-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s7
-; GFX1100-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-NEXT: v_ldexp_f32 v2, s2, s3
-; GFX1100-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v4, s1, s6
-; GFX1100-NEXT: v_ldexp_f32 v5, s0, s2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-NEXT: v_log_f32_e32 v4, v4
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_log_f32_e32 v5, v5
-; GFX1100-NEXT: v_mov_b32_e32 v6, 0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_dual_sub_f32 v2, v2, v0 :: v_dual_sub_f32 v1, v4, v1
-; GFX1100-NEXT: v_sub_f32_e32 v0, v5, v3
-; GFX1100-NEXT: global_store_b96 v6, v[0:2], s[4:5]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log2_v3f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
+; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; SI-SDAG-NEXT: s_and_b64 s[8:9], vcc, exec
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; SI-SDAG-NEXT: s_and_b64 s[8:9], vcc, exec
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s1, v3
+; SI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, s1
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v5, s0, v5
+; SI-SDAG-NEXT: s_and_b64 s[0:1], vcc, exec
+; SI-SDAG-NEXT: s_cselect_b32 s0, 32, 0
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, s2, v0
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v7, v0
+; SI-SDAG-NEXT: v_log_f32_e32 v5, v5
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v3, v2
+; SI-SDAG-NEXT: v_sub_f32_e32 v2, v7, v6
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v5, v4
+; SI-SDAG-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log2_v3f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
+; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: s_mov_b32 s6, -1
+; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], s[0:1], s[0:1]
+; SI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[0:1], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s9, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; SI-GISEL-NEXT: v_log_f32_e32 v2, v2
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s10, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v3, v1
+; SI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v2
+; SI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log2_v3f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s2
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_ldexp_f32 v5, s1, v5
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v5, v5
+; VI-SDAG-NEXT: v_log_f32_e32 v6, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v5, v4
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v6, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5
+; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log2_v3f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
+; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v0, s4, v0
+; VI-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; VI-GISEL-NEXT: v_ldexp_f32 v2, s9, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; VI-GISEL-NEXT: v_log_f32_e32 v2, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v3, v1
+; VI-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v2
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s3
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s2
+; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log2_v3f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s3
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s2, v3
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, s2
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_ldexp_f32 v5, s1, v5
+; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT: v_log_f32_e32 v5, v5
+; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v1
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v3, v2
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v5, v4
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v6, v0
+; GFX900-SDAG-NEXT: global_store_dwordx3 v7, v[0:2], s[6:7]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log2_v3f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s8, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s4, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s1
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s4, s4, 5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s9, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s4
+; GFX900-GISEL-NEXT: v_log_f32_e32 v2, v2
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s10, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v2
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log2_v3f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_clause 0x1
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s3
+; GFX1100-SDAG-NEXT: s_and_b32 s3, s3, exec_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s6
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v3, 0, 0x42000000, s7
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s2, s3
+; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v4, s1, s6
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v5, s0, s2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v4, v4
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v5, v5
+; GFX1100-SDAG-NEXT: v_mov_b32_e32 v6, 0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v2, v2, v0 :: v_dual_sub_f32 v1, v4, v1
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v5, v3
+; GFX1100-SDAG-NEXT: global_store_b96 v6, v[0:2], s[4:5]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log2_v3f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s3, 0x800000, s0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s3, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s3, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, s0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, s8
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_dual_subrev_f32 v0, s3, v0 :: v_dual_subrev_f32 v1, s6, v1
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v2, s2, v2
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b96 v3, v[0:2], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v3f32:
; R600: ; %bb.0:
@@ -537,175 +922,389 @@ define amdgpu_kernel void @s_log2_v3f32(ptr addrspace(1) %out, <3 x float> %in)
; FIXME: We should be able to merge these packets together on Cayman so we
; have a maximum of 4 instructions.
define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
-; SI-LABEL: s_log2_v4f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd
-; SI-NEXT: v_mov_b32_e32 v0, 0x800000
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: s_mov_b32 s3, 0xf000
-; SI-NEXT: s_mov_b32 s2, -1
-; SI-NEXT: s_waitcnt lgkmcnt(0)
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
-; SI-NEXT: s_and_b64 s[8:9], vcc, exec
-; SI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; SI-NEXT: s_cselect_b32 s8, 32, 0
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
-; SI-NEXT: v_mov_b32_e32 v3, s8
-; SI-NEXT: s_and_b64 s[8:9], vcc, exec
-; SI-NEXT: v_ldexp_f32_e32 v3, s7, v3
-; SI-NEXT: s_cselect_b32 s7, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v5, s7
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
-; SI-NEXT: v_ldexp_f32_e32 v5, s6, v5
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; SI-NEXT: s_cselect_b32 s6, 32, 0
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_mov_b32_e32 v7, s6
-; SI-NEXT: s_and_b64 s[6:7], vcc, exec
-; SI-NEXT: v_ldexp_f32_e32 v7, s5, v7
-; SI-NEXT: s_cselect_b32 s5, 32, 0
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; SI-NEXT: v_mov_b32_e32 v1, s5
-; SI-NEXT: v_ldexp_f32_e32 v1, s4, v1
-; SI-NEXT: v_log_f32_e32 v3, v3
-; SI-NEXT: v_log_f32_e32 v5, v5
-; SI-NEXT: v_log_f32_e32 v7, v7
-; SI-NEXT: v_log_f32_e32 v8, v1
-; SI-NEXT: v_sub_f32_e32 v3, v3, v2
-; SI-NEXT: v_sub_f32_e32 v2, v5, v4
-; SI-NEXT: v_sub_f32_e32 v1, v7, v6
-; SI-NEXT: v_sub_f32_e32 v0, v8, v0
-; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; SI-NEXT: s_endpgm
-;
-; VI-LABEL: s_log2_v4f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
-; VI-NEXT: v_mov_b32_e32 v0, 0x800000
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; VI-NEXT: s_cselect_b32 s6, 32, 0
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: s_and_b64 s[6:7], vcc, exec
-; VI-NEXT: v_ldexp_f32 v3, s3, v3
-; VI-NEXT: s_cselect_b32 s3, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v5, s3
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; VI-NEXT: v_ldexp_f32 v5, s2, v5
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
-; VI-NEXT: s_cselect_b32 s2, 32, 0
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; VI-NEXT: v_mov_b32_e32 v7, s2
-; VI-NEXT: s_and_b64 s[2:3], vcc, exec
-; VI-NEXT: v_ldexp_f32 v7, s1, v7
-; VI-NEXT: s_cselect_b32 s1, 32, 0
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: v_ldexp_f32 v1, s0, v1
-; VI-NEXT: v_log_f32_e32 v3, v3
-; VI-NEXT: v_log_f32_e32 v5, v5
-; VI-NEXT: v_log_f32_e32 v7, v7
-; VI-NEXT: v_log_f32_e32 v8, v1
-; VI-NEXT: v_sub_f32_e32 v3, v3, v2
-; VI-NEXT: v_sub_f32_e32 v2, v5, v4
-; VI-NEXT: v_sub_f32_e32 v1, v7, v6
-; VI-NEXT: v_sub_f32_e32 v0, v8, v0
-; VI-NEXT: v_mov_b32_e32 v4, s4
-; VI-NEXT: v_mov_b32_e32 v5, s5
-; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; VI-NEXT: s_endpgm
-;
-; GFX900-LABEL: s_log2_v4f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
-; GFX900-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
-; GFX900-NEXT: v_mov_b32_e32 v0, 0x800000
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_mov_b32_e32 v4, 0
-; GFX900-NEXT: s_waitcnt lgkmcnt(0)
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
-; GFX900-NEXT: s_cselect_b32 s4, 32, 0
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
-; GFX900-NEXT: v_mov_b32_e32 v3, s4
-; GFX900-NEXT: s_and_b64 s[4:5], vcc, exec
-; GFX900-NEXT: v_ldexp_f32 v3, s3, v3
-; GFX900-NEXT: s_cselect_b32 s3, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v6, s3
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
-; GFX900-NEXT: v_ldexp_f32 v6, s2, v6
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc
-; GFX900-NEXT: s_cselect_b32 s2, 32, 0
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GFX900-NEXT: v_mov_b32_e32 v8, s2
-; GFX900-NEXT: s_and_b64 s[2:3], vcc, exec
-; GFX900-NEXT: v_ldexp_f32 v8, s1, v8
-; GFX900-NEXT: s_cselect_b32 s1, 32, 0
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GFX900-NEXT: v_mov_b32_e32 v1, s1
-; GFX900-NEXT: v_ldexp_f32 v1, s0, v1
-; GFX900-NEXT: v_log_f32_e32 v3, v3
-; GFX900-NEXT: v_log_f32_e32 v6, v6
-; GFX900-NEXT: v_log_f32_e32 v8, v8
-; GFX900-NEXT: v_log_f32_e32 v9, v1
-; GFX900-NEXT: v_sub_f32_e32 v3, v3, v2
-; GFX900-NEXT: v_sub_f32_e32 v2, v6, v5
-; GFX900-NEXT: v_sub_f32_e32 v1, v8, v7
-; GFX900-NEXT: v_sub_f32_e32 v0, v9, v0
-; GFX900-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
-; GFX900-NEXT: s_endpgm
-;
-; GFX1100-LABEL: s_log2_v4f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_clause 0x1
-; GFX1100-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
-; GFX1100-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX1100-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1100-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s6
-; GFX1100-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s7
-; GFX1100-NEXT: s_cselect_b32 s6, 32, 0
-; GFX1100-NEXT: s_and_b32 s7, s7, exec_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s8
-; GFX1100-NEXT: s_cselect_b32 s7, 32, 0
-; GFX1100-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1100-NEXT: v_ldexp_f32 v2, s3, s6
-; GFX1100-NEXT: s_cselect_b32 s3, 32, 0
-; GFX1100-NEXT: s_and_b32 s6, s9, exec_lo
-; GFX1100-NEXT: v_ldexp_f32 v3, s2, s7
-; GFX1100-NEXT: s_cselect_b32 s2, 32, 0
-; GFX1100-NEXT: v_ldexp_f32 v6, s1, s3
-; GFX1100-NEXT: v_ldexp_f32 v7, s0, s2
-; GFX1100-NEXT: v_log_f32_e32 v2, v2
-; GFX1100-NEXT: v_log_f32_e32 v8, v3
-; GFX1100-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s9
-; GFX1100-NEXT: v_log_f32_e32 v6, v6
-; GFX1100-NEXT: v_log_f32_e32 v7, v7
-; GFX1100-NEXT: v_mov_b32_e32 v9, 0
-; GFX1100-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
-; GFX1100-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
-; GFX1100-NEXT: global_store_b128 v9, v[0:3], s[4:5]
-; GFX1100-NEXT: s_endpgm
+; SI-SDAG-LABEL: s_log2_v4f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
+; SI-SDAG-NEXT: s_mov_b32 s2, -1
+; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
+; SI-SDAG-NEXT: s_and_b64 s[8:9], vcc, exec
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; SI-SDAG-NEXT: s_cselect_b32 s8, 32, 0
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, s8
+; SI-SDAG-NEXT: s_and_b64 s[8:9], vcc, exec
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v3, s7, v3
+; SI-SDAG-NEXT: s_cselect_b32 s7, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, s7
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v5, s6, v5
+; SI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
+; SI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, s6
+; SI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v7, s5, v7
+; SI-SDAG-NEXT: s_cselect_b32 s5, 32, 0
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, s5
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, s4, v1
+; SI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; SI-SDAG-NEXT: v_log_f32_e32 v5, v5
+; SI-SDAG-NEXT: v_log_f32_e32 v7, v7
+; SI-SDAG-NEXT: v_log_f32_e32 v8, v1
+; SI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; SI-SDAG-NEXT: v_sub_f32_e32 v2, v5, v4
+; SI-SDAG-NEXT: v_sub_f32_e32 v1, v7, v6
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v8, v0
+; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-SDAG-NEXT: s_endpgm
+;
+; SI-GISEL-LABEL: s_log2_v4f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
+; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
+; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s9, v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, s3
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, s9, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, s8, v0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v1, s2, v1
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s11, v2
+; SI-GISEL-NEXT: v_subrev_f32_e32 v0, s4, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; SI-GISEL-NEXT: s_cselect_b32 s4, 0x42000000, 0
+; SI-GISEL-NEXT: s_or_b64 s[2:3], vcc, vcc
+; SI-GISEL-NEXT: s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT: s_lshl_b32 s3, s3, 5
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v3, s10, v3
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v2, s11, v2
+; SI-GISEL-NEXT: v_log_f32_e32 v3, v3
+; SI-GISEL-NEXT: v_log_f32_e32 v4, v2
+; SI-GISEL-NEXT: s_cmp_lg_u32 s2, 0
+; SI-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; SI-GISEL-NEXT: v_subrev_f32_e32 v2, s4, v3
+; SI-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v4
+; SI-GISEL-NEXT: s_mov_b32 s2, -1
+; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-GISEL-NEXT: s_endpgm
+;
+; VI-SDAG-LABEL: s_log2_v4f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; VI-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v3, s6
+; VI-SDAG-NEXT: s_and_b64 s[6:7], vcc, exec
+; VI-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; VI-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s3
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; VI-SDAG-NEXT: v_ldexp_f32 v5, s2, v5
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v1, vcc
+; VI-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, s2
+; VI-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; VI-SDAG-NEXT: v_ldexp_f32 v7, s1, v7
+; VI-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; VI-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; VI-SDAG-NEXT: v_log_f32_e32 v3, v3
+; VI-SDAG-NEXT: v_log_f32_e32 v5, v5
+; VI-SDAG-NEXT: v_log_f32_e32 v7, v7
+; VI-SDAG-NEXT: v_log_f32_e32 v8, v1
+; VI-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; VI-SDAG-NEXT: v_sub_f32_e32 v2, v5, v4
+; VI-SDAG-NEXT: v_sub_f32_e32 v1, v7, v6
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v8, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
+; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
+; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-SDAG-NEXT: s_endpgm
+;
+; VI-GISEL-LABEL: s_log2_v4f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
+; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, s7
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; VI-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s7, s7, 5
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s7
+; VI-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v1, v1
+; VI-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; VI-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v1
+; VI-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; VI-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; VI-GISEL-NEXT: v_ldexp_f32 v3, s2, v3
+; VI-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; VI-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; VI-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; VI-GISEL-NEXT: v_log_f32_e32 v3, v3
+; VI-GISEL-NEXT: v_ldexp_f32 v2, s3, v2
+; VI-GISEL-NEXT: v_log_f32_e32 v4, v2
+; VI-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; VI-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; VI-GISEL-NEXT: v_subrev_f32_e32 v3, s0, v4
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, s4
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, s5
+; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-GISEL-NEXT: s_endpgm
+;
+; GFX900-SDAG-LABEL: s_log2_v4f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x800000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v1, vcc
+; GFX900-SDAG-NEXT: s_cselect_b32 s4, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, s4
+; GFX900-SDAG-NEXT: s_and_b64 s[4:5], vcc, exec
+; GFX900-SDAG-NEXT: v_ldexp_f32 v3, s3, v3
+; GFX900-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, s3
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
+; GFX900-SDAG-NEXT: v_ldexp_f32 v6, s2, v6
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v7, 0, v1, vcc
+; GFX900-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v8, s2
+; GFX900-SDAG-NEXT: s_and_b64 s[2:3], vcc, exec
+; GFX900-SDAG-NEXT: v_ldexp_f32 v8, s1, v8
+; GFX900-SDAG-NEXT: s_cselect_b32 s1, 32, 0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, s1
+; GFX900-SDAG-NEXT: v_ldexp_f32 v1, s0, v1
+; GFX900-SDAG-NEXT: v_log_f32_e32 v3, v3
+; GFX900-SDAG-NEXT: v_log_f32_e32 v6, v6
+; GFX900-SDAG-NEXT: v_log_f32_e32 v8, v8
+; GFX900-SDAG-NEXT: v_log_f32_e32 v9, v1
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v3, v2
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, v6, v5
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v1, v8, v7
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v9, v0
+; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX900-SDAG-NEXT: s_endpgm
+;
+; GFX900-GISEL-LABEL: s_log2_v4f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
+; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x800000
+; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, s5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v2
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s4, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s5, s5, 5
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, s5
+; GFX900-GISEL-NEXT: v_ldexp_f32 v1, s1, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s4, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v2
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v1, s0, v1
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s3, v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, s1
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GFX900-GISEL-NEXT: v_ldexp_f32 v3, s2, v3
+; GFX900-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX900-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX900-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v3, v3
+; GFX900-GISEL-NEXT: v_ldexp_f32 v2, s3, v2
+; GFX900-GISEL-NEXT: v_log_f32_e32 v4, v2
+; GFX900-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v2, s0, v3
+; GFX900-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GFX900-GISEL-NEXT: v_subrev_f32_e32 v3, s0, v4
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
+; GFX900-GISEL-NEXT: s_endpgm
+;
+; GFX1100-SDAG-LABEL: s_log2_v4f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_clause 0x1
+; GFX1100-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX1100-SDAG-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s3
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s2
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s8, 0x800000, s1
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 0x42000000, s6
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s7
+; GFX1100-SDAG-NEXT: s_cselect_b32 s6, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s7, s7, exec_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 0x42000000, s8
+; GFX1100-SDAG-NEXT: s_cselect_b32 s7, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s8, s8, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v2, s3, s6
+; GFX1100-SDAG-NEXT: s_cselect_b32 s3, 32, 0
+; GFX1100-SDAG-NEXT: s_and_b32 s6, s9, exec_lo
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v3, s2, s7
+; GFX1100-SDAG-NEXT: s_cselect_b32 s2, 32, 0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v6, s1, s3
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v7, s0, s2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v8, v3
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 0x42000000, s9
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v6, v6
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v7, v7
+; GFX1100-SDAG-NEXT: v_mov_b32_e32 v9, 0
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_3)
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v3, v2, v0 :: v_dual_sub_f32 v2, v8, v1
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_dual_sub_f32 v1, v6, v4 :: v_dual_sub_f32 v0, v7, v5
+; GFX1100-SDAG-NEXT: global_store_b128 v9, v[0:3], s[4:5]
+; GFX1100-SDAG-NEXT: s_endpgm
+;
+; GFX1100-GISEL-LABEL: s_log2_v4f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x34
+; GFX1100-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s6, 0x800000, s0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s1
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s9, 0x800000, s2
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, s0, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s6, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s7, 0x800000, s3
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s8, s8, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v1, s1, s8
+; GFX1100-GISEL-NEXT: s_cselect_b32 s10, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s9, 0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s1, s1, 5
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s0, 0
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v2, s2, s1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s8, 0x42000000, 0
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v1, v1
+; GFX1100-GISEL-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX1100-GISEL-NEXT: s_lshl_b32 s0, s0, 5
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v2, v2
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v3, s3, s0
+; GFX1100-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1100-GISEL-NEXT: s_cmp_lg_u32 s7, 0
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v0, s6, v0
+; GFX1100-GISEL-NEXT: s_cselect_b32 s2, 0x42000000, 0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v3, v3
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_dual_subrev_f32 v1, s10, v1 :: v_dual_subrev_f32 v2, s8, v2
+; GFX1100-GISEL-NEXT: v_subrev_f32_e32 v3, s2, v3
+; GFX1100-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1100-GISEL-NEXT: global_store_b128 v4, v[0:3], s[0:1]
+; GFX1100-GISEL-NEXT: s_endpgm
;
; R600-LABEL: s_log2_v4f32:
; R600: ; %bb.0:
@@ -806,57 +1405,114 @@ define amdgpu_kernel void @s_log2_v4f32(ptr addrspace(1) %out, <4 x float> %in)
}
define float @v_log2_f32(float %in) {
-; SI-LABEL: v_log2_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32:
; R600: ; %bb.0:
@@ -872,58 +1528,115 @@ define float @v_log2_f32(float %in) {
}
define float @v_log2_fabs_f32(float %in) {
-; SI-LABEL: v_log2_fabs_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_fabs_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, |v0|, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_fabs_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_fabs_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_fabs_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
-; GFX1100-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_fabs_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_fabs_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_fabs_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_fabs_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fabs_f32:
; R600: ; %bb.0:
@@ -940,58 +1653,115 @@ define float @v_log2_fabs_f32(float %in) {
}
define float @v_log2_fneg_fabs_f32(float %in) {
-; SI-LABEL: v_log2_fneg_fabs_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x80800000
-; SI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, -|v0|, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_fneg_fabs_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, -|v0|, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_fneg_fabs_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x80800000
-; VI-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, -|v0|, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_fneg_fabs_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -|v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_fneg_fabs_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x80800000
-; GFX900-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, -|v0|, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_fneg_fabs_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_fneg_fabs_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_lt_f32_e64 s0, 0x80800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
-; GFX1100-NEXT: v_ldexp_f32 v0, -|v0|, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_fneg_fabs_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_fneg_fabs_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_fneg_fabs_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_fneg_fabs_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_lt_f32_e64 s0, 0x80800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -|v0|, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_fneg_fabs_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -|v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -|v0|, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fneg_fabs_f32:
; R600: ; %bb.0:
@@ -1009,57 +1779,114 @@ define float @v_log2_fneg_fabs_f32(float %in) {
}
define float @v_log2_fneg_f32(float %in) {
-; SI-LABEL: v_log2_fneg_f32:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x80800000
-; SI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, -v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_fneg_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, -v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_fneg_f32:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x80800000
-; VI-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, -v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_fneg_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, -v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_fneg_f32:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x80800000
-; GFX900-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, -v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_fneg_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, -v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_fneg_f32:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x80800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, -v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_fneg_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_fneg_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x80800000
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, -v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_fneg_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_fneg_f32:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0x80800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, -v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_fneg_f32:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, -v0
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, -v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_fneg_f32:
; R600: ; %bb.0:
@@ -1076,57 +1903,114 @@ define float @v_log2_fneg_f32(float %in) {
}
define float @v_log2_f32_fast(float %in) {
-; SI-LABEL: v_log2_f32_fast:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_fast:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_fast:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_fast:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_fast:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_fast:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_fast:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_fast:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_fast:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_fast:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_fast:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_fast:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_fast:
; R600: ; %bb.0:
@@ -1142,57 +2026,114 @@ define float @v_log2_f32_fast(float %in) {
}
define float @v_log2_f32_unsafe_math_attr(float %in) {
-; SI-LABEL: v_log2_f32_unsafe_math_attr:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_unsafe_math_attr:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_unsafe_math_attr:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_unsafe_math_attr:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_unsafe_math_attr:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_unsafe_math_attr:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_unsafe_math_attr:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_unsafe_math_attr:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_unsafe_math_attr:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_unsafe_math_attr:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_unsafe_math_attr:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_unsafe_math_attr:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_unsafe_math_attr:
; R600: ; %bb.0:
@@ -1208,57 +2149,114 @@ define float @v_log2_f32_unsafe_math_attr(float %in) {
}
define float @v_log2_f32_ninf(float %in) {
-; SI-LABEL: v_log2_f32_ninf:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_ninf:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_ninf:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_ninf:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_ninf:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_ninf:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_ninf:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_ninf:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_ninf:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_ninf:
; R600: ; %bb.0:
@@ -1274,57 +2272,114 @@ define float @v_log2_f32_ninf(float %in) {
}
define float @v_log2_f32_afn(float %in) {
-; SI-LABEL: v_log2_f32_afn:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_afn:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_afn:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_afn:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_afn:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_afn:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_afn:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_afn:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_afn:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_afn:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_afn:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_afn:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_afn:
; R600: ; %bb.0:
@@ -1366,57 +2421,114 @@ define float @v_log2_f32_afn_daz(float %in) #0 {
}
define float @v_log2_f32_afn_dynamic(float %in) #1 {
-; SI-LABEL: v_log2_f32_afn_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_afn_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_afn_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_afn_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_afn_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_afn_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_afn_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_afn_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_afn_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_afn_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_afn_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_afn_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_afn_dynamic:
; R600: ; %bb.0:
@@ -1432,58 +2544,115 @@ define float @v_log2_f32_afn_dynamic(float %in) #1 {
}
define float @v_fabs_log2_f32_afn(float %in) {
-; SI-LABEL: v_fabs_log2_f32_afn:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_fabs_log2_f32_afn:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e64 v0, |v0|, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_fabs_log2_f32_afn:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, |v0|, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_fabs_log2_f32_afn:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e64 v0, |v0|, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_fabs_log2_f32_afn:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_fabs_log2_f32_afn:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_fabs_log2_f32_afn:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
-; GFX1100-NEXT: v_ldexp_f32 v0, |v0|, v2
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_fabs_log2_f32_afn:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_fabs_log2_f32_afn:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_fabs_log2_f32_afn:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_fabs_log2_f32_afn:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, s0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, |v0|, v2
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_fabs_log2_f32_afn:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e64 s0, 0x800000, |v0|
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, |v0|, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, s0
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_fabs_log2_f32_afn:
; R600: ; %bb.0:
@@ -1526,57 +2695,114 @@ define float @v_log2_f32_daz(float %in) #0 {
}
define float @v_log2_f32_nnan(float %in) {
-; SI-LABEL: v_log2_f32_nnan:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_nnan:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_nnan:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_nnan:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_nnan:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_nnan:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_nnan:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_nnan:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_nnan:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_nnan:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_nnan:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_nnan:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_nnan:
; R600: ; %bb.0:
@@ -1618,57 +2844,114 @@ define float @v_log2_f32_nnan_daz(float %in) #0 {
}
define float @v_log2_f32_nnan_dynamic(float %in) #1 {
-; SI-LABEL: v_log2_f32_nnan_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_nnan_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_nnan_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_nnan_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_nnan_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_nnan_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_nnan_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_nnan_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_nnan_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_nnan_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_nnan_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_nnan_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_nnan_dynamic:
; R600: ; %bb.0:
@@ -1710,57 +2993,114 @@ define float @v_log2_f32_ninf_daz(float %in) #0 {
}
define float @v_log2_f32_ninf_dynamic(float %in) #1 {
-; SI-LABEL: v_log2_f32_ninf_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_ninf_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_ninf_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_ninf_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_ninf_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_ninf_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_ninf_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_ninf_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_ninf_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_ninf_dynamic:
; R600: ; %bb.0:
@@ -1776,57 +3116,114 @@ define float @v_log2_f32_ninf_dynamic(float %in) #1 {
}
define float @v_log2_f32_nnan_ninf(float %in) {
-; SI-LABEL: v_log2_f32_nnan_ninf:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_nnan_ninf:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_nnan_ninf:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_nnan_ninf:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_nnan_ninf:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_nnan_ninf:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_nnan_ninf:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_nnan_ninf:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_nnan_ninf:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_nnan_ninf:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_nnan_ninf:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_nnan_ninf:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_nnan_ninf:
; R600: ; %bb.0:
@@ -1868,57 +3265,114 @@ define float @v_log2_f32_nnan_ninf_daz(float %in) #0 {
}
define float @v_log2_f32_nnan_ninf_dynamic(float %in) #1 {
-; SI-LABEL: v_log2_f32_nnan_ninf_dynamic:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_nnan_ninf_dynamic:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_nnan_ninf_dynamic:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_nnan_ninf_dynamic:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_nnan_ninf_dynamic:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_nnan_ninf_dynamic:
; R600: ; %bb.0:
@@ -1960,57 +3414,114 @@ define float @v_log2_f32_fast_daz(float %in) #0 {
}
define float @v_log2_f32_dynamic_mode(float %in) #1 {
-; SI-LABEL: v_log2_f32_dynamic_mode:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: s_mov_b32 s4, 0x800000
-; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-NEXT: v_log_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-NEXT: s_setpc_b64 s[30:31]
+; SI-SDAG-LABEL: v_log2_f32_dynamic_mode:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
+; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_log2_f32_dynamic_mode:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0x800000
-; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-NEXT: v_log_f32_e32 v0, v0
-; VI-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_log2_f32_dynamic_mode:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_log2_f32_dynamic_mode:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-NEXT: v_log_f32_e32 v0, v0
-; GFX900-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_log2_f32_dynamic_mode:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1100-LABEL: v_log2_f32_dynamic_mode:
-; GFX1100: ; %bb.0:
-; GFX1100-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX1100-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-NEXT: s_setpc_b64 s[30:31]
+; VI-GISEL-LABEL: v_log2_f32_dynamic_mode:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_log2_f32_dynamic_mode:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
+; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
+; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_log2_f32_dynamic_mode:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
+; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-SDAG-LABEL: v_log2_f32_dynamic_mode:
+; GFX1100-SDAG: ; %bb.0:
+; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
+; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-SDAG-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX1100-GISEL-LABEL: v_log2_f32_dynamic_mode:
+; GFX1100-GISEL: ; %bb.0:
+; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
+; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
+; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
+; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GFX1100-GISEL-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
+; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_log2_f32_dynamic_mode:
; R600: ; %bb.0:
@@ -3782,7 +5293,5 @@ attributes #0 = { denormal_fpenv(float: ieee|preservesign) }
attributes #1 = { denormal_fpenv(float: dynamic|dynamic) }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1100-GISEL: {{.*}}
-; GFX1100-SDAG: {{.*}}
; GFX689-GISEL: {{.*}}
; GFX689-SDAG: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
index c0e41672ae50f..bdba8aae77a71 100644
--- a/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
+++ b/llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.03 < %s | FileCheck -check-prefixes=GCN-GISEL %s
; TODO: GlobalISel should avoid generating v_ldexp_f32.
define amdgpu_cs float @v_s_exp_f32(float inreg %src) {
@@ -105,32 +105,54 @@ define amdgpu_cs half @v_s_amdgcn_exp_f16(half inreg %src) {
}
define amdgpu_cs float @v_s_log_f32(float inreg %src) {
-; GFX12-LABEL: v_s_log_f32:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_cmp_lt_f32 s0, 0x800000
-; GFX12-NEXT: s_cselect_b32 s1, 0x4f800000, 1.0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: s_mul_f32 s0, s0, s1
-; GFX12-NEXT: s_cselect_b32 s1, 0x42000000, 0
-; GFX12-NEXT: v_s_log_f32 s0, s0
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: s_sub_f32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: v_s_log_f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_cmp_lt_f32 s0, 0x800000
+; GFX12-SDAG-NEXT: s_cselect_b32 s1, 0x4f800000, 1.0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_mul_f32 s0, s0, s1
+; GFX12-SDAG-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX12-SDAG-NEXT: v_s_log_f32 s0, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_sub_f32 s0, s0, s1
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: v_s_log_f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_cmp_lt_f32 s0, 0x800000
+; GFX12-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX12-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12-GISEL-NEXT: v_ldexp_f32 v0, s0, s2
+; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: v_s_log_f32 s0, s0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: s_sub_f32 s0, s0, s1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-GISEL-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: v_s_log_f32:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
-; GCN-GISEL-NEXT: s_and_b64 s[2:3], vcc, exec
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GCN-GISEL-NEXT: s_cselect_b32 s1, 32, 0
-; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GCN-GISEL-NEXT: v_ldexp_f32 v1, s0, v1
-; GCN-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
+; GCN-GISEL-NEXT: s_cmp_lg_u64 vcc, 0
+; GCN-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GCN-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GCN-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GCN-GISEL-NEXT: v_ldexp_f32 v0, s0, v0
+; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GCN-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GCN-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
; GCN-GISEL-NEXT: ; return to shader part epilog
%result = call float @llvm.log2.f32(float %src)
ret float %result
@@ -566,34 +588,58 @@ define amdgpu_cs half @v_amdgcn_sqrt_f16(half inreg %src) {
}
define amdgpu_cs float @srcmods_abs_f32(float inreg %src) {
-; GFX12-LABEL: srcmods_abs_f32:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_bitset0_b32 s0, 31
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_cmp_lt_f32 s0, 0x800000
-; GFX12-NEXT: s_cselect_b32 s1, 0x4f800000, 1.0
-; GFX12-NEXT: s_mul_f32 s0, s0, s1
-; GFX12-NEXT: s_cselect_b32 s1, 0x42000000, 0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
-; GFX12-NEXT: v_s_log_f32 s0, s0
-; GFX12-NEXT: s_sub_f32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: srcmods_abs_f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_bitset0_b32 s0, 31
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX12-SDAG-NEXT: s_cmp_lt_f32 s0, 0x800000
+; GFX12-SDAG-NEXT: s_cselect_b32 s1, 0x4f800000, 1.0
+; GFX12-SDAG-NEXT: s_mul_f32 s0, s0, s1
+; GFX12-SDAG-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(TRANS32_DEP_1)
+; GFX12-SDAG-NEXT: v_s_log_f32 s0, s0
+; GFX12-SDAG-NEXT: s_sub_f32 s0, s0, s1
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: srcmods_abs_f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_and_b32 s1, s0, 0x7fffffff
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_cmp_lt_f32 s1, 0x800000
+; GFX12-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX12-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12-GISEL-NEXT: v_ldexp_f32 v0, |s0|, s2
+; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: v_s_log_f32 s0, s0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: s_sub_f32 s0, s0, s1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-GISEL-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: srcmods_abs_f32:
; GCN-GISEL: ; %bb.0:
; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
-; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |s0|, v0
-; GCN-GISEL-NEXT: s_and_b64 s[2:3], vcc, exec
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GCN-GISEL-NEXT: s_cselect_b32 s1, 32, 0
-; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GCN-GISEL-NEXT: v_ldexp_f32 v1, |s0|, v1
-; GCN-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
+; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], |s0|, v0
+; GCN-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GCN-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GCN-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GCN-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GCN-GISEL-NEXT: v_ldexp_f32 v0, |s0|, v0
+; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GCN-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GCN-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
; GCN-GISEL-NEXT: ; return to shader part epilog
%abs = call float @llvm.fabs.f32(float %src)
%result = call float @llvm.log2.f32(float %abs)
@@ -601,33 +647,57 @@ define amdgpu_cs float @srcmods_abs_f32(float inreg %src) {
}
define amdgpu_cs float @srcmods_neg_f32(float inreg %src) {
-; GFX12-LABEL: srcmods_neg_f32:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_xor_b32 s1, s0, 0x80000000
-; GFX12-NEXT: s_cmp_gt_f32 s0, 0x80800000
-; GFX12-NEXT: s_cselect_b32 s0, 0x4f800000, 1.0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: s_mul_f32 s0, s1, s0
-; GFX12-NEXT: s_cselect_b32 s1, 0x42000000, 0
-; GFX12-NEXT: v_s_log_f32 s0, s0
-; GFX12-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
-; GFX12-NEXT: s_sub_f32 s0, s0, s1
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX12-SDAG-LABEL: srcmods_neg_f32:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_xor_b32 s1, s0, 0x80000000
+; GFX12-SDAG-NEXT: s_cmp_gt_f32 s0, 0x80800000
+; GFX12-SDAG-NEXT: s_cselect_b32 s0, 0x4f800000, 1.0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_mul_f32 s0, s1, s0
+; GFX12-SDAG-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX12-SDAG-NEXT: v_s_log_f32 s0, s0
+; GFX12-SDAG-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-SDAG-NEXT: s_sub_f32 s0, s0, s1
+; GFX12-SDAG-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-SDAG-NEXT: ; return to shader part epilog
+;
+; GFX12-GISEL-LABEL: srcmods_neg_f32:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_xor_b32 s1, s0, 0x80000000
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-GISEL-NEXT: s_cmp_lt_f32 s1, 0x800000
+; GFX12-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX12-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GFX12-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GFX12-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GFX12-GISEL-NEXT: v_ldexp_f32 v0, -s0, s2
+; GFX12-GISEL-NEXT: s_cselect_b32 s1, 0x42000000, 0
+; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-GISEL-NEXT: v_s_log_f32 s0, s0
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
+; GFX12-GISEL-NEXT: s_sub_f32 s0, s0, s1
+; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-GISEL-NEXT: ; return to shader part epilog
;
; GCN-GISEL-LABEL: srcmods_neg_f32:
; GCN-GISEL: ; %bb.0:
-; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x80800000
-; GCN-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s0, v0
-; GCN-GISEL-NEXT: s_and_b64 s[2:3], vcc, exec
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GCN-GISEL-NEXT: s_cselect_b32 s1, 32, 0
-; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-GISEL-NEXT: v_mov_b32_e32 v1, s1
-; GCN-GISEL-NEXT: v_ldexp_f32 v1, -s0, v1
-; GCN-GISEL-NEXT: v_log_f32_e32 v1, v1
-; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
+; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0x800000
+; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 s[2:3], -s0, v0
+; GCN-GISEL-NEXT: s_cmp_lg_u64 s[2:3], 0
+; GCN-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GCN-GISEL-NEXT: s_cselect_b32 s1, 1, 0
+; GCN-GISEL-NEXT: s_lshl_b32 s2, s2, 5
+; GCN-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GCN-GISEL-NEXT: v_ldexp_f32 v0, -s0, v0
+; GCN-GISEL-NEXT: v_log_f32_e32 v0, v0
+; GCN-GISEL-NEXT: s_cmp_lg_u32 s1, 0
+; GCN-GISEL-NEXT: s_cselect_b32 s0, 0x42000000, 0
+; GCN-GISEL-NEXT: v_subrev_f32_e32 v0, s0, v0
; GCN-GISEL-NEXT: ; return to shader part epilog
%neg = fneg float %src
%result = call float @llvm.log2.f32(float %neg)
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