[llvm-branch-commits] [llvm] release/23.x: [X86] Fix assertion failure for tail call on i686+pic (#210302) (PR #210318)
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Fri Jul 17 05:45:08 PDT 2026
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<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: llvmbot
<details>
<summary>Changes</summary>
Backport 23b0281d75a4320a4e6e3d837edf94911d98d252
Requested by: @<!-- -->nikic
---
Full diff: https://github.com/llvm/llvm-project/pull/210318.diff
2 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelDAGToDAG.cpp (+2-1)
- (added) llvm/test/CodeGen/X86/tailcall-i686-pic.ll (+14)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index b794567f6a047..9a0045367a8bf 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -3561,7 +3561,8 @@ bool X86DAGToDAGISel::checkTCRetEnoughRegs(SDNode *N) const {
LoadGPRs -= 2; // Base is fixed index off ESP; no regs needed.
} else if (BasePtr.getOpcode() == X86ISD::Wrapper &&
isa<GlobalAddressSDNode>(BasePtr->getOperand(0))) {
- assert(!getTargetMachine().isPositionIndependent());
+ if (getTargetMachine().isPositionIndependent())
+ return false;
LoadGPRs -= 1; // Base is a global (immediate since this is non-PIC), no
// reg needed.
}
diff --git a/llvm/test/CodeGen/X86/tailcall-i686-pic.ll b/llvm/test/CodeGen/X86/tailcall-i686-pic.ll
new file mode 100644
index 0000000000000..b8a4207451e8a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/tailcall-i686-pic.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=i686-pc-windows-msvc -relocation-model=pic < %s | FileCheck %s
+
+ at fnptr = external global ptr
+
+define void @test() {
+; CHECK-LABEL: test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl _fnptr, %eax
+; CHECK-NEXT: jmpl *%eax # TAILCALL
+ %p = load ptr, ptr @fnptr
+ tail call void %p()
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/210318
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