[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for applyD16Load (PR #210103)

[Petar Avramovic via llvm-branch-commits]

https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/210103

>From b46e6de853a7658094820305ae89cbeb102a3fed Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Thu, 16 Jul 2026 18:19:55 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Fix type mismatch in regbank combiner for
 applyD16Load

---
 llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp | 15 ++++++++++++++-
 llvm/test/CodeGen/AMDGPU/global-saddr-load.ll    |  4 ++--
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
index f9d8a09e29b0d..baf83e7f7762a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp
@@ -566,9 +566,22 @@ bool AMDGPURegBankCombinerImpl::matchMinMaxToMinMax3(
 bool AMDGPURegBankCombinerImpl::applyD16Load(
     unsigned D16Opc, MachineInstr &DstMI, MachineInstr *SmallLoad,
     Register SrcReg32ToOverwriteD16) const {
-  B.buildInstr(D16Opc, {DstMI.getOperand(0).getReg()},
+  Register DstReg = DstMI.getOperand(0).getReg();
+  LLT SrcTy = MRI.getType(SrcReg32ToOverwriteD16);
+
+  // Dst and Src for D16 load need to have same type.
+  Register D16Dst =
+      SrcTy == MRI.getType(DstReg)
+          ? DstReg
+          : MRI.createVirtualRegister({MRI.getRegBank(DstReg), SrcTy});
+
+  B.buildInstr(D16Opc, {D16Dst},
                {SmallLoad->getOperand(1).getReg(), SrcReg32ToOverwriteD16})
       .setMemRefs(SmallLoad->memoperands());
+
+  if (D16Dst != DstReg)
+    B.buildBitcast(DstReg, D16Dst);
+
   DstMI.eraseFromParent();
   return true;
 }
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
index 3d4b8796b1902..a1130abf89a7a 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
@@ -5,8 +5,8 @@
 ; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 ; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-TRUE16 %s
 ; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG,GFX12-SDAG-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -mattr=+wavefrontsize64 < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL,GFX12-GISEL-FAKE16 %s
 
 ; Test using saddr addressing mode of global_*load_* flat instructions.