[llvm-branch-commits] [llvm] GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering (PR #210099)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jul 16 09:34:53 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
---
Patch is 293.15 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/210099.diff
6 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+47-47)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll (+251-419)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir (+238-239)
- (modified) llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll (+1228-1399)
- (modified) llvm/test/CodeGen/AMDGPU/fptrunc.ll (+359-238)
- (modified) llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll (+176-91)
``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a911697ba73f2..cee544de940dd 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -8799,7 +8799,7 @@ LegalizerHelper::lowerFPExtAndTruncMem(MachineInstr &MI) {
LegalizerHelper::LegalizeResult
LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
const LLT S1 = LLT::scalar(1);
- const LLT S32 = LLT::scalar(32);
+ const LLT I32 = LLT::integer(32);
auto [Dst, Src] = MI.getFirst2Regs();
assert(MRI.getType(Dst).getScalarType() == LLT::float16() &&
@@ -8810,7 +8810,7 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
if (MI.getFlag(MachineInstr::FmAfn)) {
unsigned Flags = MI.getFlags();
- auto Src32 = MIRBuilder.buildFPTrunc(S32, Src, Flags);
+ auto Src32 = MIRBuilder.buildFPTrunc(LLT::float32(), Src, Flags);
MIRBuilder.buildFPTrunc(Dst, Src32, Flags);
MI.eraseFromParent();
return Legalized;
@@ -8820,91 +8820,91 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
const unsigned ExpBiasf64 = 1023;
const unsigned ExpBiasf16 = 15;
- auto Unmerge = MIRBuilder.buildUnmerge(S32, Src);
+ auto Unmerge = MIRBuilder.buildUnmerge(I32, Src);
Register U = Unmerge.getReg(0);
Register UH = Unmerge.getReg(1);
- auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20));
- E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));
+ auto E = MIRBuilder.buildLShr(I32, UH, MIRBuilder.buildConstant(I32, 20));
+ E = MIRBuilder.buildAnd(I32, E, MIRBuilder.buildConstant(I32, ExpMask));
// Subtract the fp64 exponent bias (1023) to get the real exponent and
// add the f16 bias (15) to get the biased exponent for the f16 format.
E = MIRBuilder.buildAdd(
- S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16));
+ I32, E, MIRBuilder.buildConstant(I32, -ExpBiasf64 + ExpBiasf16));
- auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8));
- M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));
+ auto M = MIRBuilder.buildLShr(I32, UH, MIRBuilder.buildConstant(I32, 8));
+ M = MIRBuilder.buildAnd(I32, M, MIRBuilder.buildConstant(I32, 0xffe));
- auto MaskedSig = MIRBuilder.buildAnd(S32, UH,
- MIRBuilder.buildConstant(S32, 0x1ff));
- MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U);
+ auto MaskedSig = MIRBuilder.buildAnd(I32, UH,
+ MIRBuilder.buildConstant(I32, 0x1ff));
+ MaskedSig = MIRBuilder.buildOr(I32, MaskedSig, U);
- auto Zero = MIRBuilder.buildConstant(S32, 0);
+ auto Zero = MIRBuilder.buildConstant(I32, 0);
auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero);
- auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0);
- M = MIRBuilder.buildOr(S32, M, Lo40Set);
+ auto Lo40Set = MIRBuilder.buildZExt(I32, SigCmpNE0);
+ M = MIRBuilder.buildOr(I32, M, Lo40Set);
// (M != 0 ? 0x0200 : 0) | 0x7c00;
- auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200);
+ auto Bits0x200 = MIRBuilder.buildConstant(I32, 0x0200);
auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero);
- auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero);
+ auto SelectCC = MIRBuilder.buildSelect(I32, CmpM_NE0, Bits0x200, Zero);
- auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00);
- auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00);
+ auto Bits0x7c00 = MIRBuilder.buildConstant(I32, 0x7c00);
+ auto I = MIRBuilder.buildOr(I32, SelectCC, Bits0x7c00);
// N = M | (E << 12);
- auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12));
- auto N = MIRBuilder.buildOr(S32, M, EShl12);
+ auto EShl12 = MIRBuilder.buildShl(I32, E, MIRBuilder.buildConstant(I32, 12));
+ auto N = MIRBuilder.buildOr(I32, M, EShl12);
// B = clamp(1-E, 0, 13);
- auto One = MIRBuilder.buildConstant(S32, 1);
- auto OneSubExp = MIRBuilder.buildSub(S32, One, E);
- auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero);
- B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13));
+ auto One = MIRBuilder.buildConstant(I32, 1);
+ auto OneSubExp = MIRBuilder.buildSub(I32, One, E);
+ auto B = MIRBuilder.buildSMax(I32, OneSubExp, Zero);
+ B = MIRBuilder.buildSMin(I32, B, MIRBuilder.buildConstant(I32, 13));
- auto SigSetHigh = MIRBuilder.buildOr(S32, M,
- MIRBuilder.buildConstant(S32, 0x1000));
+ auto SigSetHigh = MIRBuilder.buildOr(I32, M,
+ MIRBuilder.buildConstant(I32, 0x1000));
- auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B);
- auto D0 = MIRBuilder.buildShl(S32, D, B);
+ auto D = MIRBuilder.buildLShr(I32, SigSetHigh, B);
+ auto D0 = MIRBuilder.buildShl(I32, D, B);
auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1,
D0, SigSetHigh);
- auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh);
- D = MIRBuilder.buildOr(S32, D, D1);
+ auto D1 = MIRBuilder.buildZExt(I32, D0_NE_SigSetHigh);
+ D = MIRBuilder.buildOr(I32, D, D1);
auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One);
- auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N);
+ auto V = MIRBuilder.buildSelect(I32, CmpELtOne, D, N);
- auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));
- V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2));
+ auto VLow3 = MIRBuilder.buildAnd(I32, V, MIRBuilder.buildConstant(I32, 7));
+ V = MIRBuilder.buildLShr(I32, V, MIRBuilder.buildConstant(I32, 2));
auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3,
- MIRBuilder.buildConstant(S32, 3));
- auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3);
+ MIRBuilder.buildConstant(I32, 3));
+ auto V0 = MIRBuilder.buildZExt(I32, VLow3Eq3);
auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3,
- MIRBuilder.buildConstant(S32, 5));
- auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5);
+ MIRBuilder.buildConstant(I32, 5));
+ auto V1 = MIRBuilder.buildZExt(I32, VLow3Gt5);
- V1 = MIRBuilder.buildOr(S32, V0, V1);
- V = MIRBuilder.buildAdd(S32, V, V1);
+ V1 = MIRBuilder.buildOr(I32, V0, V1);
+ V = MIRBuilder.buildAdd(I32, V, V1);
auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1,
- E, MIRBuilder.buildConstant(S32, 30));
- V = MIRBuilder.buildSelect(S32, CmpEGt30,
- MIRBuilder.buildConstant(S32, 0x7c00), V);
+ E, MIRBuilder.buildConstant(I32, 30));
+ V = MIRBuilder.buildSelect(I32, CmpEGt30,
+ MIRBuilder.buildConstant(I32, 0x7c00), V);
auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1,
- E, MIRBuilder.buildConstant(S32, 1039));
- V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V);
+ E, MIRBuilder.buildConstant(I32, 1039));
+ V = MIRBuilder.buildSelect(I32, CmpEGt1039, I, V);
// Extract the sign bit.
- auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16));
- Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));
+ auto Sign = MIRBuilder.buildLShr(I32, UH, MIRBuilder.buildConstant(I32, 16));
+ Sign = MIRBuilder.buildAnd(I32, Sign, MIRBuilder.buildConstant(I32, 0x8000));
// Insert the sign bit
- V = MIRBuilder.buildOr(S32, Sign, V);
+ V = MIRBuilder.buildOr(I32, Sign, V);
MIRBuilder.buildTrunc(Dst, V);
MI.eraseFromParent();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
index ff53b3dfdeb5e..69aa974f6aebc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.50-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.50-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.50-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.50-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
define amdgpu_ps half @fptrunc_f32_to_f16_uniform(float inreg %a) {
; GFX11-FAKE16-LABEL: fptrunc_f32_to_f16_uniform:
@@ -127,49 +127,48 @@ define amdgpu_ps float @fptrunc_f64_to_f32_div(double %a) {
define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX11-LABEL: fptrunc_f64_to_f16_uniform:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s2, s1, 0x1ff
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s2, s0
-; GFX11-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-NEXT: s_bfe_u32 s2, s1, 0xb0014
-; GFX11-NEXT: s_sub_i32 s3, 0x3f1, s2
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_med3_i32 v0, s3, 0, 13
; GFX11-NEXT: s_lshr_b32 s3, s1, 8
+; GFX11-NEXT: s_and_b32 s4, s1, 0x1ff
+; GFX11-NEXT: s_addk_i32 s2, 0xfc10
; GFX11-NEXT: s_and_b32 s3, s3, 0xffe
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readfirstlane_b32 s4, v0
+; GFX11-NEXT: s_or_b32 s0, s4, s0
+; GFX11-NEXT: s_cselect_b32 s0, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s0, s3, s0
-; GFX11-NEXT: s_or_b32 s3, s0, 0x1000
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_lshr_b32 s5, s3, s4
-; GFX11-NEXT: s_lshl_b32 s4, s5, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_cmp_lg_u32 s4, s3
; GFX11-NEXT: s_cselect_b32 s3, 1, 0
-; GFX11-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-NEXT: s_or_b32 s3, s5, s3
-; GFX11-NEXT: s_lshl_b32 s4, s2, 12
-; GFX11-NEXT: s_or_b32 s4, s0, s4
+; GFX11-NEXT: s_sub_i32 s4, 1, s2
+; GFX11-NEXT: s_or_b32 s5, s0, 0x1000
+; GFX11-NEXT: s_max_i32 s4, s4, 0
+; GFX11-NEXT: s_lshl_b32 s3, s3, 9
+; GFX11-NEXT: s_min_i32 s4, s4, 13
+; GFX11-NEXT: s_lshl_b32 s7, s2, 12
+; GFX11-NEXT: s_lshr_b32 s6, s5, s4
+; GFX11-NEXT: s_or_b32 s3, s3, 0x7c00
+; GFX11-NEXT: s_lshl_b32 s4, s6, s4
+; GFX11-NEXT: s_or_b32 s0, s0, s7
+; GFX11-NEXT: s_cmp_lg_u32 s4, s5
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s4, s6, s4
; GFX11-NEXT: s_cmp_lt_i32 s2, 1
-; GFX11-NEXT: s_cselect_b32 s3, s3, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_and_b32 s4, s3, 7
-; GFX11-NEXT: s_cmp_gt_i32 s4, 5
-; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_cselect_b32 s0, s4, s0
+; GFX11-NEXT: s_and_b32 s4, s0, 7
+; GFX11-NEXT: s_lshr_b32 s0, s0, 2
; GFX11-NEXT: s_cmp_eq_u32 s4, 3
+; GFX11-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-NEXT: s_cmp_gt_i32 s4, 5
+; GFX11-NEXT: s_cselect_b32 s4, 1, 0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s4, s5, s4
+; GFX11-NEXT: s_cmp_lg_u32 s4, 0
; GFX11-NEXT: s_cselect_b32 s4, 1, 0
-; GFX11-NEXT: s_lshr_b32 s3, s3, 2
-; GFX11-NEXT: s_or_b32 s4, s4, s5
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: s_add_i32 s3, s3, s4
-; GFX11-NEXT: s_cmp_lt_i32 s2, 31
-; GFX11-NEXT: s_movk_i32 s4, 0x7e00
-; GFX11-NEXT: s_cselect_b32 s3, s3, 0x7c00
-; GFX11-NEXT: s_cmp_lg_u32 s0, 0
-; GFX11-NEXT: s_cselect_b32 s0, s4, 0x7c00
+; GFX11-NEXT: s_add_i32 s0, s0, s4
+; GFX11-NEXT: s_cmp_gt_i32 s2, 30
+; GFX11-NEXT: s_cselect_b32 s0, 0x7c00, s0
; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x40f
-; GFX11-NEXT: s_cselect_b32 s0, s0, s3
+; GFX11-NEXT: s_cselect_b32 s0, s3, s0
; GFX11-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s1, s1, 0x8000
@@ -180,57 +179,48 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
;
; GFX12-LABEL: fptrunc_f64_to_f16_uniform:
; GFX12: ; %bb.0:
-; GFX12-NEXT: s_and_b32 s2, s1, 0x1ff
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_or_b32 s0, s2, s0
-; GFX12-NEXT: s_cselect_b32 s0, 1, 0
; GFX12-NEXT: s_bfe_u32 s2, s1, 0xb0014
-; GFX12-NEXT: s_sub_co_i32 s3, 0x3f1, s2
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_med3_i32 v0, s3, 0, 13
; GFX12-NEXT: s_lshr_b32 s3, s1, 8
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_and_b32 s4, s1, 0x1ff
+; GFX12-NEXT: s_addk_co_i32 s2, 0xfc10
; GFX12-NEXT: s_and_b32 s3, s3, 0xffe
-; GFX12-NEXT: v_readfirstlane_b32 s4, v0
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_or_b32 s0, s3, s0
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_or_b32 s3, s0, 0x1000
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_lshr_b32 s5, s3, s4
-; GFX12-NEXT: s_lshl_b32 s4, s5, s4
+; GFX12-NEXT: s_or_b32 s0, s4, s0
+; GFX12-NEXT: s_cselect_b32 s0, 1, 0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cmp_lg_u32 s4, s3
+; GFX12-NEXT: s_or_b32 s0, s3, s0
; GFX12-NEXT: s_cselect_b32 s3, 1, 0
-; GFX12-NEXT: s_addk_co_i32 s2, 0xfc10
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_or_b32 s3, s5, s3
-; GFX12-NEXT: s_lshl_b32 s4, s2, 12
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_or_b32 s4, s0, s4
+; GFX12-NEXT: s_sub_co_i32 s4, 1, s2
+; GFX12-NEXT: s_or_b32 s5, s0, 0x1000
+; GFX12-NEXT: s_max_i32 s4, s4, 0
+; GFX12-NEXT: s_lshl_b32 s3, s3, 9
+; GFX12-NEXT: s_min_i32 s4, s4, 13
+; GFX12-NEXT: s_lshl_b32 s7, s2, 12
+; GFX12-NEXT: s_lshr_b32 s6, s5, s4
+; GFX12-NEXT: s_or_b32 s3, s3, 0x7c00
+; GFX12-NEXT: s_lshl_b32 s4, s6, s4
+; GFX12-NEXT: s_or_b32 s0, s0, s7
+; GFX12-NEXT: s_cmp_lg_u32 s4, s5
+; GFX12-NEXT: s_cselect_b32 s4, 1, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_or_b32 s4, s6, s4
; GFX12-NEXT: s_cmp_lt_i32 s2, 1
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_cselect_b32 s3, s3, s4
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_and_b32 s4, s3, 7
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cmp_gt_i32 s4, 5
-; GFX12-NEXT: s_cselect_b32 s5, 1, 0
+; GFX12-NEXT: s_cselect_b32 s0, s4, s0
+; GFX12-NEXT: s_and_b32 s4, s0, 7
+; GFX12-NEXT: s_lshr_b32 s0, s0, 2
; GFX12-NEXT: s_cmp_eq_u32 s4, 3
+; GFX12-NEXT: s_cselect_b32 s5, 1, 0
+; GFX12-NEXT: s_cmp_gt_i32 s4, 5
; GFX12-NEXT: s_cselect_b32 s4, 1, 0
-; GFX12-NEXT: s_lshr_b32 s3, s3, 2
-; GFX12-NEXT: s_or_b32 s4, s4, s5
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_add_co_i32 s3, s3, s4
-; GFX12-NEXT: s_cmp_lt_i32 s2, 31
-; GFX12-NEXT: s_movk_i32 s4, 0x7e00
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_cselect_b32 s3, s3, 0x7c00
-; GFX12-NEXT: s_cmp_lg_u32 s0, 0
-; GFX12-NEXT: s_cselect_b32 s0, s4, 0x7c00
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_or_b32 s4, s5, s4
+; GFX12-NEXT: s_cmp_lg_u32 s4, 0
+; GFX12-NEXT: s_cselect_b32 s4, 1, 0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: s_add_co_i32 s0, s0, s4
+; GFX12-NEXT: s_cmp_gt_i32 s2, 30
+; GFX12-NEXT: s_cselect_b32 s0, 0x7c00, s0
; GFX12-NEXT: s_cmp_eq_u32 s2, 0x40f
-; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: s_cselect_b32 s0, s0, s3
+; GFX12-NEXT: s_cselect_b32 s0, s3, s0
; GFX12-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: s_and_b32 s1, s1, 0x8000
@@ -244,49 +234,48 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
; GFX1250-NEXT: global_wb
; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s2, s1, 0x1ff
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s0, s2, s0
-; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
; GFX1250-NEXT: s_bfe_u32 s2, s1, 0xb0014
-; GFX1250-NEXT: s_sub_co_i32 s3, 0x3f1, s2
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: v_med3_i32 v0, s3, 0, 13
; GFX1250-NEXT: s_lshr_b32 s3, s1, 8
+; GFX1250-NEXT: s_and_b32 s4, s1, 0x1ff
+; GFX1250-NEXT: s_addk_co_i32 s2, 0xfc10
; GFX1250-NEXT: s_and_b32 s3, s3, 0xffe
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1250-NEXT: s_or_b32 s0, s4, s0
+; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: s_or_b32 s0, s3, s0
-; GFX1250-NEXT: s_or_b32 s3, s0, 0x1000
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_lshr_b32 s5, s3, s4
-; GFX1250-NEXT: s_lshl_b32 s4, s5, s4
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_cmp_lg_u32 s4, s3
; GFX1250-NEXT: s_cselect_b32 s3, 1, 0
-; GFX1250-NEXT: s_addk_co_i32 s2, 0xfc10
-; GFX1250-NEXT: s_or_b32 s3, s5, s3
-; GFX1250-NEXT: s_lshl_b32 s4, s2, 12
-; GFX1250-NEXT: s_or_b32 s4, s0, s4
+; GFX1250-NEXT: s_sub_co_i32 s4, 1, s2
+; GFX1250-NEXT: s_or_b32 s5, s0, 0x1000
+; GFX1250-NEXT: s_max_i32 s4, s4, 0
+; GFX1250-NEXT: s_lshl_b32 s3, s3, 9
+; GFX1250-NEXT: s_min_i32 s4, s4, 13
+; GFX1250-NEXT: s_lshl_b32 s7, s2, 12
+; GFX1250-NEXT: s_lshr_b32 s6, s5, s4
+; GFX1250-NEXT: s_or_b32 s3, s3, 0x7c00
+; GFX1250-NEXT: s_lshl_b32 s4, s6, s4
+; GFX1250-NEXT: s_or_b32 s0, s0, s7
+; GFX1250-NEXT: s_cmp_lg_u32 s4, s5
+; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/210099
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