[llvm-branch-commits] [llvm] GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering (PR #210099)

Thu Jul 16 09:31:36 PDT 2026

https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/210099

None

>From 5b85ddc6386b40832f6d37ea74d288e49126c655 Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Thu, 16 Jul 2026 18:13:29 +0200
Subject: [PATCH] GlobalISel: Use extended LLTs in f64 to f16 fptrunc lowering

---
 .../CodeGen/GlobalISel/LegalizerHelper.cpp    |   94 +-
 .../test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll |  670 ++---
 .../AMDGPU/GlobalISel/legalize-fptrunc.mir    |  477 ++-
 llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll       | 2627 ++++++++---------
 llvm/test/CodeGen/AMDGPU/fptrunc.ll           |  597 ++--
 .../AMDGPU/fptrunc.v2f16.no.fast.math.ll      |  267 +-
 6 files changed, 2299 insertions(+), 2433 deletions(-)

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a911697ba73f2..cee544de940dd 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -8799,7 +8799,7 @@ LegalizerHelper::lowerFPExtAndTruncMem(MachineInstr &MI) {
 LegalizerHelper::LegalizeResult
 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
   const LLT S1 = LLT::scalar(1);
-  const LLT S32 = LLT::scalar(32);
+  const LLT I32 = LLT::integer(32);
 
   auto [Dst, Src] = MI.getFirst2Regs();
   assert(MRI.getType(Dst).getScalarType() == LLT::float16() &&
@@ -8810,7 +8810,7 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
 
   if (MI.getFlag(MachineInstr::FmAfn)) {
     unsigned Flags = MI.getFlags();
-    auto Src32 = MIRBuilder.buildFPTrunc(S32, Src, Flags);
+    auto Src32 = MIRBuilder.buildFPTrunc(LLT::float32(), Src, Flags);
     MIRBuilder.buildFPTrunc(Dst, Src32, Flags);
     MI.eraseFromParent();
     return Legalized;
@@ -8820,91 +8820,91 @@ LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
   const unsigned ExpBiasf64 = 1023;
   const unsigned ExpBiasf16 = 15;
 
-  auto Unmerge = MIRBuilder.buildUnmerge(S32, Src);
+  auto Unmerge = MIRBuilder.buildUnmerge(I32, Src);
   Register U = Unmerge.getReg(0);
   Register UH = Unmerge.getReg(1);
 
-  auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20));
-  E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));
+  auto E = MIRBuilder.buildLShr(I32, UH, MIRBuilder.buildConstant(I32, 20));
+  E = MIRBuilder.buildAnd(I32, E, MIRBuilder.buildConstant(I32, ExpMask));
 
   // Subtract the fp64 exponent bias (1023) to get the real exponent and
   // add the f16 bias (15) to get the biased exponent for the f16 format.
   E = MIRBuilder.buildAdd(
-    S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16));
+    I32, E, MIRBuilder.buildConstant(I32, -ExpBiasf64 + ExpBiasf16));
 
-  auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8));
-  M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));
+  auto M = MIRBuilder.buildLShr(I32, UH, MIRBuilder.buildConstant(I32, 8));
+  M = MIRBuilder.buildAnd(I32, M, MIRBuilder.buildConstant(I32, 0xffe));
 
-  auto MaskedSig = MIRBuilder.buildAnd(S32, UH,
-                                       MIRBuilder.buildConstant(S32, 0x1ff));
-  MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U);
+  auto MaskedSig = MIRBuilder.buildAnd(I32, UH,
+                                       MIRBuilder.buildConstant(I32, 0x1ff));
+  MaskedSig = MIRBuilder.buildOr(I32, MaskedSig, U);
 
-  auto Zero = MIRBuilder.buildConstant(S32, 0);
+  auto Zero = MIRBuilder.buildConstant(I32, 0);
   auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero);
-  auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0);
-  M = MIRBuilder.buildOr(S32, M, Lo40Set);
+  auto Lo40Set = MIRBuilder.buildZExt(I32, SigCmpNE0);
+  M = MIRBuilder.buildOr(I32, M, Lo40Set);
 
   // (M != 0 ? 0x0200 : 0) | 0x7c00;
-  auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200);
+  auto Bits0x200 = MIRBuilder.buildConstant(I32, 0x0200);
   auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero);
-  auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero);
+  auto SelectCC = MIRBuilder.buildSelect(I32, CmpM_NE0, Bits0x200, Zero);
 
-  auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00);
-  auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00);
+  auto Bits0x7c00 = MIRBuilder.buildConstant(I32, 0x7c00);
+  auto I = MIRBuilder.buildOr(I32, SelectCC, Bits0x7c00);
 
   // N = M | (E << 12);
-  auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12));
-  auto N = MIRBuilder.buildOr(S32, M, EShl12);
+  auto EShl12 = MIRBuilder.buildShl(I32, E, MIRBuilder.buildConstant(I32, 12));
+  auto N = MIRBuilder.buildOr(I32, M, EShl12);
 
   // B = clamp(1-E, 0, 13);
-  auto One = MIRBuilder.buildConstant(S32, 1);
-  auto OneSubExp = MIRBuilder.buildSub(S32, One, E);
-  auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero);
-  B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13));
+  auto One = MIRBuilder.buildConstant(I32, 1);
+  auto OneSubExp = MIRBuilder.buildSub(I32, One, E);
+  auto B = MIRBuilder.buildSMax(I32, OneSubExp, Zero);
+  B = MIRBuilder.buildSMin(I32, B, MIRBuilder.buildConstant(I32, 13));
 
-  auto SigSetHigh = MIRBuilder.buildOr(S32, M,
-                                       MIRBuilder.buildConstant(S32, 0x1000));
+  auto SigSetHigh = MIRBuilder.buildOr(I32, M,
+                                       MIRBuilder.buildConstant(I32, 0x1000));
 
-  auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B);
-  auto D0 = MIRBuilder.buildShl(S32, D, B);
+  auto D = MIRBuilder.buildLShr(I32, SigSetHigh, B);
+  auto D0 = MIRBuilder.buildShl(I32, D, B);
 
   auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1,
                                              D0, SigSetHigh);
-  auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh);
-  D = MIRBuilder.buildOr(S32, D, D1);
+  auto D1 = MIRBuilder.buildZExt(I32, D0_NE_SigSetHigh);
+  D = MIRBuilder.buildOr(I32, D, D1);
 
   auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One);
-  auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N);
+  auto V = MIRBuilder.buildSelect(I32, CmpELtOne, D, N);
 
-  auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));
-  V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2));
+  auto VLow3 = MIRBuilder.buildAnd(I32, V, MIRBuilder.buildConstant(I32, 7));
+  V = MIRBuilder.buildLShr(I32, V, MIRBuilder.buildConstant(I32, 2));
 
   auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3,
-                                       MIRBuilder.buildConstant(S32, 3));
-  auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3);
+                                       MIRBuilder.buildConstant(I32, 3));
+  auto V0 = MIRBuilder.buildZExt(I32, VLow3Eq3);
 
   auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3,
-                                       MIRBuilder.buildConstant(S32, 5));
-  auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5);
+                                       MIRBuilder.buildConstant(I32, 5));
+  auto V1 = MIRBuilder.buildZExt(I32, VLow3Gt5);
 
-  V1 = MIRBuilder.buildOr(S32, V0, V1);
-  V = MIRBuilder.buildAdd(S32, V, V1);
+  V1 = MIRBuilder.buildOr(I32, V0, V1);
+  V = MIRBuilder.buildAdd(I32, V, V1);
 
   auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,  S1,
-                                       E, MIRBuilder.buildConstant(S32, 30));
-  V = MIRBuilder.buildSelect(S32, CmpEGt30,
-                             MIRBuilder.buildConstant(S32, 0x7c00), V);
+                                       E, MIRBuilder.buildConstant(I32, 30));
+  V = MIRBuilder.buildSelect(I32, CmpEGt30,
+                             MIRBuilder.buildConstant(I32, 0x7c00), V);
 
   auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1,
-                                         E, MIRBuilder.buildConstant(S32, 1039));
-  V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V);
+                                         E, MIRBuilder.buildConstant(I32, 1039));
+  V = MIRBuilder.buildSelect(I32, CmpEGt1039, I, V);
 
   // Extract the sign bit.
-  auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16));
-  Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));
+  auto Sign = MIRBuilder.buildLShr(I32, UH, MIRBuilder.buildConstant(I32, 16));
+  Sign = MIRBuilder.buildAnd(I32, Sign, MIRBuilder.buildConstant(I32, 0x8000));
 
   // Insert the sign bit
-  V = MIRBuilder.buildOr(S32, Sign, V);
+  V = MIRBuilder.buildOr(I32, Sign, V);
 
   MIRBuilder.buildTrunc(Dst, V);
   MI.eraseFromParent();
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
index ff53b3dfdeb5e..69aa974f6aebc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fptrunc.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.50-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.50-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.50-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.50-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
 
 define amdgpu_ps half @fptrunc_f32_to_f16_uniform(float inreg %a) {
 ; GFX11-FAKE16-LABEL: fptrunc_f32_to_f16_uniform:
@@ -127,49 +127,48 @@ define amdgpu_ps float @fptrunc_f64_to_f32_div(double %a) {
 define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
 ; GFX11-LABEL: fptrunc_f64_to_f16_uniform:
 ; GFX11:       ; %bb.0:
-; GFX11-NEXT:    s_and_b32 s2, s1, 0x1ff
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_or_b32 s0, s2, s0
-; GFX11-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX11-NEXT:    s_bfe_u32 s2, s1, 0xb0014
-; GFX11-NEXT:    s_sub_i32 s3, 0x3f1, s2
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_med3_i32 v0, s3, 0, 13
 ; GFX11-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX11-NEXT:    s_and_b32 s4, s1, 0x1ff
+; GFX11-NEXT:    s_addk_i32 s2, 0xfc10
 ; GFX11-NEXT:    s_and_b32 s3, s3, 0xffe
-; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX11-NEXT:    s_or_b32 s0, s4, s0
+; GFX11-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_or_b32 s0, s3, s0
-; GFX11-NEXT:    s_or_b32 s3, s0, 0x1000
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_lshr_b32 s5, s3, s4
-; GFX11-NEXT:    s_lshl_b32 s4, s5, s4
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_cmp_lg_u32 s4, s3
 ; GFX11-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX11-NEXT:    s_addk_i32 s2, 0xfc10
-; GFX11-NEXT:    s_or_b32 s3, s5, s3
-; GFX11-NEXT:    s_lshl_b32 s4, s2, 12
-; GFX11-NEXT:    s_or_b32 s4, s0, s4
+; GFX11-NEXT:    s_sub_i32 s4, 1, s2
+; GFX11-NEXT:    s_or_b32 s5, s0, 0x1000
+; GFX11-NEXT:    s_max_i32 s4, s4, 0
+; GFX11-NEXT:    s_lshl_b32 s3, s3, 9
+; GFX11-NEXT:    s_min_i32 s4, s4, 13
+; GFX11-NEXT:    s_lshl_b32 s7, s2, 12
+; GFX11-NEXT:    s_lshr_b32 s6, s5, s4
+; GFX11-NEXT:    s_or_b32 s3, s3, 0x7c00
+; GFX11-NEXT:    s_lshl_b32 s4, s6, s4
+; GFX11-NEXT:    s_or_b32 s0, s0, s7
+; GFX11-NEXT:    s_cmp_lg_u32 s4, s5
+; GFX11-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_or_b32 s4, s6, s4
 ; GFX11-NEXT:    s_cmp_lt_i32 s2, 1
-; GFX11-NEXT:    s_cselect_b32 s3, s3, s4
-; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT:    s_and_b32 s4, s3, 7
-; GFX11-NEXT:    s_cmp_gt_i32 s4, 5
-; GFX11-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX11-NEXT:    s_cselect_b32 s0, s4, s0
+; GFX11-NEXT:    s_and_b32 s4, s0, 7
+; GFX11-NEXT:    s_lshr_b32 s0, s0, 2
 ; GFX11-NEXT:    s_cmp_eq_u32 s4, 3
+; GFX11-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX11-NEXT:    s_cmp_gt_i32 s4, 5
+; GFX11-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT:    s_or_b32 s4, s5, s4
+; GFX11-NEXT:    s_cmp_lg_u32 s4, 0
 ; GFX11-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX11-NEXT:    s_lshr_b32 s3, s3, 2
-; GFX11-NEXT:    s_or_b32 s4, s4, s5
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT:    s_add_i32 s3, s3, s4
-; GFX11-NEXT:    s_cmp_lt_i32 s2, 31
-; GFX11-NEXT:    s_movk_i32 s4, 0x7e00
-; GFX11-NEXT:    s_cselect_b32 s3, s3, 0x7c00
-; GFX11-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX11-NEXT:    s_cselect_b32 s0, s4, 0x7c00
+; GFX11-NEXT:    s_add_i32 s0, s0, s4
+; GFX11-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX11-NEXT:    s_cselect_b32 s0, 0x7c00, s0
 ; GFX11-NEXT:    s_cmpk_eq_i32 s2, 0x40f
-; GFX11-NEXT:    s_cselect_b32 s0, s0, s3
+; GFX11-NEXT:    s_cselect_b32 s0, s3, s0
 ; GFX11-NEXT:    s_lshr_b32 s1, s1, 16
 ; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX11-NEXT:    s_and_b32 s1, s1, 0x8000
@@ -180,57 +179,48 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
 ;
 ; GFX12-LABEL: fptrunc_f64_to_f16_uniform:
 ; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_and_b32 s2, s1, 0x1ff
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT:    s_or_b32 s0, s2, s0
-; GFX12-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX12-NEXT:    s_bfe_u32 s2, s1, 0xb0014
-; GFX12-NEXT:    s_sub_co_i32 s3, 0x3f1, s2
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-NEXT:    v_med3_i32 v0, s3, 0, 13
 ; GFX12-NEXT:    s_lshr_b32 s3, s1, 8
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT:    s_and_b32 s4, s1, 0x1ff
+; GFX12-NEXT:    s_addk_co_i32 s2, 0xfc10
 ; GFX12-NEXT:    s_and_b32 s3, s3, 0xffe
-; GFX12-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_or_b32 s0, s3, s0
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT:    s_or_b32 s3, s0, 0x1000
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_lshr_b32 s5, s3, s4
-; GFX12-NEXT:    s_lshl_b32 s4, s5, s4
+; GFX12-NEXT:    s_or_b32 s0, s4, s0
+; GFX12-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT:    s_cmp_lg_u32 s4, s3
+; GFX12-NEXT:    s_or_b32 s0, s3, s0
 ; GFX12-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX12-NEXT:    s_addk_co_i32 s2, 0xfc10
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_or_b32 s3, s5, s3
-; GFX12-NEXT:    s_lshl_b32 s4, s2, 12
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT:    s_or_b32 s4, s0, s4
+; GFX12-NEXT:    s_sub_co_i32 s4, 1, s2
+; GFX12-NEXT:    s_or_b32 s5, s0, 0x1000
+; GFX12-NEXT:    s_max_i32 s4, s4, 0
+; GFX12-NEXT:    s_lshl_b32 s3, s3, 9
+; GFX12-NEXT:    s_min_i32 s4, s4, 13
+; GFX12-NEXT:    s_lshl_b32 s7, s2, 12
+; GFX12-NEXT:    s_lshr_b32 s6, s5, s4
+; GFX12-NEXT:    s_or_b32 s3, s3, 0x7c00
+; GFX12-NEXT:    s_lshl_b32 s4, s6, s4
+; GFX12-NEXT:    s_or_b32 s0, s0, s7
+; GFX12-NEXT:    s_cmp_lg_u32 s4, s5
+; GFX12-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT:    s_or_b32 s4, s6, s4
 ; GFX12-NEXT:    s_cmp_lt_i32 s2, 1
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_cselect_b32 s3, s3, s4
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_and_b32 s4, s3, 7
-; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT:    s_cmp_gt_i32 s4, 5
-; GFX12-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX12-NEXT:    s_cselect_b32 s0, s4, s0
+; GFX12-NEXT:    s_and_b32 s4, s0, 7
+; GFX12-NEXT:    s_lshr_b32 s0, s0, 2
 ; GFX12-NEXT:    s_cmp_eq_u32 s4, 3
+; GFX12-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX12-NEXT:    s_cmp_gt_i32 s4, 5
 ; GFX12-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX12-NEXT:    s_lshr_b32 s3, s3, 2
-; GFX12-NEXT:    s_or_b32 s4, s4, s5
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_add_co_i32 s3, s3, s4
-; GFX12-NEXT:    s_cmp_lt_i32 s2, 31
-; GFX12-NEXT:    s_movk_i32 s4, 0x7e00
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_cselect_b32 s3, s3, 0x7c00
-; GFX12-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX12-NEXT:    s_cselect_b32 s0, s4, 0x7c00
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT:    s_or_b32 s4, s5, s4
+; GFX12-NEXT:    s_cmp_lg_u32 s4, 0
+; GFX12-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT:    s_add_co_i32 s0, s0, s4
+; GFX12-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX12-NEXT:    s_cselect_b32 s0, 0x7c00, s0
 ; GFX12-NEXT:    s_cmp_eq_u32 s2, 0x40f
-; GFX12-NEXT:    s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT:    s_cselect_b32 s0, s0, s3
+; GFX12-NEXT:    s_cselect_b32 s0, s3, s0
 ; GFX12-NEXT:    s_lshr_b32 s1, s1, 16
 ; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX12-NEXT:    s_and_b32 s1, s1, 0x8000
@@ -244,49 +234,48 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
 ; GFX1250-NEXT:    global_wb
 ; GFX1250-NEXT:    v_nop
 ; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT:    s_and_b32 s2, s1, 0x1ff
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_or_b32 s0, s2, s0
-; GFX1250-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX1250-NEXT:    s_bfe_u32 s2, s1, 0xb0014
-; GFX1250-NEXT:    s_sub_co_i32 s3, 0x3f1, s2
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    v_med3_i32 v0, s3, 0, 13
 ; GFX1250-NEXT:    s_lshr_b32 s3, s1, 8
+; GFX1250-NEXT:    s_and_b32 s4, s1, 0x1ff
+; GFX1250-NEXT:    s_addk_co_i32 s2, 0xfc10
 ; GFX1250-NEXT:    s_and_b32 s3, s3, 0xffe
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    v_readfirstlane_b32 s4, v0
+; GFX1250-NEXT:    s_or_b32 s0, s4, s0
+; GFX1250-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_or_b32 s0, s3, s0
-; GFX1250-NEXT:    s_or_b32 s3, s0, 0x1000
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_lshr_b32 s5, s3, s4
-; GFX1250-NEXT:    s_lshl_b32 s4, s5, s4
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_cmp_lg_u32 s4, s3
 ; GFX1250-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX1250-NEXT:    s_addk_co_i32 s2, 0xfc10
-; GFX1250-NEXT:    s_or_b32 s3, s5, s3
-; GFX1250-NEXT:    s_lshl_b32 s4, s2, 12
-; GFX1250-NEXT:    s_or_b32 s4, s0, s4
+; GFX1250-NEXT:    s_sub_co_i32 s4, 1, s2
+; GFX1250-NEXT:    s_or_b32 s5, s0, 0x1000
+; GFX1250-NEXT:    s_max_i32 s4, s4, 0
+; GFX1250-NEXT:    s_lshl_b32 s3, s3, 9
+; GFX1250-NEXT:    s_min_i32 s4, s4, 13
+; GFX1250-NEXT:    s_lshl_b32 s7, s2, 12
+; GFX1250-NEXT:    s_lshr_b32 s6, s5, s4
+; GFX1250-NEXT:    s_or_b32 s3, s3, 0x7c00
+; GFX1250-NEXT:    s_lshl_b32 s4, s6, s4
+; GFX1250-NEXT:    s_or_b32 s0, s0, s7
+; GFX1250-NEXT:    s_cmp_lg_u32 s4, s5
+; GFX1250-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_or_b32 s4, s6, s4
 ; GFX1250-NEXT:    s_cmp_lt_i32 s2, 1
-; GFX1250-NEXT:    s_cselect_b32 s3, s3, s4
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_and_b32 s4, s3, 7
-; GFX1250-NEXT:    s_cmp_gt_i32 s4, 5
-; GFX1250-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX1250-NEXT:    s_cselect_b32 s0, s4, s0
+; GFX1250-NEXT:    s_and_b32 s4, s0, 7
+; GFX1250-NEXT:    s_lshr_b32 s0, s0, 2
 ; GFX1250-NEXT:    s_cmp_eq_u32 s4, 3
+; GFX1250-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX1250-NEXT:    s_cmp_gt_i32 s4, 5
+; GFX1250-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_or_b32 s4, s5, s4
+; GFX1250-NEXT:    s_cmp_lg_u32 s4, 0
 ; GFX1250-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX1250-NEXT:    s_lshr_b32 s3, s3, 2
-; GFX1250-NEXT:    s_or_b32 s4, s4, s5
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_add_co_i32 s3, s3, s4
-; GFX1250-NEXT:    s_cmp_lt_i32 s2, 31
-; GFX1250-NEXT:    s_movk_i32 s4, 0x7e00
-; GFX1250-NEXT:    s_cselect_b32 s3, s3, 0x7c00
-; GFX1250-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX1250-NEXT:    s_cselect_b32 s0, s4, 0x7c00
+; GFX1250-NEXT:    s_add_co_i32 s0, s0, s4
+; GFX1250-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX1250-NEXT:    s_cselect_b32 s0, 0x7c00, s0
 ; GFX1250-NEXT:    s_cmp_eq_u32 s2, 0x40f
-; GFX1250-NEXT:    s_cselect_b32 s0, s0, s3
+; GFX1250-NEXT:    s_cselect_b32 s0, s3, s0
 ; GFX1250-NEXT:    s_lshr_b32 s1, s1, 16
 ; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
 ; GFX1250-NEXT:    s_and_b32 s1, s1, 0x8000
@@ -299,313 +288,156 @@ define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
 }
 
 define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
-; GFX11-FAKE16-LABEL: fptrunc_f64_to_f16_div:
-; GFX11-FAKE16:       ; %bb.0:
-; GFX11-FAKE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-FAKE16-NEXT:    v_med3_i32 v2, v4, 0, 13
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
-; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
-; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 7, v2
-; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX11-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
-; GFX11-FAKE16-NEXT:    ; return to shader part epilog
-;
-; GFX11-TRUE16-LABEL: fptrunc_f64_to_f16_div:
-; GFX11-TRUE16:       ; %bb.0:
-; GFX11-TRUE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-TRUE16-NEXT:    v_med3_i32 v2, v4, 0, 13
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
-; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX11-TRUE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
-; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX11-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v2
-; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX11-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.h, 0
-; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v1.h
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX11-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX11-TRUE16-NEXT:    v_and_or_b32 v0, 0x8000, v4, v0
-; GFX11-TRUE16-NEXT:    ; return to shader part epilog
-;
-; GFX12-FAKE16-LABEL: fptrunc_f64_to_f16_div:
-; GFX12-FAKE16:       ; %bb.0:
-; GFX12-FAKE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX12-FAKE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
-; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-FAKE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX12-FAKE16-NEXT:    v_med3_i32 v2, v4, 0, 13
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
-; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
-; GFX12-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX12-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX12-FAKE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
-; GFX12-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX12-FAKE16-NEXT:    v_and_b32_e32 v4, 7, v2
-; GFX12-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX12-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX12-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX12-FAKE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX12-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX12-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX12-FAKE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-FAKE16-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
-; GFX12-FAKE16-NEXT:    ; return to shader part epilog
-;
-; GFX12-TRUE16-LABEL: fptrunc_f64_to_f16_div:
-; GFX12-TRUE16:       ; %bb.0:
-; GFX12-TRUE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX12-TRUE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX12-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX12-TRUE16-NEXT:    v_med3_i32 v2, v4, 0, 13
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
-; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
-; GFX12-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX12-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX12-TRUE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
-; GFX12-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX12-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v2
-; GFX12-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX12-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX12-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX12-TRUE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX12-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.h, 0
-; GFX12-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v1.h
-; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX12-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX12-TRUE16-NEXT:    s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX12-TRUE16-NEXT:    v_and_or_b32 v0, 0x8000, v4, v0
-; GFX12-TRUE16-NEXT:    ; return to shader part epilog
+; GFX11-LABEL: fptrunc_f64_to_f16_div:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX11-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
+; GFX11-NEXT:    v_and_or_b32 v0, 0xffe, v3, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_med3_i32 v3, v4, 0, 13
+; GFX11-NEXT:    v_or_b32_e32 v4, 0x1000, v0
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
+; GFX11-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX11-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX11-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX11-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-NEXT:    v_and_b32_e32 v4, 7, v3
+; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX11-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
+; GFX11-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX11-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX11-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT:    v_add_nc_u32_e32 v3, v3, v4
+; GFX11-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX11-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX11-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
+; GFX11-NEXT:    ; return to shader part epilog
 ;
-; GFX1250-FAKE16-LABEL: fptrunc_f64_to_f16_div:
-; GFX1250-FAKE16:       ; %bb.0:
-; GFX1250-FAKE16-NEXT:    global_wb
-; GFX1250-FAKE16-NEXT:    v_nop
-; GFX1250-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-FAKE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX1250-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX1250-FAKE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
-; GFX1250-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1250-FAKE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX1250-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-FAKE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX1250-FAKE16-NEXT:    v_med3_i32 v2, v4, 0, 13
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
-; GFX1250-FAKE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
-; GFX1250-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX1250-FAKE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX1250-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-FAKE16-NEXT:    v_and_b32_e32 v4, 7, v2
-; GFX1250-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX1250-FAKE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1250-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX1250-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX1250-FAKE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX1250-FAKE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX1250-FAKE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX1250-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX1250-FAKE16-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
-; GFX1250-FAKE16-NEXT:    ; return to shader part epilog
+; GFX12-LABEL: fptrunc_f64_to_f16_div:
+; GFX12:       ; %bb.0:
+; GFX12-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX12-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX12-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX12-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
+; GFX12-NEXT:    v_and_or_b32 v0, 0xffe, v3, v0
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_med3_i32 v3, v4, 0, 13
+; GFX12-NEXT:    v_or_b32_e32 v4, 0x1000, v0
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
+; GFX12-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX12-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
+; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX12-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX12-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX12-NEXT:    v_and_b32_e32 v4, 7, v3
+; GFX12-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX12-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX12-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
+; GFX12-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX12-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX12-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-NEXT:    v_add_nc_u32_e32 v3, v3, v4
+; GFX12-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX12-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX12-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX12-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX12-NEXT:    s_wait_alu depctr_va_vcc(0)
+; GFX12-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
+; GFX12-NEXT:    ; return to shader part epilog
 ;
-; GFX1250-TRUE16-LABEL: fptrunc_f64_to_f16_div:
-; GFX1250-TRUE16:       ; %bb.0:
-; GFX1250-TRUE16-NEXT:    global_wb
-; GFX1250-TRUE16-NEXT:    v_nop
-; GFX1250-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-TRUE16-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX1250-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX1250-TRUE16-NEXT:    v_bfe_u32 v3, v1, 20, 11
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1250-TRUE16-NEXT:    v_sub_nc_u32_e32 v4, 0x3f1, v3
-; GFX1250-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0xfffffc10, v3
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX1250-TRUE16-NEXT:    v_med3_i32 v2, v4, 0, 13
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT:    v_or_b32_e32 v4, 0x1000, v0
-; GFX1250-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, v2, v4
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, v2, v5
-; GFX1250-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v4
-; GFX1250-TRUE16-NEXT:    v_lshl_or_b32 v4, v3, 12, v0
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX1250-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v3
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT:    v_or_b32_e32 v2, v5, v2
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1250-TRUE16-NEXT:    v_and_b32_e32 v4, 7, v2
-; GFX1250-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX1250-TRUE16-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v4
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1250-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX1250-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT:    v_or_b32_e32 v4, v4, v5
-; GFX1250-TRUE16-NEXT:    v_dual_mov_b32 v5, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v4
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v5, vcc_lo
-; GFX1250-TRUE16-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v3
-; GFX1250-TRUE16-NEXT:    v_mov_b16_e32 v4.h, 0
-; GFX1250-TRUE16-NEXT:    v_mov_b16_e32 v4.l, v1.h
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
-; GFX1250-TRUE16-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v3
-; GFX1250-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
-; GFX1250-TRUE16-NEXT:    v_and_or_b32 v0, 0x8000, v4, v0
-; GFX1250-TRUE16-NEXT:    ; return to shader part epilog
+; GFX1250-LABEL: fptrunc_f64_to_f16_div:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    global_wb
+; GFX1250-NEXT:    v_nop
+; GFX1250-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
+; GFX1250-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
+; GFX1250-NEXT:    v_dual_lshrrev_b32 v3, 8, v1 :: v_dual_lshrrev_b32 v1, 16, v1
+; GFX1250-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
+; GFX1250-NEXT:    v_and_or_b32 v0, 0xffe, v3, v0
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_med3_i32 v3, v4, 0, 13
+; GFX1250-NEXT:    v_or_b32_e32 v4, 0x1000, v0
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
+; GFX1250-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX1250-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
+; GFX1250-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX1250-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX1250-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1250-NEXT:    v_and_b32_e32 v4, 7, v3
+; GFX1250-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX1250-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
+; GFX1250-NEXT:    s_or_b32 s0, vcc_lo, s0
+; GFX1250-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX1250-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX1250-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1250-NEXT:    v_add_nc_u32_e32 v3, v3, v4
+; GFX1250-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX1250-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX1250-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX1250-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
+; GFX1250-NEXT:    ; return to shader part epilog
   %result = fptrunc double %a to half
   ret half %result
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
index 0368684fc6e4c..18250cdb08d47 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
@@ -96,70 +96,70 @@ body: |
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](f64)
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
-    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
-    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1008
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
-    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C3]](s32)
-    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4094
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
-    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C5]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[UV]]
-    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](s32), [[C6]]
-    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ZEXT]]
-    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 512
-    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](s32), [[C6]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
-    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
-    ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
-    ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
-    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C9]](s32)
-    ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL]]
-    ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
-    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C6]]
-    ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
-    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
-    ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
-    ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
-    ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
-    ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
-    ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]]
-    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP2]](s1)
-    ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[ZEXT1]]
-    ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](s32), [[C10]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
-    ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
-    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C13]]
-    ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C14]](s32)
-    ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](s32), [[C15]]
-    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP4]](s1)
-    ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
-    ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](s32), [[C16]]
-    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP5]](s1)
-    ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[ZEXT3]]
-    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[OR6]]
-    ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
-    ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD]](s32), [[C17]]
-    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
-    ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1039
-    ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD]](s32), [[C18]]
-    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
-    ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C19]](s32)
-    ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
-    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
-    ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
-    ; CHECK-NEXT: $vgpr0 = COPY [[OR7]](s32)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](f64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[UV1]], [[C]](i32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2047
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1008
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[AND]], [[C2]]
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[UV1]], [[C3]](i32)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4094
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR1]], [[C4]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 511
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[UV1]], [[C5]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[UV]]
+    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](i32), [[C6]]
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[ZEXT]]
+    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 512
+    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](i32), [[C6]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
+    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 31744
+    ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[SELECT]], [[C8]]
+    ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ADD]], [[C9]](i32)
+    ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL]]
+    ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[C10]], [[ADD]]
+    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(i32) = G_SMAX [[SUB]], [[C6]]
+    ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(i32) = G_SMIN [[SMAX]], [[C11]]
+    ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 4096
+    ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[C12]]
+    ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[OR4]], [[SMIN]](i32)
+    ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[LSHR2]], [[SMIN]](i32)
+    ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](i32), [[OR4]]
+    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP2]](s1)
+    ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[LSHR2]], [[ZEXT1]]
+    ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](i32), [[C10]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
+    ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[SELECT1]], [[C13]]
+    ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+    ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[SELECT1]], [[C14]](i32)
+    ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+    ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](i32), [[C15]]
+    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP4]](s1)
+    ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+    ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](i32), [[C16]]
+    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP5]](s1)
+    ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[ZEXT3]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[LSHR3]], [[OR6]]
+    ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
+    ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD]](i32), [[C17]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(i32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
+    ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 1039
+    ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD]](i32), [[C18]]
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(i32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
+    ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+    ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[UV1]], [[C19]](i32)
+    ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 32768
+    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C20]]
+    ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SELECT3]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[OR7]](i32)
     %0:_(f64) = COPY $vgpr0_vgpr1
     %1:_(f16) = G_FPTRUNC %0
     %2:_(s32) = G_ANYEXT %1
@@ -177,116 +177,115 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](f64)
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C]](s32)
-    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
-    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1008
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
-    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C3]](s32)
-    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4094
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
-    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C5]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[UV2]]
-    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](s32), [[C6]]
-    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ZEXT]]
-    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 512
-    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](s32), [[C6]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
-    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
-    ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
-    ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
-    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C9]](s32)
-    ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL]]
-    ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
-    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C6]]
-    ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
-    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
-    ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
-    ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
-    ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
-    ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
-    ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]]
-    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP2]](s1)
-    ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[ZEXT1]]
-    ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](s32), [[C10]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
-    ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
-    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C13]]
-    ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C14]](s32)
-    ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](s32), [[C15]]
-    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP4]](s1)
-    ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
-    ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](s32), [[C16]]
-    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP5]](s1)
-    ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[ZEXT3]]
-    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[OR6]]
-    ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
-    ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD]](s32), [[C17]]
-    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
-    ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1039
-    ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD]](s32), [[C18]]
-    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
-    ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV3]], [[C19]](s32)
-    ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
-    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
-    ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
-    ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](f64)
-    ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C]](s32)
-    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[LSHR5]], [[C1]]
-    ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[AND5]], [[C2]]
-    ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C3]](s32)
-    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[LSHR6]], [[C4]]
-    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C5]]
-    ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(s32) = G_OR [[AND7]], [[UV4]]
-    ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR8]](s32), [[C6]]
-    ; CHECK-NEXT: [[ZEXT4:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP8]](s1)
-    ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(s32) = G_OR [[AND6]], [[ZEXT4]]
-    ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR9]](s32), [[C6]]
-    ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[ICMP9]](s1), [[C7]], [[C6]]
-    ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(s32) = G_OR [[SELECT4]], [[C8]]
-    ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[ADD2]], [[C9]](s32)
-    ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[SHL2]]
-    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD2]]
-    ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(s32) = G_SMAX [[SUB1]], [[C6]]
-    ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(s32) = G_SMIN [[SMAX1]], [[C11]]
-    ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C12]]
-    ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[OR12]], [[SMIN1]](s32)
-    ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[LSHR7]], [[SMIN1]](s32)
-    ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL3]](s32), [[OR12]]
-    ; CHECK-NEXT: [[ZEXT5:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP10]](s1)
-    ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(s32) = G_OR [[LSHR7]], [[ZEXT5]]
-    ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD2]](s32), [[C10]]
-    ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[ICMP11]](s1), [[OR13]], [[OR11]]
-    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[SELECT5]], [[C13]]
-    ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[SELECT5]], [[C14]](s32)
-    ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND8]](s32), [[C15]]
-    ; CHECK-NEXT: [[ZEXT6:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP12]](s1)
-    ; CHECK-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND8]](s32), [[C16]]
-    ; CHECK-NEXT: [[ZEXT7:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP13]](s1)
-    ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(s32) = G_OR [[ZEXT6]], [[ZEXT7]]
-    ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[LSHR8]], [[OR14]]
-    ; CHECK-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD2]](s32), [[C17]]
-    ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(s32) = G_SELECT [[ICMP14]](s1), [[C8]], [[ADD3]]
-    ; CHECK-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD2]](s32), [[C18]]
-    ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(s32) = G_SELECT [[ICMP15]](s1), [[OR10]], [[SELECT6]]
-    ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[UV5]], [[C19]](s32)
-    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[LSHR9]], [[C20]]
-    ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(s32) = G_OR [[AND9]], [[SELECT7]]
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[UV]](f64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[UV3]], [[C]](i32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2047
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1008
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[AND]], [[C2]]
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[UV3]], [[C3]](i32)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4094
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR1]], [[C4]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 511
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[UV3]], [[C5]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[UV2]]
+    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](i32), [[C6]]
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[ZEXT]]
+    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 512
+    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](i32), [[C6]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
+    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 31744
+    ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[SELECT]], [[C8]]
+    ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ADD]], [[C9]](i32)
+    ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL]]
+    ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[C10]], [[ADD]]
+    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(i32) = G_SMAX [[SUB]], [[C6]]
+    ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(i32) = G_SMIN [[SMAX]], [[C11]]
+    ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 4096
+    ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[C12]]
+    ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[OR4]], [[SMIN]](i32)
+    ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[LSHR2]], [[SMIN]](i32)
+    ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](i32), [[OR4]]
+    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP2]](s1)
+    ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[LSHR2]], [[ZEXT1]]
+    ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](i32), [[C10]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
+    ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[SELECT1]], [[C13]]
+    ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+    ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[SELECT1]], [[C14]](i32)
+    ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+    ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](i32), [[C15]]
+    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP4]](s1)
+    ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+    ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](i32), [[C16]]
+    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP5]](s1)
+    ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[ZEXT3]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[LSHR3]], [[OR6]]
+    ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
+    ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD]](i32), [[C17]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(i32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
+    ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 1039
+    ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD]](i32), [[C18]]
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(i32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
+    ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+    ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[UV3]], [[C19]](i32)
+    ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 32768
+    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C20]]
+    ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SELECT3]]
+    ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(i32), [[UV5:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[UV1]](f64)
+    ; CHECK-NEXT: [[LSHR5:%[0-9]+]]:_(i32) = G_LSHR [[UV5]], [[C]](i32)
+    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(i32) = G_AND [[LSHR5]], [[C1]]
+    ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(i32) = G_ADD [[AND5]], [[C2]]
+    ; CHECK-NEXT: [[LSHR6:%[0-9]+]]:_(i32) = G_LSHR [[UV5]], [[C3]](i32)
+    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(i32) = G_AND [[LSHR6]], [[C4]]
+    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(i32) = G_AND [[UV5]], [[C5]]
+    ; CHECK-NEXT: [[OR8:%[0-9]+]]:_(i32) = G_OR [[AND7]], [[UV4]]
+    ; CHECK-NEXT: [[ICMP8:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR8]](i32), [[C6]]
+    ; CHECK-NEXT: [[ZEXT4:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP8]](s1)
+    ; CHECK-NEXT: [[OR9:%[0-9]+]]:_(i32) = G_OR [[AND6]], [[ZEXT4]]
+    ; CHECK-NEXT: [[ICMP9:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR9]](i32), [[C6]]
+    ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(i32) = G_SELECT [[ICMP9]](s1), [[C7]], [[C6]]
+    ; CHECK-NEXT: [[OR10:%[0-9]+]]:_(i32) = G_OR [[SELECT4]], [[C8]]
+    ; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(i32) = G_SHL [[ADD2]], [[C9]](i32)
+    ; CHECK-NEXT: [[OR11:%[0-9]+]]:_(i32) = G_OR [[OR9]], [[SHL2]]
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(i32) = G_SUB [[C10]], [[ADD2]]
+    ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(i32) = G_SMAX [[SUB1]], [[C6]]
+    ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(i32) = G_SMIN [[SMAX1]], [[C11]]
+    ; CHECK-NEXT: [[OR12:%[0-9]+]]:_(i32) = G_OR [[OR9]], [[C12]]
+    ; CHECK-NEXT: [[LSHR7:%[0-9]+]]:_(i32) = G_LSHR [[OR12]], [[SMIN1]](i32)
+    ; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(i32) = G_SHL [[LSHR7]], [[SMIN1]](i32)
+    ; CHECK-NEXT: [[ICMP10:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL3]](i32), [[OR12]]
+    ; CHECK-NEXT: [[ZEXT5:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP10]](s1)
+    ; CHECK-NEXT: [[OR13:%[0-9]+]]:_(i32) = G_OR [[LSHR7]], [[ZEXT5]]
+    ; CHECK-NEXT: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD2]](i32), [[C10]]
+    ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(i32) = G_SELECT [[ICMP11]](s1), [[OR13]], [[OR11]]
+    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(i32) = G_AND [[SELECT5]], [[C13]]
+    ; CHECK-NEXT: [[LSHR8:%[0-9]+]]:_(i32) = G_LSHR [[SELECT5]], [[C14]](i32)
+    ; CHECK-NEXT: [[ICMP12:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND8]](i32), [[C15]]
+    ; CHECK-NEXT: [[ZEXT6:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP12]](s1)
+    ; CHECK-NEXT: [[ICMP13:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND8]](i32), [[C16]]
+    ; CHECK-NEXT: [[ZEXT7:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP13]](s1)
+    ; CHECK-NEXT: [[OR14:%[0-9]+]]:_(i32) = G_OR [[ZEXT6]], [[ZEXT7]]
+    ; CHECK-NEXT: [[ADD3:%[0-9]+]]:_(i32) = G_ADD [[LSHR8]], [[OR14]]
+    ; CHECK-NEXT: [[ICMP14:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD2]](i32), [[C17]]
+    ; CHECK-NEXT: [[SELECT6:%[0-9]+]]:_(i32) = G_SELECT [[ICMP14]](s1), [[C8]], [[ADD3]]
+    ; CHECK-NEXT: [[ICMP15:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD2]](i32), [[C18]]
+    ; CHECK-NEXT: [[SELECT7:%[0-9]+]]:_(i32) = G_SELECT [[ICMP15]](s1), [[OR10]], [[SELECT6]]
+    ; CHECK-NEXT: [[LSHR9:%[0-9]+]]:_(i32) = G_LSHR [[UV5]], [[C19]](i32)
+    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(i32) = G_AND [[LSHR9]], [[C20]]
+    ; CHECK-NEXT: [[OR15:%[0-9]+]]:_(i32) = G_OR [[AND9]], [[SELECT7]]
     ; CHECK-NEXT: [[C21:%[0-9]+]]:_(i32) = G_CONSTANT i32 65535
     ; CHECK-NEXT: [[AND10:%[0-9]+]]:_(i32) = G_AND [[OR7]], [[C21]]
     ; CHECK-NEXT: [[AND11:%[0-9]+]]:_(i32) = G_AND [[OR15]], [[C21]]
-    ; CHECK-NEXT: [[C22:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
-    ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[C22]](i32)
+    ; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(i32) = G_SHL [[AND11]], [[C19]](i32)
     ; CHECK-NEXT: [[OR16:%[0-9]+]]:_(i32) = G_OR [[AND10]], [[SHL4]]
     ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x f16>) = G_BITCAST [[OR16]](i32)
     ; CHECK-NEXT: $vgpr0 = COPY [[BITCAST]](<2 x f16>)
@@ -305,70 +304,70 @@ body: |
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(f64) = COPY $vgpr0_vgpr1
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](f64)
-    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
-    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
-    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2047
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]]
-    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1008
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C2]]
-    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
-    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C3]](s32)
-    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4094
-    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C4]]
-    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 511
-    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C5]]
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[UV]]
-    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](s32), [[C6]]
-    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[ZEXT]]
-    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 512
-    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](s32), [[C6]]
-    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
-    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 31744
-    ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SELECT]], [[C8]]
-    ; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
-    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ADD]], [[C9]](s32)
-    ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[SHL]]
-    ; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
-    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SUB]], [[C6]]
-    ; CHECK-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
-    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SMAX]], [[C11]]
-    ; CHECK-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
-    ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
-    ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[OR4]], [[SMIN]](s32)
-    ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[LSHR2]], [[SMIN]](s32)
-    ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](s32), [[OR4]]
-    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP2]](s1)
-    ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s32) = G_OR [[LSHR2]], [[ZEXT1]]
-    ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](s32), [[C10]]
-    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
-    ; CHECK-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
-    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[SELECT1]], [[C13]]
-    ; CHECK-NEXT: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
-    ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SELECT1]], [[C14]](s32)
-    ; CHECK-NEXT: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
-    ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](s32), [[C15]]
-    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP4]](s1)
-    ; CHECK-NEXT: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
-    ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](s32), [[C16]]
-    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP5]](s1)
-    ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[ZEXT3]]
-    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[LSHR3]], [[OR6]]
-    ; CHECK-NEXT: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 30
-    ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD]](s32), [[C17]]
-    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
-    ; CHECK-NEXT: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 1039
-    ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD]](s32), [[C18]]
-    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
-    ; CHECK-NEXT: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
-    ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C19]](s32)
-    ; CHECK-NEXT: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 32768
-    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s32) = G_AND [[LSHR4]], [[C20]]
-    ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(s32) = G_OR [[AND4]], [[SELECT3]]
-    ; CHECK-NEXT: $vgpr0 = COPY [[OR7]](s32)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[COPY]](f64)
+    ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 20
+    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[UV1]], [[C]](i32)
+    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 2047
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[LSHR]], [[C1]]
+    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 -1008
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(i32) = G_ADD [[AND]], [[C2]]
+    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+    ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[UV1]], [[C3]](i32)
+    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(i32) = G_CONSTANT i32 4094
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[LSHR1]], [[C4]]
+    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(i32) = G_CONSTANT i32 511
+    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(i32) = G_AND [[UV1]], [[C5]]
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND2]], [[UV]]
+    ; CHECK-NEXT: [[C6:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR]](i32), [[C6]]
+    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP]](s1)
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[ZEXT]]
+    ; CHECK-NEXT: [[C7:%[0-9]+]]:_(i32) = G_CONSTANT i32 512
+    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[OR1]](i32), [[C6]]
+    ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(i32) = G_SELECT [[ICMP1]](s1), [[C7]], [[C6]]
+    ; CHECK-NEXT: [[C8:%[0-9]+]]:_(i32) = G_CONSTANT i32 31744
+    ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[SELECT]], [[C8]]
+    ; CHECK-NEXT: [[C9:%[0-9]+]]:_(i32) = G_CONSTANT i32 12
+    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[ADD]], [[C9]](i32)
+    ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[SHL]]
+    ; CHECK-NEXT: [[C10:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(i32) = G_SUB [[C10]], [[ADD]]
+    ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(i32) = G_SMAX [[SUB]], [[C6]]
+    ; CHECK-NEXT: [[C11:%[0-9]+]]:_(i32) = G_CONSTANT i32 13
+    ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(i32) = G_SMIN [[SMAX]], [[C11]]
+    ; CHECK-NEXT: [[C12:%[0-9]+]]:_(i32) = G_CONSTANT i32 4096
+    ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(i32) = G_OR [[OR1]], [[C12]]
+    ; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[OR4]], [[SMIN]](i32)
+    ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[LSHR2]], [[SMIN]](i32)
+    ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL1]](i32), [[OR4]]
+    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP2]](s1)
+    ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(i32) = G_OR [[LSHR2]], [[ZEXT1]]
+    ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](i32), [[C10]]
+    ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(i32) = G_SELECT [[ICMP3]](s1), [[OR5]], [[OR3]]
+    ; CHECK-NEXT: [[C13:%[0-9]+]]:_(i32) = G_CONSTANT i32 7
+    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(i32) = G_AND [[SELECT1]], [[C13]]
+    ; CHECK-NEXT: [[C14:%[0-9]+]]:_(i32) = G_CONSTANT i32 2
+    ; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[SELECT1]], [[C14]](i32)
+    ; CHECK-NEXT: [[C15:%[0-9]+]]:_(i32) = G_CONSTANT i32 3
+    ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND3]](i32), [[C15]]
+    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP4]](s1)
+    ; CHECK-NEXT: [[C16:%[0-9]+]]:_(i32) = G_CONSTANT i32 5
+    ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[AND3]](i32), [[C16]]
+    ; CHECK-NEXT: [[ZEXT3:%[0-9]+]]:_(i32) = G_ZEXT [[ICMP5]](s1)
+    ; CHECK-NEXT: [[OR6:%[0-9]+]]:_(i32) = G_OR [[ZEXT2]], [[ZEXT3]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(i32) = G_ADD [[LSHR3]], [[OR6]]
+    ; CHECK-NEXT: [[C17:%[0-9]+]]:_(i32) = G_CONSTANT i32 30
+    ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[ADD]](i32), [[C17]]
+    ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(i32) = G_SELECT [[ICMP6]](s1), [[C8]], [[ADD1]]
+    ; CHECK-NEXT: [[C18:%[0-9]+]]:_(i32) = G_CONSTANT i32 1039
+    ; CHECK-NEXT: [[ICMP7:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[ADD]](i32), [[C18]]
+    ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(i32) = G_SELECT [[ICMP7]](s1), [[OR2]], [[SELECT2]]
+    ; CHECK-NEXT: [[C19:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
+    ; CHECK-NEXT: [[LSHR4:%[0-9]+]]:_(i32) = G_LSHR [[UV1]], [[C19]](i32)
+    ; CHECK-NEXT: [[C20:%[0-9]+]]:_(i32) = G_CONSTANT i32 32768
+    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(i32) = G_AND [[LSHR4]], [[C20]]
+    ; CHECK-NEXT: [[OR7:%[0-9]+]]:_(i32) = G_OR [[AND4]], [[SELECT3]]
+    ; CHECK-NEXT: $vgpr0 = COPY [[OR7]](i32)
     %0:_(f64) = COPY $vgpr0_vgpr1
     %1:_(f16) = G_FPTRUNC %0
     %2:_(s32) = afn G_ANYEXT %1
@@ -386,10 +385,10 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x f64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
     ; CHECK-NEXT: [[UV:%[0-9]+]]:_(f64), [[UV1:%[0-9]+]]:_(f64) = G_UNMERGE_VALUES [[COPY]](<2 x f64>)
-    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s32) = afn G_FPTRUNC [[UV]](f64)
-    ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = afn G_FPTRUNC [[FPTRUNC]](s32)
-    ; CHECK-NEXT: [[FPTRUNC2:%[0-9]+]]:_(s32) = afn G_FPTRUNC [[UV1]](f64)
-    ; CHECK-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = afn G_FPTRUNC [[FPTRUNC2]](s32)
+    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(f32) = afn G_FPTRUNC [[UV]](f64)
+    ; CHECK-NEXT: [[FPTRUNC1:%[0-9]+]]:_(f16) = afn G_FPTRUNC [[FPTRUNC]](f32)
+    ; CHECK-NEXT: [[FPTRUNC2:%[0-9]+]]:_(f32) = afn G_FPTRUNC [[UV1]](f64)
+    ; CHECK-NEXT: [[FPTRUNC3:%[0-9]+]]:_(f16) = afn G_FPTRUNC [[FPTRUNC2]](f32)
     ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC1]](f16)
     ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(i32) = G_ZEXT [[FPTRUNC3]](f16)
     ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
index aed733e40ef2a..250edaa5c9a50 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
@@ -1,20 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 -global-isel=0 < %s | FileCheck -enable-var-scope -check-prefixes=SI-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=SI-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 -global-isel=1 < %s | FileCheck -check-prefixes=SI-GISEL %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu8.03 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu8.03 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu8.03 -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=VI-GISEL %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.00 -global-isel=0 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.00 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.00 -global-isel=1 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX9-GISEL %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.50 -global-isel=0 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-SDAG %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.50 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-GISEL %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.50 -global-isel=1 -mattr=-flat-for-global -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX950-GISEL %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -global-isel=0 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SDAG-TRUE16 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -global-isel=0 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-SDAG-FAKE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-TRUE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-FAKE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -global-isel=1 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -global-isel=1 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX11-GISEL-FAKE16 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.50 -global-isel=0 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-TRUE16 %s
 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.50 -global-isel=0 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-SDAG-FAKE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.50 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-TRUE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.50 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-FAKE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.50 -global-isel=1 -mattr=-flat-for-global,+real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.50 -global-isel=1 -mattr=-flat-for-global,-real-true16 -denormal-fp-math=preserve-sign < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250-GISEL-FAKE16 %s
 
 define amdgpu_kernel void @fptrunc_f32_to_f16(
 ; SI-SDAG-LABEL: fptrunc_f32_to_f16:
@@ -619,60 +619,54 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
 ;
 ; SI-GISEL-LABEL: fptrunc_f64_to_f16:
 ; SI-GISEL:       ; %bb.0: ; %entry
-; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s10, s2
-; SI-GISEL-NEXT:    s_mov_b32 s11, s3
+; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    s_mov_b32 s8, s6
-; SI-GISEL-NEXT:    s_mov_b32 s9, s7
-; SI-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; SI-GISEL-NEXT:    s_mov_b32 s0, s4
-; SI-GISEL-NEXT:    s_mov_b32 s1, s5
-; SI-GISEL-NEXT:    s_movk_i32 s6, 0x7e00
-; SI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s4, v1
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s5, v0
-; SI-GISEL-NEXT:    s_and_b32 s7, s4, 0x1ff
-; SI-GISEL-NEXT:    s_or_b32 s5, s7, s5
+; SI-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; SI-GISEL-NEXT:    s_lshr_b32 s5, s3, 8
+; SI-GISEL-NEXT:    s_and_b32 s6, s3, 0x1ff
+; SI-GISEL-NEXT:    s_addk_i32 s4, 0xfc10
+; SI-GISEL-NEXT:    s_and_b32 s5, s5, 0xffe
+; SI-GISEL-NEXT:    s_or_b32 s2, s6, s2
+; SI-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s2, s5, s2
 ; SI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; SI-GISEL-NEXT:    s_lshr_b32 s7, s4, 8
-; SI-GISEL-NEXT:    s_bfe_u32 s8, s4, 0xb0014
-; SI-GISEL-NEXT:    s_and_b32 s7, s7, 0xffe
-; SI-GISEL-NEXT:    s_sub_i32 s9, 0x3f1, s8
-; SI-GISEL-NEXT:    s_or_b32 s5, s7, s5
-; SI-GISEL-NEXT:    v_med3_i32 v0, s9, 0, 13
-; SI-GISEL-NEXT:    s_or_b32 s7, s5, 0x1000
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s9, v0
-; SI-GISEL-NEXT:    s_lshr_b32 s10, s7, s9
-; SI-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
-; SI-GISEL-NEXT:    s_cmp_lg_u32 s9, s7
+; SI-GISEL-NEXT:    s_sub_i32 s7, 1, s4
+; SI-GISEL-NEXT:    s_lshl_b32 s6, s4, 12
+; SI-GISEL-NEXT:    s_max_i32 s7, s7, 0
+; SI-GISEL-NEXT:    s_or_b32 s6, s2, s6
+; SI-GISEL-NEXT:    s_min_i32 s7, s7, 13
+; SI-GISEL-NEXT:    s_bitset1_b32 s2, 12
+; SI-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; SI-GISEL-NEXT:    s_lshr_b32 s8, s2, s7
+; SI-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; SI-GISEL-NEXT:    s_lshl_b32 s7, s8, s7
+; SI-GISEL-NEXT:    s_cmp_lg_u32 s7, s2
+; SI-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s2, s8, s2
+; SI-GISEL-NEXT:    s_cmp_lt_i32 s4, 1
+; SI-GISEL-NEXT:    s_cselect_b32 s2, s2, s6
+; SI-GISEL-NEXT:    s_and_b32 s6, s2, 7
+; SI-GISEL-NEXT:    s_lshr_b32 s2, s2, 2
+; SI-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
 ; SI-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
-; SI-GISEL-NEXT:    s_addk_i32 s8, 0xfc10
-; SI-GISEL-NEXT:    s_lshl_b32 s9, s8, 12
-; SI-GISEL-NEXT:    s_or_b32 s7, s10, s7
-; SI-GISEL-NEXT:    s_or_b32 s9, s5, s9
-; SI-GISEL-NEXT:    s_cmp_lt_i32 s8, 1
-; SI-GISEL-NEXT:    s_cselect_b32 s7, s7, s9
-; SI-GISEL-NEXT:    s_and_b32 s9, s7, 7
-; SI-GISEL-NEXT:    s_cmp_gt_i32 s9, 5
-; SI-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; SI-GISEL-NEXT:    s_cmp_eq_u32 s9, 3
-; SI-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; SI-GISEL-NEXT:    s_lshr_b32 s7, s7, 2
-; SI-GISEL-NEXT:    s_or_b32 s9, s9, s10
-; SI-GISEL-NEXT:    s_add_i32 s7, s7, s9
-; SI-GISEL-NEXT:    s_cmp_lt_i32 s8, 31
-; SI-GISEL-NEXT:    s_cselect_b32 s7, s7, 0x7c00
-; SI-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; SI-GISEL-NEXT:    s_cselect_b32 s5, s6, 0x7c00
-; SI-GISEL-NEXT:    s_cmpk_eq_i32 s8, 0x40f
-; SI-GISEL-NEXT:    s_cselect_b32 s5, s5, s7
-; SI-GISEL-NEXT:    s_lshr_b32 s4, s4, 16
-; SI-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
-; SI-GISEL-NEXT:    s_or_b32 s4, s4, s5
-; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
+; SI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s6, s7, s6
+; SI-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT:    s_add_i32 s2, s2, s6
+; SI-GISEL-NEXT:    s_cmp_gt_i32 s4, 30
+; SI-GISEL-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; SI-GISEL-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; SI-GISEL-NEXT:    s_cselect_b32 s2, s5, s2
+; SI-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
+; SI-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; SI-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
@@ -737,60 +731,54 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
 ;
 ; VI-GISEL-LABEL: fptrunc_f64_to_f16:
 ; VI-GISEL:       ; %bb.0: ; %entry
-; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x24
-; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; VI-GISEL-NEXT:    s_mov_b32 s2, -1
-; VI-GISEL-NEXT:    s_mov_b32 s10, s2
-; VI-GISEL-NEXT:    s_mov_b32 s11, s3
+; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    s_mov_b32 s8, s6
-; VI-GISEL-NEXT:    s_mov_b32 s9, s7
-; VI-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; VI-GISEL-NEXT:    s_mov_b32 s0, s4
-; VI-GISEL-NEXT:    s_mov_b32 s1, s5
-; VI-GISEL-NEXT:    s_movk_i32 s6, 0x7e00
-; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s4, v1
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s5, v0
-; VI-GISEL-NEXT:    s_and_b32 s7, s4, 0x1ff
-; VI-GISEL-NEXT:    s_or_b32 s5, s7, s5
+; VI-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; VI-GISEL-NEXT:    s_lshr_b32 s5, s3, 8
+; VI-GISEL-NEXT:    s_and_b32 s6, s3, 0x1ff
+; VI-GISEL-NEXT:    s_addk_i32 s4, 0xfc10
+; VI-GISEL-NEXT:    s_and_b32 s5, s5, 0xffe
+; VI-GISEL-NEXT:    s_or_b32 s2, s6, s2
+; VI-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s2, s5, s2
 ; VI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; VI-GISEL-NEXT:    s_lshr_b32 s7, s4, 8
-; VI-GISEL-NEXT:    s_bfe_u32 s8, s4, 0xb0014
-; VI-GISEL-NEXT:    s_and_b32 s7, s7, 0xffe
-; VI-GISEL-NEXT:    s_sub_i32 s9, 0x3f1, s8
-; VI-GISEL-NEXT:    s_or_b32 s5, s7, s5
-; VI-GISEL-NEXT:    v_med3_i32 v0, s9, 0, 13
-; VI-GISEL-NEXT:    s_or_b32 s7, s5, 0x1000
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s9, v0
-; VI-GISEL-NEXT:    s_lshr_b32 s10, s7, s9
-; VI-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s9, s7
+; VI-GISEL-NEXT:    s_sub_i32 s7, 1, s4
+; VI-GISEL-NEXT:    s_lshl_b32 s6, s4, 12
+; VI-GISEL-NEXT:    s_max_i32 s7, s7, 0
+; VI-GISEL-NEXT:    s_or_b32 s6, s2, s6
+; VI-GISEL-NEXT:    s_min_i32 s7, s7, 13
+; VI-GISEL-NEXT:    s_bitset1_b32 s2, 12
+; VI-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; VI-GISEL-NEXT:    s_lshr_b32 s8, s2, s7
+; VI-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; VI-GISEL-NEXT:    s_lshl_b32 s7, s8, s7
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s7, s2
+; VI-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s2, s8, s2
+; VI-GISEL-NEXT:    s_cmp_lt_i32 s4, 1
+; VI-GISEL-NEXT:    s_cselect_b32 s2, s2, s6
+; VI-GISEL-NEXT:    s_and_b32 s6, s2, 7
+; VI-GISEL-NEXT:    s_lshr_b32 s2, s2, 2
+; VI-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
 ; VI-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
-; VI-GISEL-NEXT:    s_addk_i32 s8, 0xfc10
-; VI-GISEL-NEXT:    s_lshl_b32 s9, s8, 12
-; VI-GISEL-NEXT:    s_or_b32 s7, s10, s7
-; VI-GISEL-NEXT:    s_or_b32 s9, s5, s9
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s8, 1
-; VI-GISEL-NEXT:    s_cselect_b32 s7, s7, s9
-; VI-GISEL-NEXT:    s_and_b32 s9, s7, 7
-; VI-GISEL-NEXT:    s_cmp_gt_i32 s9, 5
-; VI-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; VI-GISEL-NEXT:    s_cmp_eq_u32 s9, 3
-; VI-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; VI-GISEL-NEXT:    s_lshr_b32 s7, s7, 2
-; VI-GISEL-NEXT:    s_or_b32 s9, s9, s10
-; VI-GISEL-NEXT:    s_add_i32 s7, s7, s9
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s8, 31
-; VI-GISEL-NEXT:    s_cselect_b32 s7, s7, 0x7c00
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s6, 0x7c00
-; VI-GISEL-NEXT:    s_cmpk_eq_i32 s8, 0x40f
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s5, s7
-; VI-GISEL-NEXT:    s_lshr_b32 s4, s4, 16
-; VI-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
-; VI-GISEL-NEXT:    s_or_b32 s4, s4, s5
-; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
+; VI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s6, s7, s6
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT:    s_add_i32 s2, s2, s6
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s4, 30
+; VI-GISEL-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; VI-GISEL-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; VI-GISEL-NEXT:    s_cselect_b32 s2, s5, s2
+; VI-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
+; VI-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; VI-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT:    s_mov_b32 s2, -1
+; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; VI-GISEL-NEXT:    s_endpgm
 ;
@@ -855,60 +843,54 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
 ;
 ; GFX9-GISEL-LABEL: fptrunc_f64_to_f16:
 ; GFX9-GISEL:       ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX9-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-GISEL-NEXT:    s_mov_b32 s2, -1
-; GFX9-GISEL-NEXT:    s_mov_b32 s6, s2
-; GFX9-GISEL-NEXT:    s_mov_b32 s7, s3
+; GFX9-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT:    s_mov_b32 s4, s10
-; GFX9-GISEL-NEXT:    s_mov_b32 s5, s11
-; GFX9-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; GFX9-GISEL-NEXT:    s_mov_b32 s0, s8
-; GFX9-GISEL-NEXT:    s_mov_b32 s1, s9
-; GFX9-GISEL-NEXT:    s_movk_i32 s4, 0x7e00
-; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s5, v1
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s6, v0
-; GFX9-GISEL-NEXT:    s_and_b32 s7, s5, 0x1ff
-; GFX9-GISEL-NEXT:    s_or_b32 s6, s7, s6
+; GFX9-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX9-GISEL-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX9-GISEL-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX9-GISEL-NEXT:    s_addk_i32 s4, 0xfc10
+; GFX9-GISEL-NEXT:    s_and_b32 s5, s5, 0xffe
+; GFX9-GISEL-NEXT:    s_or_b32 s2, s6, s2
+; GFX9-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s2, s5, s2
+; GFX9-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX9-GISEL-NEXT:    s_sub_i32 s7, 1, s4
+; GFX9-GISEL-NEXT:    s_lshl_b32 s6, s4, 12
+; GFX9-GISEL-NEXT:    s_max_i32 s7, s7, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s6, s2, s6
+; GFX9-GISEL-NEXT:    s_min_i32 s7, s7, 13
+; GFX9-GISEL-NEXT:    s_bitset1_b32 s2, 12
+; GFX9-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX9-GISEL-NEXT:    s_lshr_b32 s8, s2, s7
+; GFX9-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX9-GISEL-NEXT:    s_lshl_b32 s7, s8, s7
+; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s7, s2
+; GFX9-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s2, s8, s2
+; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s4, 1
+; GFX9-GISEL-NEXT:    s_cselect_b32 s2, s2, s6
+; GFX9-GISEL-NEXT:    s_and_b32 s6, s2, 7
+; GFX9-GISEL-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX9-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX9-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
 ; GFX9-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s7, s5, 8
-; GFX9-GISEL-NEXT:    s_bfe_u32 s8, s5, 0xb0014
-; GFX9-GISEL-NEXT:    s_and_b32 s7, s7, 0xffe
-; GFX9-GISEL-NEXT:    s_sub_i32 s9, 0x3f1, s8
 ; GFX9-GISEL-NEXT:    s_or_b32 s6, s7, s6
-; GFX9-GISEL-NEXT:    v_med3_i32 v0, s9, 0, 13
-; GFX9-GISEL-NEXT:    s_or_b32 s7, s6, 0x1000
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s9, v0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s10, s7, s9
-; GFX9-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
-; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s9, s7
-; GFX9-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
-; GFX9-GISEL-NEXT:    s_addk_i32 s8, 0xfc10
-; GFX9-GISEL-NEXT:    s_lshl_b32 s9, s8, 12
-; GFX9-GISEL-NEXT:    s_or_b32 s7, s10, s7
-; GFX9-GISEL-NEXT:    s_or_b32 s9, s6, s9
-; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s8, 1
-; GFX9-GISEL-NEXT:    s_cselect_b32 s7, s7, s9
-; GFX9-GISEL-NEXT:    s_and_b32 s9, s7, 7
-; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s9, 5
-; GFX9-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX9-GISEL-NEXT:    s_cmp_eq_u32 s9, 3
-; GFX9-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s7, s7, 2
-; GFX9-GISEL-NEXT:    s_or_b32 s9, s9, s10
-; GFX9-GISEL-NEXT:    s_add_i32 s7, s7, s9
-; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s8, 31
-; GFX9-GISEL-NEXT:    s_cselect_b32 s7, s7, 0x7c00
 ; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
-; GFX9-GISEL-NEXT:    s_cselect_b32 s4, s4, 0x7c00
-; GFX9-GISEL-NEXT:    s_cmpk_eq_i32 s8, 0x40f
-; GFX9-GISEL-NEXT:    s_cselect_b32 s4, s4, s7
-; GFX9-GISEL-NEXT:    s_lshr_b32 s5, s5, 16
-; GFX9-GISEL-NEXT:    s_and_b32 s5, s5, 0x8000
-; GFX9-GISEL-NEXT:    s_or_b32 s4, s5, s4
-; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX9-GISEL-NEXT:    s_add_i32 s2, s2, s6
+; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX9-GISEL-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; GFX9-GISEL-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX9-GISEL-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX9-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX9-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX9-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX9-GISEL-NEXT:    s_endpgm
 ;
@@ -973,60 +955,54 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
 ;
 ; GFX950-GISEL-LABEL: fptrunc_f64_to_f16:
 ; GFX950-GISEL:       ; %bb.0: ; %entry
-; GFX950-GISEL-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX950-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; GFX950-GISEL-NEXT:    s_mov_b32 s2, -1
-; GFX950-GISEL-NEXT:    s_mov_b32 s6, s2
-; GFX950-GISEL-NEXT:    s_mov_b32 s7, s3
+; GFX950-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX950-GISEL-NEXT:    s_mov_b32 s4, s10
-; GFX950-GISEL-NEXT:    s_mov_b32 s5, s11
-; GFX950-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[4:7], 0
-; GFX950-GISEL-NEXT:    s_mov_b32 s0, s8
-; GFX950-GISEL-NEXT:    s_mov_b32 s1, s9
-; GFX950-GISEL-NEXT:    s_movk_i32 s4, 0x7e00
-; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s5, v1
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s6, v0
-; GFX950-GISEL-NEXT:    s_and_b32 s7, s5, 0x1ff
-; GFX950-GISEL-NEXT:    s_or_b32 s6, s7, s6
+; GFX950-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX950-GISEL-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX950-GISEL-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX950-GISEL-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX950-GISEL-NEXT:    s_addk_i32 s4, 0xfc10
+; GFX950-GISEL-NEXT:    s_and_b32 s5, s5, 0xffe
+; GFX950-GISEL-NEXT:    s_or_b32 s2, s6, s2
+; GFX950-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s2, s5, s2
+; GFX950-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX950-GISEL-NEXT:    s_sub_i32 s7, 1, s4
+; GFX950-GISEL-NEXT:    s_lshl_b32 s6, s4, 12
+; GFX950-GISEL-NEXT:    s_max_i32 s7, s7, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s6, s2, s6
+; GFX950-GISEL-NEXT:    s_min_i32 s7, s7, 13
+; GFX950-GISEL-NEXT:    s_bitset1_b32 s2, 12
+; GFX950-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX950-GISEL-NEXT:    s_lshr_b32 s8, s2, s7
+; GFX950-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX950-GISEL-NEXT:    s_lshl_b32 s7, s8, s7
+; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s7, s2
+; GFX950-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s2, s8, s2
+; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s4, 1
+; GFX950-GISEL-NEXT:    s_cselect_b32 s2, s2, s6
+; GFX950-GISEL-NEXT:    s_and_b32 s6, s2, 7
+; GFX950-GISEL-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX950-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX950-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
 ; GFX950-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s7, s5, 8
-; GFX950-GISEL-NEXT:    s_bfe_u32 s8, s5, 0xb0014
-; GFX950-GISEL-NEXT:    s_and_b32 s7, s7, 0xffe
-; GFX950-GISEL-NEXT:    s_sub_i32 s9, 0x3f1, s8
 ; GFX950-GISEL-NEXT:    s_or_b32 s6, s7, s6
-; GFX950-GISEL-NEXT:    v_med3_i32 v0, s9, 0, 13
-; GFX950-GISEL-NEXT:    s_or_b32 s7, s6, 0x1000
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s9, v0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s10, s7, s9
-; GFX950-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
-; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s9, s7
-; GFX950-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
-; GFX950-GISEL-NEXT:    s_addk_i32 s8, 0xfc10
-; GFX950-GISEL-NEXT:    s_lshl_b32 s9, s8, 12
-; GFX950-GISEL-NEXT:    s_or_b32 s7, s10, s7
-; GFX950-GISEL-NEXT:    s_or_b32 s9, s6, s9
-; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s8, 1
-; GFX950-GISEL-NEXT:    s_cselect_b32 s7, s7, s9
-; GFX950-GISEL-NEXT:    s_and_b32 s9, s7, 7
-; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s9, 5
-; GFX950-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX950-GISEL-NEXT:    s_cmp_eq_u32 s9, 3
-; GFX950-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s7, s7, 2
-; GFX950-GISEL-NEXT:    s_or_b32 s9, s9, s10
-; GFX950-GISEL-NEXT:    s_add_i32 s7, s7, s9
-; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s8, 31
-; GFX950-GISEL-NEXT:    s_cselect_b32 s7, s7, 0x7c00
 ; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
-; GFX950-GISEL-NEXT:    s_cselect_b32 s4, s4, 0x7c00
-; GFX950-GISEL-NEXT:    s_cmpk_eq_i32 s8, 0x40f
-; GFX950-GISEL-NEXT:    s_cselect_b32 s4, s4, s7
-; GFX950-GISEL-NEXT:    s_lshr_b32 s5, s5, 16
-; GFX950-GISEL-NEXT:    s_and_b32 s5, s5, 0x8000
-; GFX950-GISEL-NEXT:    s_or_b32 s4, s5, s4
-; GFX950-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX950-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX950-GISEL-NEXT:    s_add_i32 s2, s2, s6
+; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX950-GISEL-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; GFX950-GISEL-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX950-GISEL-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX950-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX950-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX950-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; GFX950-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX950-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX950-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX950-GISEL-NEXT:    s_endpgm
 ;
@@ -1167,135 +1143,117 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
 ; GFX11-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16:
 ; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-TRUE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], 0
-; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v1
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s4, s2, 0x1ff
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX11-GISEL-TRUE16-NEXT:    s_sub_i32 s5, 0x3f1, s4
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, s5, 0, 13
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX11-GISEL-TRUE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX11-GISEL-TRUE16-NEXT:    s_addk_i32 s4, 0xfc10
 ; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, s5
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s2, s6, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s2, s5, s2
 ; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_addk_i32 s4, 0xfc10
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s5, s9, s5
-; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_sub_i32 s6, 1, s4
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX11-GISEL-TRUE16-NEXT:    s_max_i32 s6, s6, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX11-GISEL-TRUE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s2, s2, s7
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s6, s9, s6
 ; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s6, s2, 7
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s8, 3
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s8, s8, s9
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s6, s7, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_add_i32 s5, s5, s8
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX11-GISEL-TRUE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s8, 0x7c00
+; GFX11-GISEL-TRUE16-NEXT:    s_add_i32 s2, s2, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, 0x7c00, s2
 ; GFX11-GISEL-TRUE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s3, s5
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s2, s2, 0x8000
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 16
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s2, s2, s3
-; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX11-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16:
 ; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-FAKE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], 0
-; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v1
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s4, s2, 0x1ff
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX11-GISEL-FAKE16-NEXT:    s_sub_i32 s5, 0x3f1, s4
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, s5, 0, 13
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX11-GISEL-FAKE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX11-GISEL-FAKE16-NEXT:    s_addk_i32 s4, 0xfc10
 ; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, s5
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s2, s6, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s2, s5, s2
 ; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_addk_i32 s4, 0xfc10
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s5, s9, s5
-; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_sub_i32 s6, 1, s4
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX11-GISEL-FAKE16-NEXT:    s_max_i32 s6, s6, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX11-GISEL-FAKE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s2, s2, s7
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s6, s9, s6
 ; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s6, s2, 7
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s8, 3
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s8, s8, s9
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s6, s7, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_add_i32 s5, s5, s8
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX11-GISEL-FAKE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s8, 0x7c00
+; GFX11-GISEL-FAKE16-NEXT:    s_add_i32 s2, s2, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, 0x7c00, s2
 ; GFX11-GISEL-FAKE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s3, s5
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s2, s2, 0x8000
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 16
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s2, s2, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16:
@@ -1444,68 +1402,59 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
 ; GFX1250-GISEL-TRUE16-NEXT:    v_nop
 ; GFX1250-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], null
-; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v1
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s4, s2, 0x1ff
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX1250-GISEL-TRUE16-NEXT:    s_sub_co_i32 s5, 0x3f1, s4
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_med3_i32 v0, s5, 0, 13
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX1250-GISEL-TRUE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX1250-GISEL-TRUE16-NEXT:    s_addk_co_i32 s4, 0xfc10
 ; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, s5
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s2, s6, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s2, s5, s2
 ; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_addk_co_i32 s4, 0xfc10
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s5, s9, s5
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_sub_co_i32 s6, 1, s4
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX1250-GISEL-TRUE16-NEXT:    s_max_i32 s6, s6, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX1250-GISEL-TRUE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s2, s2, s7
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s6, s9, s6
 ; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s6, s2, 7
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s8, 3
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s8, s8, s9
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s6, s7, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_add_co_i32 s5, s5, s8
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX1250-GISEL-TRUE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s8, 0x7c00
+; GFX1250-GISEL-TRUE16-NEXT:    s_add_co_i32 s2, s2, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, 0x7c00, s2
 ; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s4, 0x40f
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s3, s5
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s2, s2, 0x8000
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 16
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s2, s2, s3
-; GFX1250-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[4:7], null
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
 ; GFX1250-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16:
@@ -1514,68 +1463,59 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
 ; GFX1250-GISEL-FAKE16-NEXT:    v_nop
 ; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], null
-; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v1
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v0
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s4, s2, 0x1ff
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX1250-GISEL-FAKE16-NEXT:    s_sub_co_i32 s5, 0x3f1, s4
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_med3_i32 v0, s5, 0, 13
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX1250-GISEL-FAKE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX1250-GISEL-FAKE16-NEXT:    s_addk_co_i32 s4, 0xfc10
 ; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, s5
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s2, s6, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s2, s5, s2
 ; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_addk_co_i32 s4, 0xfc10
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s5, s9, s5
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_sub_co_i32 s6, 1, s4
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX1250-GISEL-FAKE16-NEXT:    s_max_i32 s6, s6, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX1250-GISEL-FAKE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s2, s2, s7
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s6, s9, s6
 ; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s6, s2, 7
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s8, 3
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s8, s8, s9
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s6, s7, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_add_co_i32 s5, s5, s8
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX1250-GISEL-FAKE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s8, 0x7c00
+; GFX1250-GISEL-FAKE16-NEXT:    s_add_co_i32 s2, s2, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, 0x7c00, s2
 ; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s4, 0x40f
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s3, s5
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s2, s2, 0x8000
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 16
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s2, s2, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1250-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[4:7], null
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
 ; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a) {
@@ -1609,20 +1549,14 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
 ; SI-GISEL-LABEL: fptrunc_f64_to_f16_afn:
 ; SI-GISEL:       ; %bb.0: ; %entry
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT:    s_mov_b32 s6, -1
-; SI-GISEL-NEXT:    s_mov_b32 s10, s6
-; SI-GISEL-NEXT:    s_mov_b32 s11, s7
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    s_mov_b32 s8, s2
-; SI-GISEL-NEXT:    s_mov_b32 s9, s3
-; SI-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; SI-GISEL-NEXT:    s_mov_b32 s4, s0
-; SI-GISEL-NEXT:    s_mov_b32 s5, s1
-; SI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; SI-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-GISEL-NEXT:    buffer_store_short v0, off, s[4:7], 0
+; SI-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: fptrunc_f64_to_f16_afn:
@@ -1647,20 +1581,14 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
 ; VI-GISEL-LABEL: fptrunc_f64_to_f16_afn:
 ; VI-GISEL:       ; %bb.0: ; %entry
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; VI-GISEL-NEXT:    s_mov_b32 s6, -1
-; VI-GISEL-NEXT:    s_mov_b32 s10, s6
-; VI-GISEL-NEXT:    s_mov_b32 s11, s7
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    s_mov_b32 s8, s2
-; VI-GISEL-NEXT:    s_mov_b32 s9, s3
-; VI-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; VI-GISEL-NEXT:    s_mov_b32 s4, s0
-; VI-GISEL-NEXT:    s_mov_b32 s5, s1
-; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; VI-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
+; VI-GISEL-NEXT:    s_mov_b32 s2, -1
+; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; VI-GISEL-NEXT:    buffer_store_short v0, off, s[4:7], 0
+; VI-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX9-SDAG-LABEL: fptrunc_f64_to_f16_afn:
@@ -1685,20 +1613,14 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
 ; GFX9-GISEL-LABEL: fptrunc_f64_to_f16_afn:
 ; GFX9-GISEL:       ; %bb.0: ; %entry
 ; GFX9-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; GFX9-GISEL-NEXT:    s_mov_b32 s6, -1
-; GFX9-GISEL-NEXT:    s_mov_b32 s10, s6
-; GFX9-GISEL-NEXT:    s_mov_b32 s11, s7
 ; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT:    s_mov_b32 s8, s2
-; GFX9-GISEL-NEXT:    s_mov_b32 s9, s3
-; GFX9-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; GFX9-GISEL-NEXT:    s_mov_b32 s4, s0
-; GFX9-GISEL-NEXT:    s_mov_b32 s5, s1
-; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX9-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
+; GFX9-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX9-GISEL-NEXT:    buffer_store_short v0, off, s[4:7], 0
+; GFX9-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX9-GISEL-NEXT:    s_endpgm
 ;
 ; GFX950-SDAG-LABEL: fptrunc_f64_to_f16_afn:
@@ -1723,20 +1645,14 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
 ; GFX950-GISEL-LABEL: fptrunc_f64_to_f16_afn:
 ; GFX950-GISEL:       ; %bb.0: ; %entry
 ; GFX950-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; GFX950-GISEL-NEXT:    s_mov_b32 s6, -1
-; GFX950-GISEL-NEXT:    s_mov_b32 s10, s6
-; GFX950-GISEL-NEXT:    s_mov_b32 s11, s7
 ; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX950-GISEL-NEXT:    s_mov_b32 s8, s2
-; GFX950-GISEL-NEXT:    s_mov_b32 s9, s3
-; GFX950-GISEL-NEXT:    buffer_load_dwordx2 v[0:1], off, s[8:11], 0
-; GFX950-GISEL-NEXT:    s_mov_b32 s4, s0
-; GFX950-GISEL-NEXT:    s_mov_b32 s5, s1
-; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
 ; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX950-GISEL-NEXT:    buffer_store_short v0, off, s[4:7], 0
+; GFX950-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX950-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; GFX950-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX950-GISEL-NEXT:    s_endpgm
 ;
 ; GFX11-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
@@ -1782,41 +1698,29 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
 ; GFX11-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
 ; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-TRUE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], 0
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-TRUE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
+; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX11-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
 ; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-FAKE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], 0
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-FAKE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[4:7], 0
+; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-SDAG-TRUE16-LABEL: fptrunc_f64_to_f16_afn:
@@ -1873,22 +1777,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
 ; GFX1250-GISEL-TRUE16-NEXT:    v_nop
 ; GFX1250-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], null
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX1250-GISEL-TRUE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[4:7], null
+; GFX1250-GISEL-TRUE16-NEXT:    s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
 ; GFX1250-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16_afn:
@@ -1897,22 +1797,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
 ; GFX1250-GISEL-FAKE16-NEXT:    v_nop
 ; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_load_b64 v[0:1], off, s[8:11], null
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX1250-GISEL-FAKE16-NEXT:    s_load_b64 s[2:3], s[2:3], 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[4:7], null
+; GFX1250-GISEL-FAKE16-NEXT:    s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], null
 ; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a) {
@@ -2339,103 +2235,99 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
 ;
 ; SI-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
 ; SI-GISEL:       ; %bb.0: ; %entry
-; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; SI-GISEL-NEXT:    s_mov_b32 s2, -1
-; SI-GISEL-NEXT:    s_mov_b32 s10, s2
-; SI-GISEL-NEXT:    s_mov_b32 s11, s3
+; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    s_mov_b32 s8, s6
-; SI-GISEL-NEXT:    s_mov_b32 s9, s7
-; SI-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; SI-GISEL-NEXT:    s_mov_b32 s0, s4
-; SI-GISEL-NEXT:    s_mov_b32 s1, s5
-; SI-GISEL-NEXT:    s_movk_i32 s6, 0x7e00
-; SI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s4, v3
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s5, v2
-; SI-GISEL-NEXT:    s_and_b32 s9, s4, 0x1ff
-; SI-GISEL-NEXT:    s_or_b32 s5, s9, s5
-; SI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; SI-GISEL-NEXT:    s_lshr_b32 s9, s4, 8
-; SI-GISEL-NEXT:    s_bfe_u32 s10, s4, 0xb0014
-; SI-GISEL-NEXT:    s_and_b32 s9, s9, 0xffe
-; SI-GISEL-NEXT:    s_sub_i32 s11, 0x3f1, s10
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
-; SI-GISEL-NEXT:    s_or_b32 s5, s9, s5
-; SI-GISEL-NEXT:    v_med3_i32 v0, s11, 0, 13
-; SI-GISEL-NEXT:    s_or_b32 s9, s5, 0x1000
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s11, v0
-; SI-GISEL-NEXT:    s_lshr_b32 s12, s9, s11
-; SI-GISEL-NEXT:    s_lshl_b32 s11, s12, s11
-; SI-GISEL-NEXT:    s_cmp_lg_u32 s11, s9
+; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; SI-GISEL-NEXT:    s_lshr_b32 s3, s5, 8
+; SI-GISEL-NEXT:    s_and_b32 s8, s5, 0x1ff
+; SI-GISEL-NEXT:    s_addk_i32 s2, 0xfc10
+; SI-GISEL-NEXT:    s_and_b32 s3, s3, 0xffe
+; SI-GISEL-NEXT:    s_or_b32 s4, s8, s4
+; SI-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s3, s3, s4
+; SI-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT:    s_sub_i32 s9, 1, s2
+; SI-GISEL-NEXT:    s_lshl_b32 s8, s2, 12
+; SI-GISEL-NEXT:    s_max_i32 s9, s9, 0
+; SI-GISEL-NEXT:    s_or_b32 s8, s3, s8
+; SI-GISEL-NEXT:    s_min_i32 s9, s9, 13
+; SI-GISEL-NEXT:    s_bitset1_b32 s3, 12
+; SI-GISEL-NEXT:    s_lshl_b32 s4, s4, 9
+; SI-GISEL-NEXT:    s_lshr_b32 s10, s3, s9
+; SI-GISEL-NEXT:    s_or_b32 s4, s4, 0x7c00
+; SI-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
+; SI-GISEL-NEXT:    s_cmp_lg_u32 s9, s3
+; SI-GISEL-NEXT:    s_cselect_b32 s3, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s3, s10, s3
+; SI-GISEL-NEXT:    s_cmp_lt_i32 s2, 1
+; SI-GISEL-NEXT:    s_cselect_b32 s3, s3, s8
+; SI-GISEL-NEXT:    s_and_b32 s8, s3, 7
+; SI-GISEL-NEXT:    s_lshr_b32 s3, s3, 2
+; SI-GISEL-NEXT:    s_cmp_eq_u32 s8, 3
 ; SI-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; SI-GISEL-NEXT:    s_addk_i32 s10, 0xfc10
-; SI-GISEL-NEXT:    s_lshl_b32 s11, s10, 12
-; SI-GISEL-NEXT:    s_or_b32 s9, s12, s9
-; SI-GISEL-NEXT:    s_or_b32 s11, s5, s11
-; SI-GISEL-NEXT:    s_cmp_lt_i32 s10, 1
-; SI-GISEL-NEXT:    s_cselect_b32 s9, s9, s11
-; SI-GISEL-NEXT:    s_and_b32 s11, s9, 7
-; SI-GISEL-NEXT:    s_cmp_gt_i32 s11, 5
-; SI-GISEL-NEXT:    s_cselect_b32 s12, 1, 0
-; SI-GISEL-NEXT:    s_cmp_eq_u32 s11, 3
-; SI-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; SI-GISEL-NEXT:    s_lshr_b32 s9, s9, 2
-; SI-GISEL-NEXT:    s_or_b32 s11, s11, s12
-; SI-GISEL-NEXT:    s_add_i32 s9, s9, s11
-; SI-GISEL-NEXT:    s_cmp_lt_i32 s10, 31
-; SI-GISEL-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; SI-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; SI-GISEL-NEXT:    s_cselect_b32 s5, s6, 0x7c00
-; SI-GISEL-NEXT:    s_cmpk_eq_i32 s10, 0x40f
-; SI-GISEL-NEXT:    s_cselect_b32 s5, s5, s9
-; SI-GISEL-NEXT:    s_lshr_b32 s4, s4, 16
-; SI-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s7, v1
+; SI-GISEL-NEXT:    s_cmp_gt_i32 s8, 5
+; SI-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s8, s9, s8
+; SI-GISEL-NEXT:    s_cmp_lg_u32 s8, 0
+; SI-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; SI-GISEL-NEXT:    s_add_i32 s3, s3, s8
+; SI-GISEL-NEXT:    s_cmp_gt_i32 s2, 30
+; SI-GISEL-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; SI-GISEL-NEXT:    s_cmpk_eq_i32 s2, 0x40f
+; SI-GISEL-NEXT:    s_cselect_b32 s2, s4, s3
+; SI-GISEL-NEXT:    s_lshr_b32 s3, s5, 16
+; SI-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; SI-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; SI-GISEL-NEXT:    s_bfe_u32 s3, s7, 0xb0014
+; SI-GISEL-NEXT:    s_lshr_b32 s4, s7, 8
+; SI-GISEL-NEXT:    s_addk_i32 s3, 0xfc10
+; SI-GISEL-NEXT:    s_and_b32 s4, s4, 0xffe
+; SI-GISEL-NEXT:    s_and_b32 s5, s7, 0x1ff
+; SI-GISEL-NEXT:    s_or_b32 s5, s5, s6
+; SI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
 ; SI-GISEL-NEXT:    s_or_b32 s4, s4, s5
-; SI-GISEL-NEXT:    s_and_b32 s9, s7, 0x1ff
-; SI-GISEL-NEXT:    s_lshl_b32 s4, s4, 16
-; SI-GISEL-NEXT:    s_or_b32 s5, s9, s8
 ; SI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; SI-GISEL-NEXT:    s_lshr_b32 s8, s7, 8
-; SI-GISEL-NEXT:    s_bfe_u32 s9, s7, 0xb0014
-; SI-GISEL-NEXT:    s_and_b32 s8, s8, 0xffe
-; SI-GISEL-NEXT:    s_sub_i32 s10, 0x3f1, s9
-; SI-GISEL-NEXT:    s_or_b32 s5, s8, s5
-; SI-GISEL-NEXT:    v_med3_i32 v0, s10, 0, 13
-; SI-GISEL-NEXT:    s_or_b32 s8, s5, 0x1000
-; SI-GISEL-NEXT:    v_readfirstlane_b32 s10, v0
-; SI-GISEL-NEXT:    s_lshr_b32 s11, s8, s10
-; SI-GISEL-NEXT:    s_lshl_b32 s10, s11, s10
-; SI-GISEL-NEXT:    s_cmp_lg_u32 s10, s8
+; SI-GISEL-NEXT:    s_sub_i32 s8, 1, s3
+; SI-GISEL-NEXT:    s_lshl_b32 s6, s3, 12
+; SI-GISEL-NEXT:    s_max_i32 s8, s8, 0
+; SI-GISEL-NEXT:    s_or_b32 s6, s4, s6
+; SI-GISEL-NEXT:    s_min_i32 s8, s8, 13
+; SI-GISEL-NEXT:    s_bitset1_b32 s4, 12
+; SI-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; SI-GISEL-NEXT:    s_lshr_b32 s9, s4, s8
+; SI-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; SI-GISEL-NEXT:    s_lshl_b32 s8, s9, s8
+; SI-GISEL-NEXT:    s_cmp_lg_u32 s8, s4
+; SI-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s4, s9, s4
+; SI-GISEL-NEXT:    s_cmp_lt_i32 s3, 1
+; SI-GISEL-NEXT:    s_cselect_b32 s4, s4, s6
+; SI-GISEL-NEXT:    s_and_b32 s6, s4, 7
+; SI-GISEL-NEXT:    s_lshr_b32 s4, s4, 2
+; SI-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
 ; SI-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
-; SI-GISEL-NEXT:    s_addk_i32 s9, 0xfc10
-; SI-GISEL-NEXT:    s_lshl_b32 s10, s9, 12
-; SI-GISEL-NEXT:    s_or_b32 s8, s11, s8
-; SI-GISEL-NEXT:    s_or_b32 s10, s5, s10
-; SI-GISEL-NEXT:    s_cmp_lt_i32 s9, 1
-; SI-GISEL-NEXT:    s_cselect_b32 s8, s8, s10
-; SI-GISEL-NEXT:    s_and_b32 s10, s8, 7
-; SI-GISEL-NEXT:    s_cmp_gt_i32 s10, 5
-; SI-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; SI-GISEL-NEXT:    s_cmp_eq_u32 s10, 3
-; SI-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; SI-GISEL-NEXT:    s_lshr_b32 s8, s8, 2
-; SI-GISEL-NEXT:    s_or_b32 s10, s10, s11
-; SI-GISEL-NEXT:    s_add_i32 s8, s8, s10
-; SI-GISEL-NEXT:    s_cmp_lt_i32 s9, 31
-; SI-GISEL-NEXT:    s_cselect_b32 s8, s8, 0x7c00
-; SI-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; SI-GISEL-NEXT:    s_cselect_b32 s5, s6, 0x7c00
-; SI-GISEL-NEXT:    s_cmpk_eq_i32 s9, 0x40f
-; SI-GISEL-NEXT:    s_cselect_b32 s5, s5, s8
-; SI-GISEL-NEXT:    s_lshr_b32 s6, s7, 16
-; SI-GISEL-NEXT:    s_and_b32 s6, s6, 0x8000
-; SI-GISEL-NEXT:    s_or_b32 s5, s6, s5
-; SI-GISEL-NEXT:    s_and_b32 s5, s5, 0xffff
-; SI-GISEL-NEXT:    s_or_b32 s4, s5, s4
-; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; SI-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
+; SI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT:    s_or_b32 s6, s8, s6
+; SI-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
+; SI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; SI-GISEL-NEXT:    s_add_i32 s4, s4, s6
+; SI-GISEL-NEXT:    s_cmp_gt_i32 s3, 30
+; SI-GISEL-NEXT:    s_cselect_b32 s4, 0x7c00, s4
+; SI-GISEL-NEXT:    s_cmpk_eq_i32 s3, 0x40f
+; SI-GISEL-NEXT:    s_cselect_b32 s3, s5, s4
+; SI-GISEL-NEXT:    s_lshr_b32 s4, s7, 16
+; SI-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
+; SI-GISEL-NEXT:    s_or_b32 s3, s4, s3
+; SI-GISEL-NEXT:    s_and_b32 s3, s3, 0xffff
+; SI-GISEL-NEXT:    s_and_b32 s2, s2, 0xffff
+; SI-GISEL-NEXT:    s_lshl_b32 s3, s3, 16
+; SI-GISEL-NEXT:    s_or_b32 s2, s2, s3
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
@@ -2543,103 +2435,99 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
 ;
 ; VI-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
 ; VI-GISEL:       ; %bb.0: ; %entry
-; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x24
-; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; VI-GISEL-NEXT:    s_mov_b32 s2, -1
-; VI-GISEL-NEXT:    s_mov_b32 s10, s2
-; VI-GISEL-NEXT:    s_mov_b32 s11, s3
+; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    s_mov_b32 s8, s6
-; VI-GISEL-NEXT:    s_mov_b32 s9, s7
-; VI-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; VI-GISEL-NEXT:    s_mov_b32 s0, s4
-; VI-GISEL-NEXT:    s_mov_b32 s1, s5
-; VI-GISEL-NEXT:    s_movk_i32 s6, 0x7e00
-; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s4, v3
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s5, v2
-; VI-GISEL-NEXT:    s_and_b32 s9, s4, 0x1ff
-; VI-GISEL-NEXT:    s_or_b32 s5, s9, s5
-; VI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; VI-GISEL-NEXT:    s_lshr_b32 s9, s4, 8
-; VI-GISEL-NEXT:    s_bfe_u32 s10, s4, 0xb0014
-; VI-GISEL-NEXT:    s_and_b32 s9, s9, 0xffe
-; VI-GISEL-NEXT:    s_sub_i32 s11, 0x3f1, s10
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
-; VI-GISEL-NEXT:    s_or_b32 s5, s9, s5
-; VI-GISEL-NEXT:    v_med3_i32 v0, s11, 0, 13
-; VI-GISEL-NEXT:    s_or_b32 s9, s5, 0x1000
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s11, v0
-; VI-GISEL-NEXT:    s_lshr_b32 s12, s9, s11
-; VI-GISEL-NEXT:    s_lshl_b32 s11, s12, s11
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s11, s9
+; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; VI-GISEL-NEXT:    s_lshr_b32 s3, s5, 8
+; VI-GISEL-NEXT:    s_and_b32 s8, s5, 0x1ff
+; VI-GISEL-NEXT:    s_addk_i32 s2, 0xfc10
+; VI-GISEL-NEXT:    s_and_b32 s3, s3, 0xffe
+; VI-GISEL-NEXT:    s_or_b32 s4, s8, s4
+; VI-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s3, s3, s4
+; VI-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT:    s_sub_i32 s9, 1, s2
+; VI-GISEL-NEXT:    s_lshl_b32 s8, s2, 12
+; VI-GISEL-NEXT:    s_max_i32 s9, s9, 0
+; VI-GISEL-NEXT:    s_or_b32 s8, s3, s8
+; VI-GISEL-NEXT:    s_min_i32 s9, s9, 13
+; VI-GISEL-NEXT:    s_bitset1_b32 s3, 12
+; VI-GISEL-NEXT:    s_lshl_b32 s4, s4, 9
+; VI-GISEL-NEXT:    s_lshr_b32 s10, s3, s9
+; VI-GISEL-NEXT:    s_or_b32 s4, s4, 0x7c00
+; VI-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s9, s3
+; VI-GISEL-NEXT:    s_cselect_b32 s3, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s3, s10, s3
+; VI-GISEL-NEXT:    s_cmp_lt_i32 s2, 1
+; VI-GISEL-NEXT:    s_cselect_b32 s3, s3, s8
+; VI-GISEL-NEXT:    s_and_b32 s8, s3, 7
+; VI-GISEL-NEXT:    s_lshr_b32 s3, s3, 2
+; VI-GISEL-NEXT:    s_cmp_eq_u32 s8, 3
 ; VI-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; VI-GISEL-NEXT:    s_addk_i32 s10, 0xfc10
-; VI-GISEL-NEXT:    s_lshl_b32 s11, s10, 12
-; VI-GISEL-NEXT:    s_or_b32 s9, s12, s9
-; VI-GISEL-NEXT:    s_or_b32 s11, s5, s11
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s10, 1
-; VI-GISEL-NEXT:    s_cselect_b32 s9, s9, s11
-; VI-GISEL-NEXT:    s_and_b32 s11, s9, 7
-; VI-GISEL-NEXT:    s_cmp_gt_i32 s11, 5
-; VI-GISEL-NEXT:    s_cselect_b32 s12, 1, 0
-; VI-GISEL-NEXT:    s_cmp_eq_u32 s11, 3
-; VI-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; VI-GISEL-NEXT:    s_lshr_b32 s9, s9, 2
-; VI-GISEL-NEXT:    s_or_b32 s11, s11, s12
-; VI-GISEL-NEXT:    s_add_i32 s9, s9, s11
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s10, 31
-; VI-GISEL-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s6, 0x7c00
-; VI-GISEL-NEXT:    s_cmpk_eq_i32 s10, 0x40f
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s5, s9
-; VI-GISEL-NEXT:    s_lshr_b32 s4, s4, 16
-; VI-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s7, v1
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s8, 5
+; VI-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s8, s9, s8
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s8, 0
+; VI-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; VI-GISEL-NEXT:    s_add_i32 s3, s3, s8
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s2, 30
+; VI-GISEL-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; VI-GISEL-NEXT:    s_cmpk_eq_i32 s2, 0x40f
+; VI-GISEL-NEXT:    s_cselect_b32 s2, s4, s3
+; VI-GISEL-NEXT:    s_lshr_b32 s3, s5, 16
+; VI-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; VI-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; VI-GISEL-NEXT:    s_bfe_u32 s3, s7, 0xb0014
+; VI-GISEL-NEXT:    s_lshr_b32 s4, s7, 8
+; VI-GISEL-NEXT:    s_addk_i32 s3, 0xfc10
+; VI-GISEL-NEXT:    s_and_b32 s4, s4, 0xffe
+; VI-GISEL-NEXT:    s_and_b32 s5, s7, 0x1ff
+; VI-GISEL-NEXT:    s_or_b32 s5, s5, s6
+; VI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
 ; VI-GISEL-NEXT:    s_or_b32 s4, s4, s5
-; VI-GISEL-NEXT:    s_and_b32 s9, s7, 0x1ff
-; VI-GISEL-NEXT:    s_lshl_b32 s4, s4, 16
-; VI-GISEL-NEXT:    s_or_b32 s5, s9, s8
 ; VI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; VI-GISEL-NEXT:    s_lshr_b32 s8, s7, 8
-; VI-GISEL-NEXT:    s_bfe_u32 s9, s7, 0xb0014
-; VI-GISEL-NEXT:    s_and_b32 s8, s8, 0xffe
-; VI-GISEL-NEXT:    s_sub_i32 s10, 0x3f1, s9
-; VI-GISEL-NEXT:    s_or_b32 s5, s8, s5
-; VI-GISEL-NEXT:    v_med3_i32 v0, s10, 0, 13
-; VI-GISEL-NEXT:    s_or_b32 s8, s5, 0x1000
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s10, v0
-; VI-GISEL-NEXT:    s_lshr_b32 s11, s8, s10
-; VI-GISEL-NEXT:    s_lshl_b32 s10, s11, s10
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s10, s8
+; VI-GISEL-NEXT:    s_sub_i32 s8, 1, s3
+; VI-GISEL-NEXT:    s_lshl_b32 s6, s3, 12
+; VI-GISEL-NEXT:    s_max_i32 s8, s8, 0
+; VI-GISEL-NEXT:    s_or_b32 s6, s4, s6
+; VI-GISEL-NEXT:    s_min_i32 s8, s8, 13
+; VI-GISEL-NEXT:    s_bitset1_b32 s4, 12
+; VI-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; VI-GISEL-NEXT:    s_lshr_b32 s9, s4, s8
+; VI-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; VI-GISEL-NEXT:    s_lshl_b32 s8, s9, s8
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s8, s4
+; VI-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s4, s9, s4
+; VI-GISEL-NEXT:    s_cmp_lt_i32 s3, 1
+; VI-GISEL-NEXT:    s_cselect_b32 s4, s4, s6
+; VI-GISEL-NEXT:    s_and_b32 s6, s4, 7
+; VI-GISEL-NEXT:    s_lshr_b32 s4, s4, 2
+; VI-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
 ; VI-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
-; VI-GISEL-NEXT:    s_addk_i32 s9, 0xfc10
-; VI-GISEL-NEXT:    s_lshl_b32 s10, s9, 12
-; VI-GISEL-NEXT:    s_or_b32 s8, s11, s8
-; VI-GISEL-NEXT:    s_or_b32 s10, s5, s10
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s9, 1
-; VI-GISEL-NEXT:    s_cselect_b32 s8, s8, s10
-; VI-GISEL-NEXT:    s_and_b32 s10, s8, 7
-; VI-GISEL-NEXT:    s_cmp_gt_i32 s10, 5
-; VI-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; VI-GISEL-NEXT:    s_cmp_eq_u32 s10, 3
-; VI-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; VI-GISEL-NEXT:    s_lshr_b32 s8, s8, 2
-; VI-GISEL-NEXT:    s_or_b32 s10, s10, s11
-; VI-GISEL-NEXT:    s_add_i32 s8, s8, s10
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s9, 31
-; VI-GISEL-NEXT:    s_cselect_b32 s8, s8, 0x7c00
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s6, 0x7c00
-; VI-GISEL-NEXT:    s_cmpk_eq_i32 s9, 0x40f
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s5, s8
-; VI-GISEL-NEXT:    s_lshr_b32 s6, s7, 16
-; VI-GISEL-NEXT:    s_and_b32 s6, s6, 0x8000
-; VI-GISEL-NEXT:    s_or_b32 s5, s6, s5
-; VI-GISEL-NEXT:    s_and_b32 s5, s5, 0xffff
-; VI-GISEL-NEXT:    s_or_b32 s4, s5, s4
-; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
+; VI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s6, s8, s6
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT:    s_add_i32 s4, s4, s6
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s3, 30
+; VI-GISEL-NEXT:    s_cselect_b32 s4, 0x7c00, s4
+; VI-GISEL-NEXT:    s_cmpk_eq_i32 s3, 0x40f
+; VI-GISEL-NEXT:    s_cselect_b32 s3, s5, s4
+; VI-GISEL-NEXT:    s_lshr_b32 s4, s7, 16
+; VI-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
+; VI-GISEL-NEXT:    s_or_b32 s3, s4, s3
+; VI-GISEL-NEXT:    s_and_b32 s3, s3, 0xffff
+; VI-GISEL-NEXT:    s_and_b32 s2, s2, 0xffff
+; VI-GISEL-NEXT:    s_lshl_b32 s3, s3, 16
+; VI-GISEL-NEXT:    s_or_b32 s2, s2, s3
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT:    s_mov_b32 s2, -1
+; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; VI-GISEL-NEXT:    s_endpgm
 ;
@@ -2745,101 +2633,96 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
 ;
 ; GFX9-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
 ; GFX9-GISEL:       ; %bb.0: ; %entry
-; GFX9-GISEL-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX9-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; GFX9-GISEL-NEXT:    s_mov_b32 s2, -1
-; GFX9-GISEL-NEXT:    s_mov_b32 s6, s2
-; GFX9-GISEL-NEXT:    s_mov_b32 s7, s3
+; GFX9-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT:    s_mov_b32 s4, s10
-; GFX9-GISEL-NEXT:    s_mov_b32 s5, s11
-; GFX9-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; GFX9-GISEL-NEXT:    s_mov_b32 s1, s9
-; GFX9-GISEL-NEXT:    s_mov_b32 s0, s8
-; GFX9-GISEL-NEXT:    s_movk_i32 s4, 0x7e00
-; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s5, v3
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s6, v2
-; GFX9-GISEL-NEXT:    s_and_b32 s9, s5, 0x1ff
-; GFX9-GISEL-NEXT:    s_or_b32 s6, s9, s6
-; GFX9-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s9, s5, 8
-; GFX9-GISEL-NEXT:    s_bfe_u32 s10, s5, 0xb0014
-; GFX9-GISEL-NEXT:    s_and_b32 s9, s9, 0xffe
-; GFX9-GISEL-NEXT:    s_sub_i32 s11, 0x3f1, s10
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX9-GISEL-NEXT:    s_or_b32 s6, s9, s6
-; GFX9-GISEL-NEXT:    v_med3_i32 v0, s11, 0, 13
-; GFX9-GISEL-NEXT:    s_or_b32 s9, s6, 0x1000
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s11, v0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s12, s9, s11
-; GFX9-GISEL-NEXT:    s_lshl_b32 s11, s12, s11
-; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s11, s9
+; GFX9-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; GFX9-GISEL-NEXT:    s_lshr_b32 s3, s5, 8
+; GFX9-GISEL-NEXT:    s_and_b32 s8, s5, 0x1ff
+; GFX9-GISEL-NEXT:    s_addk_i32 s2, 0xfc10
+; GFX9-GISEL-NEXT:    s_and_b32 s3, s3, 0xffe
+; GFX9-GISEL-NEXT:    s_or_b32 s4, s8, s4
+; GFX9-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s3, s3, s4
+; GFX9-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT:    s_sub_i32 s9, 1, s2
+; GFX9-GISEL-NEXT:    s_lshl_b32 s8, s2, 12
+; GFX9-GISEL-NEXT:    s_max_i32 s9, s9, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s8, s3, s8
+; GFX9-GISEL-NEXT:    s_min_i32 s9, s9, 13
+; GFX9-GISEL-NEXT:    s_bitset1_b32 s3, 12
+; GFX9-GISEL-NEXT:    s_lshl_b32 s4, s4, 9
+; GFX9-GISEL-NEXT:    s_lshr_b32 s10, s3, s9
+; GFX9-GISEL-NEXT:    s_or_b32 s4, s4, 0x7c00
+; GFX9-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
+; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s9, s3
+; GFX9-GISEL-NEXT:    s_cselect_b32 s3, 1, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s3, s10, s3
+; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s2, 1
+; GFX9-GISEL-NEXT:    s_cselect_b32 s3, s3, s8
+; GFX9-GISEL-NEXT:    s_and_b32 s8, s3, 7
+; GFX9-GISEL-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX9-GISEL-NEXT:    s_cmp_eq_u32 s8, 3
 ; GFX9-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX9-GISEL-NEXT:    s_addk_i32 s10, 0xfc10
-; GFX9-GISEL-NEXT:    s_lshl_b32 s11, s10, 12
-; GFX9-GISEL-NEXT:    s_or_b32 s9, s12, s9
-; GFX9-GISEL-NEXT:    s_or_b32 s11, s6, s11
-; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s10, 1
-; GFX9-GISEL-NEXT:    s_cselect_b32 s9, s9, s11
-; GFX9-GISEL-NEXT:    s_and_b32 s11, s9, 7
-; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s11, 5
-; GFX9-GISEL-NEXT:    s_cselect_b32 s12, 1, 0
-; GFX9-GISEL-NEXT:    s_cmp_eq_u32 s11, 3
-; GFX9-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s9, s9, 2
-; GFX9-GISEL-NEXT:    s_or_b32 s11, s11, s12
-; GFX9-GISEL-NEXT:    s_add_i32 s9, s9, s11
-; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s10, 31
-; GFX9-GISEL-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
-; GFX9-GISEL-NEXT:    s_cselect_b32 s6, s4, 0x7c00
-; GFX9-GISEL-NEXT:    s_cmpk_eq_i32 s10, 0x40f
-; GFX9-GISEL-NEXT:    s_cselect_b32 s6, s6, s9
-; GFX9-GISEL-NEXT:    s_lshr_b32 s5, s5, 16
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s7, v1
-; GFX9-GISEL-NEXT:    s_and_b32 s5, s5, 0x8000
-; GFX9-GISEL-NEXT:    s_and_b32 s9, s7, 0x1ff
+; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s8, 5
+; GFX9-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s8, s9, s8
+; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX9-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX9-GISEL-NEXT:    s_add_i32 s3, s3, s8
+; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX9-GISEL-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX9-GISEL-NEXT:    s_cmpk_eq_i32 s2, 0x40f
+; GFX9-GISEL-NEXT:    s_cselect_b32 s2, s4, s3
+; GFX9-GISEL-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX9-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX9-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; GFX9-GISEL-NEXT:    s_bfe_u32 s3, s7, 0xb0014
+; GFX9-GISEL-NEXT:    s_lshr_b32 s4, s7, 8
+; GFX9-GISEL-NEXT:    s_addk_i32 s3, 0xfc10
+; GFX9-GISEL-NEXT:    s_and_b32 s4, s4, 0xffe
+; GFX9-GISEL-NEXT:    s_and_b32 s5, s7, 0x1ff
 ; GFX9-GISEL-NEXT:    s_or_b32 s5, s5, s6
-; GFX9-GISEL-NEXT:    s_or_b32 s6, s9, s8
+; GFX9-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s4, s4, s5
+; GFX9-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX9-GISEL-NEXT:    s_sub_i32 s8, 1, s3
+; GFX9-GISEL-NEXT:    s_lshl_b32 s6, s3, 12
+; GFX9-GISEL-NEXT:    s_max_i32 s8, s8, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s6, s4, s6
+; GFX9-GISEL-NEXT:    s_min_i32 s8, s8, 13
+; GFX9-GISEL-NEXT:    s_bitset1_b32 s4, 12
+; GFX9-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX9-GISEL-NEXT:    s_lshr_b32 s9, s4, s8
+; GFX9-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX9-GISEL-NEXT:    s_lshl_b32 s8, s9, s8
+; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s8, s4
+; GFX9-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX9-GISEL-NEXT:    s_or_b32 s4, s9, s4
+; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s3, 1
+; GFX9-GISEL-NEXT:    s_cselect_b32 s4, s4, s6
+; GFX9-GISEL-NEXT:    s_and_b32 s6, s4, 7
+; GFX9-GISEL-NEXT:    s_lshr_b32 s4, s4, 2
+; GFX9-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX9-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
 ; GFX9-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s8, s7, 8
-; GFX9-GISEL-NEXT:    s_bfe_u32 s9, s7, 0xb0014
-; GFX9-GISEL-NEXT:    s_and_b32 s8, s8, 0xffe
-; GFX9-GISEL-NEXT:    s_sub_i32 s10, 0x3f1, s9
 ; GFX9-GISEL-NEXT:    s_or_b32 s6, s8, s6
-; GFX9-GISEL-NEXT:    v_med3_i32 v0, s10, 0, 13
-; GFX9-GISEL-NEXT:    s_or_b32 s8, s6, 0x1000
-; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s10, v0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s11, s8, s10
-; GFX9-GISEL-NEXT:    s_lshl_b32 s10, s11, s10
-; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s10, s8
-; GFX9-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX9-GISEL-NEXT:    s_addk_i32 s9, 0xfc10
-; GFX9-GISEL-NEXT:    s_lshl_b32 s10, s9, 12
-; GFX9-GISEL-NEXT:    s_or_b32 s8, s11, s8
-; GFX9-GISEL-NEXT:    s_or_b32 s10, s6, s10
-; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s9, 1
-; GFX9-GISEL-NEXT:    s_cselect_b32 s8, s8, s10
-; GFX9-GISEL-NEXT:    s_and_b32 s10, s8, 7
-; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s10, 5
-; GFX9-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX9-GISEL-NEXT:    s_cmp_eq_u32 s10, 3
-; GFX9-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX9-GISEL-NEXT:    s_lshr_b32 s8, s8, 2
-; GFX9-GISEL-NEXT:    s_or_b32 s10, s10, s11
-; GFX9-GISEL-NEXT:    s_add_i32 s8, s8, s10
-; GFX9-GISEL-NEXT:    s_cmp_lt_i32 s9, 31
-; GFX9-GISEL-NEXT:    s_cselect_b32 s8, s8, 0x7c00
 ; GFX9-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
-; GFX9-GISEL-NEXT:    s_cselect_b32 s4, s4, 0x7c00
-; GFX9-GISEL-NEXT:    s_cmpk_eq_i32 s9, 0x40f
-; GFX9-GISEL-NEXT:    s_cselect_b32 s4, s4, s8
-; GFX9-GISEL-NEXT:    s_lshr_b32 s6, s7, 16
-; GFX9-GISEL-NEXT:    s_and_b32 s6, s6, 0x8000
-; GFX9-GISEL-NEXT:    s_or_b32 s4, s6, s4
-; GFX9-GISEL-NEXT:    s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX9-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX9-GISEL-NEXT:    s_add_i32 s4, s4, s6
+; GFX9-GISEL-NEXT:    s_cmp_gt_i32 s3, 30
+; GFX9-GISEL-NEXT:    s_cselect_b32 s4, 0x7c00, s4
+; GFX9-GISEL-NEXT:    s_cmpk_eq_i32 s3, 0x40f
+; GFX9-GISEL-NEXT:    s_cselect_b32 s3, s5, s4
+; GFX9-GISEL-NEXT:    s_lshr_b32 s4, s7, 16
+; GFX9-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
+; GFX9-GISEL-NEXT:    s_or_b32 s3, s4, s3
+; GFX9-GISEL-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX9-GISEL-NEXT:    s_endpgm
 ;
@@ -2945,101 +2828,96 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
 ;
 ; GFX950-GISEL-LABEL: fptrunc_v2f64_to_v2f16:
 ; GFX950-GISEL:       ; %bb.0: ; %entry
-; GFX950-GISEL-NEXT:    s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX950-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; GFX950-GISEL-NEXT:    s_mov_b32 s2, -1
-; GFX950-GISEL-NEXT:    s_mov_b32 s6, s2
-; GFX950-GISEL-NEXT:    s_mov_b32 s7, s3
+; GFX950-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX950-GISEL-NEXT:    s_mov_b32 s4, s10
-; GFX950-GISEL-NEXT:    s_mov_b32 s5, s11
-; GFX950-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
-; GFX950-GISEL-NEXT:    s_mov_b32 s1, s9
-; GFX950-GISEL-NEXT:    s_mov_b32 s0, s8
-; GFX950-GISEL-NEXT:    s_movk_i32 s4, 0x7e00
-; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s5, v3
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s6, v2
-; GFX950-GISEL-NEXT:    s_and_b32 s9, s5, 0x1ff
-; GFX950-GISEL-NEXT:    s_or_b32 s6, s9, s6
-; GFX950-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s9, s5, 8
-; GFX950-GISEL-NEXT:    s_bfe_u32 s10, s5, 0xb0014
-; GFX950-GISEL-NEXT:    s_and_b32 s9, s9, 0xffe
-; GFX950-GISEL-NEXT:    s_sub_i32 s11, 0x3f1, s10
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
-; GFX950-GISEL-NEXT:    s_or_b32 s6, s9, s6
-; GFX950-GISEL-NEXT:    v_med3_i32 v0, s11, 0, 13
-; GFX950-GISEL-NEXT:    s_or_b32 s9, s6, 0x1000
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s11, v0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s12, s9, s11
-; GFX950-GISEL-NEXT:    s_lshl_b32 s11, s12, s11
-; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s11, s9
+; GFX950-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX950-GISEL-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; GFX950-GISEL-NEXT:    s_lshr_b32 s3, s5, 8
+; GFX950-GISEL-NEXT:    s_and_b32 s8, s5, 0x1ff
+; GFX950-GISEL-NEXT:    s_addk_i32 s2, 0xfc10
+; GFX950-GISEL-NEXT:    s_and_b32 s3, s3, 0xffe
+; GFX950-GISEL-NEXT:    s_or_b32 s4, s8, s4
+; GFX950-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s3, s3, s4
+; GFX950-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX950-GISEL-NEXT:    s_sub_i32 s9, 1, s2
+; GFX950-GISEL-NEXT:    s_lshl_b32 s8, s2, 12
+; GFX950-GISEL-NEXT:    s_max_i32 s9, s9, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s8, s3, s8
+; GFX950-GISEL-NEXT:    s_min_i32 s9, s9, 13
+; GFX950-GISEL-NEXT:    s_bitset1_b32 s3, 12
+; GFX950-GISEL-NEXT:    s_lshl_b32 s4, s4, 9
+; GFX950-GISEL-NEXT:    s_lshr_b32 s10, s3, s9
+; GFX950-GISEL-NEXT:    s_or_b32 s4, s4, 0x7c00
+; GFX950-GISEL-NEXT:    s_lshl_b32 s9, s10, s9
+; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s9, s3
+; GFX950-GISEL-NEXT:    s_cselect_b32 s3, 1, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s3, s10, s3
+; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s2, 1
+; GFX950-GISEL-NEXT:    s_cselect_b32 s3, s3, s8
+; GFX950-GISEL-NEXT:    s_and_b32 s8, s3, 7
+; GFX950-GISEL-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX950-GISEL-NEXT:    s_cmp_eq_u32 s8, 3
 ; GFX950-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX950-GISEL-NEXT:    s_addk_i32 s10, 0xfc10
-; GFX950-GISEL-NEXT:    s_lshl_b32 s11, s10, 12
-; GFX950-GISEL-NEXT:    s_or_b32 s9, s12, s9
-; GFX950-GISEL-NEXT:    s_or_b32 s11, s6, s11
-; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s10, 1
-; GFX950-GISEL-NEXT:    s_cselect_b32 s9, s9, s11
-; GFX950-GISEL-NEXT:    s_and_b32 s11, s9, 7
-; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s11, 5
-; GFX950-GISEL-NEXT:    s_cselect_b32 s12, 1, 0
-; GFX950-GISEL-NEXT:    s_cmp_eq_u32 s11, 3
-; GFX950-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s9, s9, 2
-; GFX950-GISEL-NEXT:    s_or_b32 s11, s11, s12
-; GFX950-GISEL-NEXT:    s_add_i32 s9, s9, s11
-; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s10, 31
-; GFX950-GISEL-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
-; GFX950-GISEL-NEXT:    s_cselect_b32 s6, s4, 0x7c00
-; GFX950-GISEL-NEXT:    s_cmpk_eq_i32 s10, 0x40f
-; GFX950-GISEL-NEXT:    s_cselect_b32 s6, s6, s9
-; GFX950-GISEL-NEXT:    s_lshr_b32 s5, s5, 16
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s7, v1
-; GFX950-GISEL-NEXT:    s_and_b32 s5, s5, 0x8000
-; GFX950-GISEL-NEXT:    s_and_b32 s9, s7, 0x1ff
+; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s8, 5
+; GFX950-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s8, s9, s8
+; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX950-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX950-GISEL-NEXT:    s_add_i32 s3, s3, s8
+; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX950-GISEL-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX950-GISEL-NEXT:    s_cmpk_eq_i32 s2, 0x40f
+; GFX950-GISEL-NEXT:    s_cselect_b32 s2, s4, s3
+; GFX950-GISEL-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX950-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX950-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; GFX950-GISEL-NEXT:    s_bfe_u32 s3, s7, 0xb0014
+; GFX950-GISEL-NEXT:    s_lshr_b32 s4, s7, 8
+; GFX950-GISEL-NEXT:    s_addk_i32 s3, 0xfc10
+; GFX950-GISEL-NEXT:    s_and_b32 s4, s4, 0xffe
+; GFX950-GISEL-NEXT:    s_and_b32 s5, s7, 0x1ff
 ; GFX950-GISEL-NEXT:    s_or_b32 s5, s5, s6
-; GFX950-GISEL-NEXT:    s_or_b32 s6, s9, s8
+; GFX950-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s4, s4, s5
+; GFX950-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX950-GISEL-NEXT:    s_sub_i32 s8, 1, s3
+; GFX950-GISEL-NEXT:    s_lshl_b32 s6, s3, 12
+; GFX950-GISEL-NEXT:    s_max_i32 s8, s8, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s6, s4, s6
+; GFX950-GISEL-NEXT:    s_min_i32 s8, s8, 13
+; GFX950-GISEL-NEXT:    s_bitset1_b32 s4, 12
+; GFX950-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX950-GISEL-NEXT:    s_lshr_b32 s9, s4, s8
+; GFX950-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX950-GISEL-NEXT:    s_lshl_b32 s8, s9, s8
+; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s8, s4
+; GFX950-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX950-GISEL-NEXT:    s_or_b32 s4, s9, s4
+; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s3, 1
+; GFX950-GISEL-NEXT:    s_cselect_b32 s4, s4, s6
+; GFX950-GISEL-NEXT:    s_and_b32 s6, s4, 7
+; GFX950-GISEL-NEXT:    s_lshr_b32 s4, s4, 2
+; GFX950-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX950-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
 ; GFX950-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s8, s7, 8
-; GFX950-GISEL-NEXT:    s_bfe_u32 s9, s7, 0xb0014
-; GFX950-GISEL-NEXT:    s_and_b32 s8, s8, 0xffe
-; GFX950-GISEL-NEXT:    s_sub_i32 s10, 0x3f1, s9
 ; GFX950-GISEL-NEXT:    s_or_b32 s6, s8, s6
-; GFX950-GISEL-NEXT:    v_med3_i32 v0, s10, 0, 13
-; GFX950-GISEL-NEXT:    s_or_b32 s8, s6, 0x1000
-; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s10, v0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s11, s8, s10
-; GFX950-GISEL-NEXT:    s_lshl_b32 s10, s11, s10
-; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s10, s8
-; GFX950-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX950-GISEL-NEXT:    s_addk_i32 s9, 0xfc10
-; GFX950-GISEL-NEXT:    s_lshl_b32 s10, s9, 12
-; GFX950-GISEL-NEXT:    s_or_b32 s8, s11, s8
-; GFX950-GISEL-NEXT:    s_or_b32 s10, s6, s10
-; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s9, 1
-; GFX950-GISEL-NEXT:    s_cselect_b32 s8, s8, s10
-; GFX950-GISEL-NEXT:    s_and_b32 s10, s8, 7
-; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s10, 5
-; GFX950-GISEL-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX950-GISEL-NEXT:    s_cmp_eq_u32 s10, 3
-; GFX950-GISEL-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX950-GISEL-NEXT:    s_lshr_b32 s8, s8, 2
-; GFX950-GISEL-NEXT:    s_or_b32 s10, s10, s11
-; GFX950-GISEL-NEXT:    s_add_i32 s8, s8, s10
-; GFX950-GISEL-NEXT:    s_cmp_lt_i32 s9, 31
-; GFX950-GISEL-NEXT:    s_cselect_b32 s8, s8, 0x7c00
 ; GFX950-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
-; GFX950-GISEL-NEXT:    s_cselect_b32 s4, s4, 0x7c00
-; GFX950-GISEL-NEXT:    s_cmpk_eq_i32 s9, 0x40f
-; GFX950-GISEL-NEXT:    s_cselect_b32 s4, s4, s8
-; GFX950-GISEL-NEXT:    s_lshr_b32 s6, s7, 16
-; GFX950-GISEL-NEXT:    s_and_b32 s6, s6, 0x8000
-; GFX950-GISEL-NEXT:    s_or_b32 s4, s6, s4
-; GFX950-GISEL-NEXT:    s_pack_ll_b32_b16 s4, s4, s5
-; GFX950-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; GFX950-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX950-GISEL-NEXT:    s_add_i32 s4, s4, s6
+; GFX950-GISEL-NEXT:    s_cmp_gt_i32 s3, 30
+; GFX950-GISEL-NEXT:    s_cselect_b32 s4, 0x7c00, s4
+; GFX950-GISEL-NEXT:    s_cmpk_eq_i32 s3, 0x40f
+; GFX950-GISEL-NEXT:    s_cselect_b32 s3, s5, s4
+; GFX950-GISEL-NEXT:    s_lshr_b32 s4, s7, 16
+; GFX950-GISEL-NEXT:    s_and_b32 s4, s4, 0x8000
+; GFX950-GISEL-NEXT:    s_or_b32 s3, s4, s3
+; GFX950-GISEL-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; GFX950-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX950-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX950-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX950-GISEL-NEXT:    s_endpgm
 ;
@@ -3278,233 +3156,211 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
 ; GFX11-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
 ; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-TRUE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], 0
-; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v3
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v2
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s4, s2, 0x1ff
+; GFX11-GISEL-TRUE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s5, 8
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s8, s5, 0x1ff
+; GFX11-GISEL-TRUE16-NEXT:    s_addk_i32 s2, 0xfc10
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0xffe
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s4, s8, s4
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s4
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_sub_i32 s8, 1, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s10, s3, 0x1000
+; GFX11-GISEL-TRUE16-NEXT:    s_max_i32 s8, s8, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s9, s2, 12
+; GFX11-GISEL-TRUE16-NEXT:    s_min_i32 s8, s8, 13
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s4, s4, 9
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s11, s10, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s9
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s11, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s4, s4, 0x7c00
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, s10
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX11-GISEL-TRUE16-NEXT:    s_sub_i32 s5, 0x3f1, s4
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v2, s5, 0, 13
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s8, s11, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s2, 1
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s8, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s8, s3, 7
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s8, 5
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s8, s9, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_add_i32 s3, s3, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_cmpk_eq_i32 s2, 0x40f
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s4, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX11-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s7, 0xb0014
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s7, 8
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s8, s7, 0x1ff
+; GFX11-GISEL-TRUE16-NEXT:    s_addk_i32 s4, 0xfc10
 ; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s8, v2
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s8, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, s5
 ; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_addk_i32 s4, 0xfc10
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s5, s9, s5
+; GFX11-GISEL-TRUE16-NEXT:    s_sub_i32 s6, 1, s4
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s9, s3, 0x1000
+; GFX11-GISEL-TRUE16-NEXT:    s_max_i32 s6, s6, 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s10, s9, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s8
+; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s6, s10, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, s9
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s6, s10, s6
 ; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, s8
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s6, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s6, s3, 7
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s6, 3
 ; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s8, s8, s9
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_add_i32 s5, s5, s8
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX11-GISEL-TRUE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v1
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, s8, 0x7c00
-; GFX11-GISEL-TRUE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s9, s5
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s9, s3, 0x1ff
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s2, s2, 0x8000
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s2, s2, s5
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_bfe_u32 s5, s3, 0xb0014
-; GFX11-GISEL-TRUE16-NEXT:    s_sub_i32 s9, 0x3f1, s5
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    v_med3_i32 v0, s9, 0, 13
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s3, 8
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s9, s9, 0xffe
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s10, v0
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s9, s4, 0x1000
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s11, s9, s10
-; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s10, s11, s10
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s10, s9
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_addk_i32 s5, 0xfc10
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s9, s11, s9
-; GFX11-GISEL-TRUE16-NEXT:    s_lshl_b32 s10, s5, 12
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s10, s4, s10
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s5, 1
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, s9, s10
-; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s10, s9, 7
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s10, 5
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s10, 3
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s9, 2
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s10, s10, s11
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s6, s8, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_add_i32 s9, s9, s10
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s5, 31
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; GFX11-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s4, 0
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, s8, 0x7c00
-; GFX11-GISEL-TRUE16-NEXT:    s_cmpk_eq_i32 s5, 0x40f
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, s4, s9
-; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX11-GISEL-TRUE16-NEXT:    s_add_i32 s3, s3, s6
+; GFX11-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX11-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s5, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_lshr_b32 s4, s7, 16
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0x8000
-; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s4
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_and_b32 s4, s4, 0x8000
+; GFX11-GISEL-TRUE16-NEXT:    s_or_b32 s3, s4, s3
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b32 v0, off, s[4:7], 0
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX11-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
 ; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], 0
-; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v3
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v2
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s4, s2, 0x1ff
+; GFX11-GISEL-FAKE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s5, 8
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s8, s5, 0x1ff
+; GFX11-GISEL-FAKE16-NEXT:    s_addk_i32 s2, 0xfc10
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0xffe
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s4, s8, s4
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s4
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_sub_i32 s8, 1, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s10, s3, 0x1000
+; GFX11-GISEL-FAKE16-NEXT:    s_max_i32 s8, s8, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s9, s2, 12
+; GFX11-GISEL-FAKE16-NEXT:    s_min_i32 s8, s8, 13
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s4, s4, 9
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s11, s10, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s9
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s11, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s4, s4, 0x7c00
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, s10
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX11-GISEL-FAKE16-NEXT:    s_sub_i32 s5, 0x3f1, s4
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v2, s5, 0, 13
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s8, s11, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s2, 1
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s8, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s8, s3, 7
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s8, 5
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s8, s9, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_add_i32 s3, s3, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_cmpk_eq_i32 s2, 0x40f
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s4, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s7, 0xb0014
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s7, 8
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s8, s7, 0x1ff
+; GFX11-GISEL-FAKE16-NEXT:    s_addk_i32 s4, 0xfc10
 ; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s8, v2
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s8, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, s5
 ; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_addk_i32 s4, 0xfc10
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s5, s9, s5
+; GFX11-GISEL-FAKE16-NEXT:    s_sub_i32 s6, 1, s4
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s9, s3, 0x1000
+; GFX11-GISEL-FAKE16-NEXT:    s_max_i32 s6, s6, 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s10, s9, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s8
+; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s6, s10, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, s9
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s6, s10, s6
 ; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, s8
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s6, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s6, s3, 7
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s6, 3
 ; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s8, s8, s9
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_add_i32 s5, s5, s8
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX11-GISEL-FAKE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v1
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, s8, 0x7c00
-; GFX11-GISEL-FAKE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s9, s5
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s9, s3, 0x1ff
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s2, s2, 0x8000
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s2, s2, s5
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_bfe_u32 s5, s3, 0xb0014
-; GFX11-GISEL-FAKE16-NEXT:    s_sub_i32 s9, 0x3f1, s5
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    v_med3_i32 v0, s9, 0, 13
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s3, 8
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s9, s9, 0xffe
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s10, v0
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s9, s4, 0x1000
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s11, s9, s10
-; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s10, s11, s10
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s10, s9
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_addk_i32 s5, 0xfc10
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s9, s11, s9
-; GFX11-GISEL-FAKE16-NEXT:    s_lshl_b32 s10, s5, 12
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s10, s4, s10
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s5, 1
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, s9, s10
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s10, s9, 7
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s10, 5
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s10, 3
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s9, 2
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s10, s10, s11
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s6, s8, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_add_i32 s9, s9, s10
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s5, 31
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; GFX11-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s4, 0
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, s8, 0x7c00
-; GFX11-GISEL-FAKE16-NEXT:    s_cmpk_eq_i32 s5, 0x40f
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, s4, s9
-; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX11-GISEL-FAKE16-NEXT:    s_add_i32 s3, s3, s6
+; GFX11-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX11-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s5, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_lshr_b32 s4, s7, 16
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0x8000
-; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s4
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_and_b32 s4, s4, 0x8000
+; GFX11-GISEL-FAKE16-NEXT:    s_or_b32 s3, s4, s3
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[4:7], 0
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16:
@@ -3751,117 +3607,106 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
 ; GFX1250-GISEL-TRUE16-NEXT:    v_nop
 ; GFX1250-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], null
-; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v3
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v2
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s4, s2, 0x1ff
+; GFX1250-GISEL-TRUE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s5, 8
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s8, s5, 0x1ff
+; GFX1250-GISEL-TRUE16-NEXT:    s_addk_co_i32 s2, 0xfc10
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0xffe
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s4, s8, s4
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s4
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_sub_co_i32 s8, 1, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s10, s3, 0x1000
+; GFX1250-GISEL-TRUE16-NEXT:    s_max_i32 s8, s8, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s9, s2, 12
+; GFX1250-GISEL-TRUE16-NEXT:    s_min_i32 s8, s8, 13
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s4, s4, 9
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s11, s10, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s9
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s11, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s4, s4, 0x7c00
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, s10
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX1250-GISEL-TRUE16-NEXT:    s_sub_co_i32 s5, 0x3f1, s4
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_med3_i32 v2, s5, 0, 13
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s8, s11, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s2, 1
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s8, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s8, s3, 7
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s8, 5
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s8, s9, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-TRUE16-NEXT:    s_add_co_i32 s3, s3, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s2, 0x40f
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s4, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX1250-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s7, 0xb0014
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s7, 8
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s8, s7, 0x1ff
+; GFX1250-GISEL-TRUE16-NEXT:    s_addk_co_i32 s4, 0xfc10
 ; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s8, v2
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s8, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s8, s5
 ; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_addk_co_i32 s4, 0xfc10
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s5, s9, s5
+; GFX1250-GISEL-TRUE16-NEXT:    s_sub_co_i32 s6, 1, s4
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s9, s3, 0x1000
+; GFX1250-GISEL-TRUE16-NEXT:    s_max_i32 s6, s6, 0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s10, s9, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s8
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s6, s10, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, s9
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s6, s10, s6
 ; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, s8
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s6, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s6, s3, 7
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s6, 3
 ; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s8, s8, s9
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_add_co_i32 s5, s5, s8
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX1250-GISEL-TRUE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v1
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, s8, 0x7c00
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s4, 0x40f
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, s9, s5
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s9, s3, 0x1ff
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s2, s2, 0x8000
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s2, s2, s5
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_bfe_u32 s5, s3, 0xb0014
-; GFX1250-GISEL-TRUE16-NEXT:    s_sub_co_i32 s9, 0x3f1, s5
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_med3_i32 v0, s9, 0, 13
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s3, 8
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s9, s9, 0xffe
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s10, v0
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s9, s4, 0x1000
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s11, s9, s10
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s10, s11, s10
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s10, s9
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_addk_co_i32 s5, 0xfc10
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s9, s11, s9
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshl_b32 s10, s5, 12
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s10, s4, s10
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s5, 1
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, s9, s10
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s10, s9, 7
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s10, 5
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s10, 3
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s9, 2
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s10, s10, s11
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s6, s8, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_add_co_i32 s9, s9, s10
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s5, 31
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s4, 0
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, s8, 0x7c00
-; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s5, 0x40f
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s4, s4, s9
-; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX1250-GISEL-TRUE16-NEXT:    s_add_co_i32 s3, s3, s6
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s4, 0x40f
+; GFX1250-GISEL-TRUE16-NEXT:    s_cselect_b32 s3, s5, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_lshr_b32 s4, s7, 16
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0x8000
-; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s3, s4
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_and_b32 s4, s4, 0x8000
+; GFX1250-GISEL-TRUE16-NEXT:    s_or_b32 s3, s4, s3
 ; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1250-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b32 v0, off, s[4:7], null
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b32 v0, off, s[0:3], null
 ; GFX1250-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16:
@@ -3870,117 +3715,106 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
 ; GFX1250-GISEL-FAKE16-NEXT:    v_nop
 ; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], null
-; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v3
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v2
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s4, s2, 0x1ff
+; GFX1250-GISEL-FAKE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    s_bfe_u32 s2, s5, 0xb0014
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s5, 8
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s8, s5, 0x1ff
+; GFX1250-GISEL-FAKE16-NEXT:    s_addk_co_i32 s2, 0xfc10
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0xffe
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s4, s8, s4
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s4
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_sub_co_i32 s8, 1, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s10, s3, 0x1000
+; GFX1250-GISEL-FAKE16-NEXT:    s_max_i32 s8, s8, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s9, s2, 12
+; GFX1250-GISEL-FAKE16-NEXT:    s_min_i32 s8, s8, 13
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s4, s4, 9
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s11, s10, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s9
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s11, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s4, s4, 0x7c00
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, s10
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s4, s3
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s2, 0xb0014
-; GFX1250-GISEL-FAKE16-NEXT:    s_sub_co_i32 s5, 0x3f1, s4
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_med3_i32 v2, s5, 0, 13
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s2, 8
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s8, s11, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s2, 1
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s8, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s8, s3, 7
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s8, 5
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s8, s9, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-FAKE16-NEXT:    s_add_co_i32 s3, s3, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s2, 30
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s2, 0x40f
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s4, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s5, 16
+; GFX1250-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s7, 0xb0014
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s7, 8
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s8, s7, 0x1ff
+; GFX1250-GISEL-FAKE16-NEXT:    s_addk_co_i32 s4, 0xfc10
 ; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s5, s5, 0xffe
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s8, v2
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s8, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
 ; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s5, s3
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s5, s3, 0x1000
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s5, s8
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s9, s8
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s8, s5
 ; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_addk_co_i32 s4, 0xfc10
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s5, s9, s5
+; GFX1250-GISEL-FAKE16-NEXT:    s_sub_co_i32 s6, 1, s4
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s9, s3, 0x1000
+; GFX1250-GISEL-FAKE16-NEXT:    s_max_i32 s6, s6, 0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s8, s4, 12
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s8, s3, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s10, s9, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s8
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s6, s10, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, s9
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s6, s10, s6
 ; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 1
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, s8
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s8, s5, 7
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s8, 5
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s8, 3
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s6, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s6, s3, 7
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 2
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s6, 3
 ; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s8, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s5, 2
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s8, s8, s9
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_add_co_i32 s5, s5, s8
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 31
-; GFX1250-GISEL-FAKE16-NEXT:    s_movk_i32 s8, 0x7e00
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s3, 0
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v1
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, s8, 0x7c00
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s4, 0x40f
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s4, v0
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, s9, s5
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s9, s3, 0x1ff
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s2, s2, 0x8000
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s2, s2, s5
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_bfe_u32 s5, s3, 0xb0014
-; GFX1250-GISEL-FAKE16-NEXT:    s_sub_co_i32 s9, 0x3f1, s5
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_med3_i32 v0, s9, 0, 13
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s3, 8
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s9, s9, 0xffe
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s10, v0
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s4, s9, s4
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s9, s4, 0x1000
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s11, s9, s10
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s10, s11, s10
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s10, s9
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_addk_co_i32 s5, 0xfc10
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s9, s11, s9
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshl_b32 s10, s5, 12
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s10, s4, s10
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s5, 1
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, s9, s10
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s10, s9, 7
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s10, 5
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s11, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s10, 3
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s10, 1, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s9, 2
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s10, s10, s11
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s6, s8, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_add_co_i32 s9, s9, s10
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s5, 31
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s9, s9, 0x7c00
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s4, 0
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, s8, 0x7c00
-; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s5, 0x40f
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s4, s4, s9
-; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX1250-GISEL-FAKE16-NEXT:    s_add_co_i32 s3, s3, s6
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, 0x7c00, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s4, 0x40f
+; GFX1250-GISEL-FAKE16-NEXT:    s_cselect_b32 s3, s5, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_lshr_b32 s4, s7, 16
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0x8000
-; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s3, s4
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s3, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_and_b32 s4, s4, 0x8000
+; GFX1250-GISEL-FAKE16-NEXT:    s_or_b32 s3, s4, s3
 ; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1250-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[4:7], null
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], null
 ; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a) {
@@ -4018,24 +3852,23 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
 ; SI-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
 ; SI-GISEL:       ; %bb.0: ; %entry
 ; SI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x9
-; SI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; SI-GISEL-NEXT:    s_mov_b32 s6, -1
-; SI-GISEL-NEXT:    s_mov_b32 s10, s6
-; SI-GISEL-NEXT:    s_mov_b32 s11, s7
 ; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; SI-GISEL-NEXT:    s_mov_b32 s8, s2
-; SI-GISEL-NEXT:    s_mov_b32 s9, s3
-; SI-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; SI-GISEL-NEXT:    s_mov_b32 s4, s0
-; SI-GISEL-NEXT:    s_mov_b32 s5, s1
-; SI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
-; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v2
+; SI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; SI-GISEL-NEXT:    s_mov_b32 s2, -1
+; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
+; SI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
 ; SI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; SI-GISEL-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
-; SI-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
-; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; SI-GISEL-NEXT:    v_readfirstlane_b32 s4, v1
+; SI-GISEL-NEXT:    v_readfirstlane_b32 s3, v0
+; SI-GISEL-NEXT:    s_bfe_u32 s4, s4, 0x100000
+; SI-GISEL-NEXT:    s_bfe_u32 s3, s3, 0x100000
+; SI-GISEL-NEXT:    s_lshl_b32 s4, s4, 16
+; SI-GISEL-NEXT:    s_or_b32 s3, s3, s4
+; SI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
+; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; SI-GISEL-NEXT:    s_endpgm
 ;
 ; VI-SDAG-LABEL: fptrunc_v2f64_to_v2f16_afn:
@@ -4063,23 +3896,23 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
 ; VI-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
 ; VI-GISEL:       ; %bb.0: ; %entry
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; VI-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; VI-GISEL-NEXT:    s_mov_b32 s6, -1
-; VI-GISEL-NEXT:    s_mov_b32 s10, s6
-; VI-GISEL-NEXT:    s_mov_b32 s11, s7
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    s_mov_b32 s8, s2
-; VI-GISEL-NEXT:    s_mov_b32 s9, s3
-; VI-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; VI-GISEL-NEXT:    s_mov_b32 s4, s0
-; VI-GISEL-NEXT:    s_mov_b32 s5, s1
-; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
-; VI-GISEL-NEXT:    v_cvt_f16_f32_sdwa v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; VI-GISEL-NEXT:    s_mov_b32 s2, -1
+; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
+; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
 ; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; VI-GISEL-NEXT:    v_or_b32_e32 v0, v0, v1
-; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; VI-GISEL-NEXT:    v_readfirstlane_b32 s4, v1
+; VI-GISEL-NEXT:    v_readfirstlane_b32 s3, v0
+; VI-GISEL-NEXT:    s_bfe_u32 s4, s4, 0x100000
+; VI-GISEL-NEXT:    s_bfe_u32 s3, s3, 0x100000
+; VI-GISEL-NEXT:    s_lshl_b32 s4, s4, 16
+; VI-GISEL-NEXT:    s_or_b32 s3, s3, s4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
+; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; VI-GISEL-NEXT:    s_endpgm
 ;
 ; GFX9-SDAG-LABEL: fptrunc_v2f64_to_v2f16_afn:
@@ -4107,23 +3940,21 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
 ; GFX9-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
 ; GFX9-GISEL:       ; %bb.0: ; %entry
 ; GFX9-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX9-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; GFX9-GISEL-NEXT:    s_mov_b32 s6, -1
-; GFX9-GISEL-NEXT:    s_mov_b32 s10, s6
-; GFX9-GISEL-NEXT:    s_mov_b32 s11, s7
 ; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-GISEL-NEXT:    s_mov_b32 s8, s2
-; GFX9-GISEL-NEXT:    s_mov_b32 s9, s3
-; GFX9-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GFX9-GISEL-NEXT:    s_mov_b32 s4, s0
-; GFX9-GISEL-NEXT:    s_mov_b32 s5, s1
-; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v2
+; GFX9-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX9-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; GFX9-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
 ; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX9-GISEL-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX9-GISEL-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX9-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX9-GISEL-NEXT:    v_readfirstlane_b32 s4, v1
+; GFX9-GISEL-NEXT:    s_pack_ll_b32_b16 s3, s3, s4
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s3
+; GFX9-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; GFX9-GISEL-NEXT:    s_nop 0
+; GFX9-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX9-GISEL-NEXT:    s_endpgm
 ;
 ; GFX950-SDAG-LABEL: fptrunc_v2f64_to_v2f16_afn:
@@ -4149,21 +3980,21 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
 ; GFX950-GISEL-LABEL: fptrunc_v2f64_to_v2f16_afn:
 ; GFX950-GISEL:       ; %bb.0: ; %entry
 ; GFX950-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
-; GFX950-GISEL-NEXT:    s_mov_b32 s7, 0xf000
-; GFX950-GISEL-NEXT:    s_mov_b32 s6, -1
-; GFX950-GISEL-NEXT:    s_mov_b32 s10, s6
-; GFX950-GISEL-NEXT:    s_mov_b32 s11, s7
 ; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX950-GISEL-NEXT:    s_mov_b32 s8, s2
-; GFX950-GISEL-NEXT:    s_mov_b32 s9, s3
-; GFX950-GISEL-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
-; GFX950-GISEL-NEXT:    s_mov_b32 s4, s0
-; GFX950-GISEL-NEXT:    s_mov_b32 s5, s1
-; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX950-GISEL-NEXT:    v_cvt_pk_f16_f32 v0, v0, v2
-; GFX950-GISEL-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX950-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX950-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX950-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; GFX950-GISEL-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
+; GFX950-GISEL-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s3, v0
+; GFX950-GISEL-NEXT:    v_readfirstlane_b32 s4, v1
+; GFX950-GISEL-NEXT:    s_pack_ll_b32_b16 s3, s3, s4
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v0, s3
+; GFX950-GISEL-NEXT:    s_mov_b32 s3, 0xf000
+; GFX950-GISEL-NEXT:    s_nop 0
+; GFX950-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX950-GISEL-NEXT:    s_endpgm
 ;
 ; GFX11-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
@@ -4215,47 +4046,43 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
 ; GFX11-GISEL-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
 ; GFX11-GISEL-TRUE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-TRUE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], 0
-; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-TRUE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX11-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
+; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v1
 ; GFX11-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.h, v2
-; GFX11-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v1.l, v0
-; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b32 v1, off, s[4:7], 0
+; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-TRUE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
 ; GFX11-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX11-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
 ; GFX11-GISEL-FAKE16:       ; %bb.0: ; %entry
 ; GFX11-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX11-GISEL-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], 0
-; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX11-GISEL-FAKE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX11-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
 ; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v2
 ; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
-; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-FAKE16-NEXT:    v_pack_b32_f16 v0, v0, v1
-; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[4:7], 0
+; GFX11-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v1, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX11-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v1
+; GFX11-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], 0
 ; GFX11-GISEL-FAKE16-NEXT:    s_endpgm
 ;
 ; GFX1250-SDAG-TRUE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
@@ -4312,22 +4139,23 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
 ; GFX1250-GISEL-TRUE16-NEXT:    v_nop
 ; GFX1250-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], null
-; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-TRUE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v2
-; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b32 v0, off, s[4:7], null
+; GFX1250-GISEL-TRUE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; GFX1250-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-TRUE16-NEXT:    v_readfirstlane_b32 s3, v1
+; GFX1250-GISEL-TRUE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-TRUE16-NEXT:    s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_cvt_f16_f32 s3, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1250-GISEL-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-TRUE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX1250-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-TRUE16-NEXT:    buffer_store_b32 v0, off, s[0:3], null
 ; GFX1250-GISEL-TRUE16-NEXT:    s_endpgm
 ;
 ; GFX1250-GISEL-FAKE16-LABEL: fptrunc_v2f64_to_v2f16_afn:
@@ -4336,22 +4164,23 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16_afn(
 ; GFX1250-GISEL-FAKE16-NEXT:    v_nop
 ; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
 ; GFX1250-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24 nv
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s6, -1
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s7, 0x31016000
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s10, s6
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s11, s7
 ; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s8, s2
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s9, s3
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s4, s0
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_load_b128 v[0:3], off, s[8:11], null
-; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s5, s1
-; GFX1250-GISEL-FAKE16-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v2, v[2:3]
-; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, v[0:1]
-; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_pk_f16_f32 v0, v0, v2
-; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[4:7], null
+; GFX1250-GISEL-FAKE16-NEXT:    s_load_b128 s[4:7], s[2:3], 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, s[4:5]
+; GFX1250-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v1, s[6:7]
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s2, v0
+; GFX1250-GISEL-FAKE16-NEXT:    v_readfirstlane_b32 s3, v1
+; GFX1250-GISEL-FAKE16-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-FAKE16-NEXT:    s_cvt_f16_f32 s2, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_cvt_f16_f32 s3, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_3)
+; GFX1250-GISEL-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s3
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX1250-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX1250-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX1250-GISEL-FAKE16-NEXT:    buffer_store_b32 v0, off, s[0:3], null
 ; GFX1250-GISEL-FAKE16-NEXT:    s_endpgm
     ptr addrspace(1) %r,
     ptr addrspace(1) %a) {
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index daeea63e72282..685fc615812dc 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -1,17 +1,17 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI %s
 ; RUN: llc -mtriple=amdgpu8.02 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-SDAG,VI-SAFE-SDAG %s
-; RUN: llc -mtriple=amdgpu8.02 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-GISEL,VI-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgpu8.02 -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-GISEL,VI-SAFE-GISEL %s
 ; RUN: llc -mtriple=amdgpu8.02 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI-SDAG,VI-UNSAFE-SDAG %s
 ; RUN: llc -mtriple=amdgpu10.30 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-SDAG,GFX10-SAFE-SDAG %s
-; RUN: llc -mtriple=amdgpu10.30 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-GISEL,GFX10-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgpu10.30 -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-GISEL,GFX10-SAFE-GISEL %s
 ; RUN: llc -mtriple=amdgpu10.30 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10-SDAG,GFX10-UNSAFE-SDAG %s
 ; RUN: llc -mtriple=amdgpu11.00 -global-isel=0 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-SAFE-SDAG %s
-; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-SAFE-GISEL %s
 ; RUN: llc -mtriple=amdgpu11.00 -global-isel=0 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-SDAG-TRUE16 %s
 ; RUN: llc -mtriple=amdgpu11.00 -global-isel=0 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-UNSAFE-SDAG-FAKE16 %s
-; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-TRUE16 %s
-; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -global-isel-abort=2 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-FAKE16 %s
+; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-TRUE16 %s
+; RUN: llc -mtriple=amdgpu11.00 -global-isel=1 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-UNSAFE-GISEL-FAKE16 %s
 
 define amdgpu_kernel void @fptrunc_f64_to_f32(ptr addrspace(1) %out, double %in) {
 ; SI-LABEL: fptrunc_f64_to_f32:
@@ -276,52 +276,52 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
 ;
 ; VI-GISEL-LABEL: fptrunc_f64_to_f16:
 ; VI-GISEL:       ; %bb.0:
-; VI-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x24
-; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
-; VI-GISEL-NEXT:    s_mov_b32 s2, -1
+; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-GISEL-NEXT:    s_mov_b32 s0, s4
-; VI-GISEL-NEXT:    s_lshr_b32 s4, s7, 8
-; VI-GISEL-NEXT:    s_mov_b32 s1, s5
-; VI-GISEL-NEXT:    s_and_b32 s4, s4, 0xffe
-; VI-GISEL-NEXT:    s_and_b32 s5, s7, 0x1ff
-; VI-GISEL-NEXT:    s_or_b32 s5, s5, s6
-; VI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; VI-GISEL-NEXT:    s_bfe_u32 s6, s7, 0xb0014
-; VI-GISEL-NEXT:    s_sub_i32 s8, 0x3f1, s6
-; VI-GISEL-NEXT:    s_or_b32 s4, s4, s5
-; VI-GISEL-NEXT:    v_med3_i32 v0, s8, 0, 13
-; VI-GISEL-NEXT:    s_or_b32 s5, s4, 0x1000
-; VI-GISEL-NEXT:    v_readfirstlane_b32 s8, v0
-; VI-GISEL-NEXT:    s_lshr_b32 s9, s5, s8
-; VI-GISEL-NEXT:    s_lshl_b32 s8, s9, s8
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s8, s5
+; VI-GISEL-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; VI-GISEL-NEXT:    s_lshr_b32 s5, s3, 8
+; VI-GISEL-NEXT:    s_and_b32 s6, s3, 0x1ff
+; VI-GISEL-NEXT:    s_addk_i32 s4, 0xfc10
+; VI-GISEL-NEXT:    s_and_b32 s5, s5, 0xffe
+; VI-GISEL-NEXT:    s_or_b32 s2, s6, s2
+; VI-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s2, s5, s2
 ; VI-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; VI-GISEL-NEXT:    s_addk_i32 s6, 0xfc10
-; VI-GISEL-NEXT:    s_lshl_b32 s8, s6, 12
-; VI-GISEL-NEXT:    s_or_b32 s5, s9, s5
-; VI-GISEL-NEXT:    s_or_b32 s8, s4, s8
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s6, 1
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s5, s8
-; VI-GISEL-NEXT:    s_and_b32 s8, s5, 7
-; VI-GISEL-NEXT:    s_cmp_gt_i32 s8, 5
-; VI-GISEL-NEXT:    s_cselect_b32 s9, 1, 0
-; VI-GISEL-NEXT:    s_cmp_eq_u32 s8, 3
-; VI-GISEL-NEXT:    s_cselect_b32 s8, 1, 0
-; VI-GISEL-NEXT:    s_or_b32 s8, s8, s9
-; VI-GISEL-NEXT:    s_lshr_b32 s5, s5, 2
-; VI-GISEL-NEXT:    s_add_i32 s5, s5, s8
-; VI-GISEL-NEXT:    s_cmp_lt_i32 s6, 31
-; VI-GISEL-NEXT:    s_cselect_b32 s5, s5, 0x7c00
-; VI-GISEL-NEXT:    s_cmp_lg_u32 s4, 0
-; VI-GISEL-NEXT:    s_movk_i32 s4, 0x7e00
-; VI-GISEL-NEXT:    s_cselect_b32 s4, s4, 0x7c00
-; VI-GISEL-NEXT:    s_cmpk_eq_i32 s6, 0x40f
-; VI-GISEL-NEXT:    s_cselect_b32 s4, s4, s5
-; VI-GISEL-NEXT:    s_lshr_b32 s5, s7, 16
-; VI-GISEL-NEXT:    s_and_b32 s5, s5, 0x8000
-; VI-GISEL-NEXT:    s_or_b32 s4, s5, s4
-; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s4
+; VI-GISEL-NEXT:    s_sub_i32 s7, 1, s4
+; VI-GISEL-NEXT:    s_lshl_b32 s6, s4, 12
+; VI-GISEL-NEXT:    s_max_i32 s7, s7, 0
+; VI-GISEL-NEXT:    s_or_b32 s6, s2, s6
+; VI-GISEL-NEXT:    s_min_i32 s7, s7, 13
+; VI-GISEL-NEXT:    s_bitset1_b32 s2, 12
+; VI-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; VI-GISEL-NEXT:    s_lshr_b32 s8, s2, s7
+; VI-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; VI-GISEL-NEXT:    s_lshl_b32 s7, s8, s7
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s7, s2
+; VI-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s2, s8, s2
+; VI-GISEL-NEXT:    s_cmp_lt_i32 s4, 1
+; VI-GISEL-NEXT:    s_cselect_b32 s2, s2, s6
+; VI-GISEL-NEXT:    s_and_b32 s6, s2, 7
+; VI-GISEL-NEXT:    s_lshr_b32 s2, s2, 2
+; VI-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
+; VI-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
+; VI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT:    s_or_b32 s6, s7, s6
+; VI-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
+; VI-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; VI-GISEL-NEXT:    s_add_i32 s2, s2, s6
+; VI-GISEL-NEXT:    s_cmp_gt_i32 s4, 30
+; VI-GISEL-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; VI-GISEL-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; VI-GISEL-NEXT:    s_cselect_b32 s2, s5, s2
+; VI-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
+; VI-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; VI-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
+; VI-GISEL-NEXT:    s_mov_b32 s2, -1
+; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; VI-GISEL-NEXT:    s_endpgm
 ;
@@ -378,42 +378,44 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
 ; GFX10-GISEL:       ; %bb.0:
 ; GFX10-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-GISEL-NEXT:    s_lshr_b32 s4, s3, 8
-; GFX10-GISEL-NEXT:    s_and_b32 s5, s3, 0x1ff
-; GFX10-GISEL-NEXT:    s_and_b32 s4, s4, 0xffe
-; GFX10-GISEL-NEXT:    s_or_b32 s2, s5, s2
+; GFX10-GISEL-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX10-GISEL-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX10-GISEL-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX10-GISEL-NEXT:    s_addk_i32 s4, 0xfc10
+; GFX10-GISEL-NEXT:    s_and_b32 s5, s5, 0xffe
+; GFX10-GISEL-NEXT:    s_or_b32 s2, s6, s2
 ; GFX10-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
-; GFX10-GISEL-NEXT:    s_bfe_u32 s5, s3, 0xb0014
-; GFX10-GISEL-NEXT:    s_or_b32 s2, s4, s2
-; GFX10-GISEL-NEXT:    s_sub_i32 s6, 0x3f1, s5
-; GFX10-GISEL-NEXT:    s_or_b32 s4, s2, 0x1000
-; GFX10-GISEL-NEXT:    v_med3_i32 v0, s6, 0, 13
-; GFX10-GISEL-NEXT:    v_readfirstlane_b32 s6, v0
-; GFX10-GISEL-NEXT:    s_lshr_b32 s7, s4, s6
-; GFX10-GISEL-NEXT:    s_lshl_b32 s6, s7, s6
-; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s6, s4
-; GFX10-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-GISEL-NEXT:    s_addk_i32 s5, 0xfc10
-; GFX10-GISEL-NEXT:    s_or_b32 s4, s7, s4
-; GFX10-GISEL-NEXT:    s_lshl_b32 s6, s5, 12
-; GFX10-GISEL-NEXT:    s_or_b32 s6, s2, s6
-; GFX10-GISEL-NEXT:    s_cmp_lt_i32 s5, 1
-; GFX10-GISEL-NEXT:    s_cselect_b32 s4, s4, s6
-; GFX10-GISEL-NEXT:    s_and_b32 s6, s4, 7
-; GFX10-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
-; GFX10-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX10-GISEL-NEXT:    s_or_b32 s2, s5, s2
+; GFX10-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX10-GISEL-NEXT:    s_sub_i32 s6, 1, s4
+; GFX10-GISEL-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX10-GISEL-NEXT:    s_max_i32 s6, s6, 0
+; GFX10-GISEL-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX10-GISEL-NEXT:    s_min_i32 s6, s6, 13
+; GFX10-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX10-GISEL-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX10-GISEL-NEXT:    s_or_b32 s2, s2, s7
+; GFX10-GISEL-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX10-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX10-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX10-GISEL-NEXT:    s_or_b32 s6, s9, s6
+; GFX10-GISEL-NEXT:    s_cmp_lt_i32 s4, 1
+; GFX10-GISEL-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX10-GISEL-NEXT:    s_and_b32 s6, s2, 7
+; GFX10-GISEL-NEXT:    s_lshr_b32 s2, s2, 2
 ; GFX10-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX10-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX10-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX10-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX10-GISEL-NEXT:    s_or_b32 s6, s7, s6
+; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
 ; GFX10-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX10-GISEL-NEXT:    s_lshr_b32 s4, s4, 2
-; GFX10-GISEL-NEXT:    s_or_b32 s6, s6, s7
-; GFX10-GISEL-NEXT:    s_add_i32 s4, s4, s6
-; GFX10-GISEL-NEXT:    s_cmp_lt_i32 s5, 31
-; GFX10-GISEL-NEXT:    s_movk_i32 s6, 0x7e00
-; GFX10-GISEL-NEXT:    s_cselect_b32 s4, s4, 0x7c00
-; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s2, 0
-; GFX10-GISEL-NEXT:    s_cselect_b32 s2, s6, 0x7c00
-; GFX10-GISEL-NEXT:    s_cmpk_eq_i32 s5, 0x40f
-; GFX10-GISEL-NEXT:    s_cselect_b32 s2, s2, s4
+; GFX10-GISEL-NEXT:    s_add_i32 s2, s2, s6
+; GFX10-GISEL-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX10-GISEL-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; GFX10-GISEL-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX10-GISEL-NEXT:    s_cselect_b32 s2, s5, s2
 ; GFX10-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
 ; GFX10-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
 ; GFX10-GISEL-NEXT:    s_or_b32 s2, s3, s2
@@ -477,59 +479,173 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
 ; GFX11-SDAG-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
 ; GFX11-SDAG-NEXT:    s_endpgm
 ;
-; GFX11-GISEL-LABEL: fptrunc_f64_to_f16:
-; GFX11-GISEL:       ; %bb.0:
-; GFX11-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-NEXT:    s_lshr_b32 s4, s3, 8
-; GFX11-GISEL-NEXT:    s_and_b32 s5, s3, 0x1ff
-; GFX11-GISEL-NEXT:    s_and_b32 s4, s4, 0xffe
-; GFX11-GISEL-NEXT:    s_or_b32 s2, s5, s2
-; GFX11-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
-; GFX11-GISEL-NEXT:    s_bfe_u32 s5, s3, 0xb0014
-; GFX11-GISEL-NEXT:    s_or_b32 s2, s4, s2
-; GFX11-GISEL-NEXT:    s_sub_i32 s6, 0x3f1, s5
-; GFX11-GISEL-NEXT:    s_or_b32 s4, s2, 0x1000
-; GFX11-GISEL-NEXT:    v_med3_i32 v0, s6, 0, 13
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT:    v_readfirstlane_b32 s6, v0
-; GFX11-GISEL-NEXT:    s_lshr_b32 s7, s4, s6
-; GFX11-GISEL-NEXT:    s_lshl_b32 s6, s7, s6
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT:    s_cmp_lg_u32 s6, s4
-; GFX11-GISEL-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX11-GISEL-NEXT:    s_addk_i32 s5, 0xfc10
-; GFX11-GISEL-NEXT:    s_or_b32 s4, s7, s4
-; GFX11-GISEL-NEXT:    s_lshl_b32 s6, s5, 12
-; GFX11-GISEL-NEXT:    s_or_b32 s6, s2, s6
-; GFX11-GISEL-NEXT:    s_cmp_lt_i32 s5, 1
-; GFX11-GISEL-NEXT:    s_cselect_b32 s4, s4, s6
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT:    s_and_b32 s6, s4, 7
-; GFX11-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
-; GFX11-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
-; GFX11-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
-; GFX11-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX11-GISEL-NEXT:    s_lshr_b32 s4, s4, 2
-; GFX11-GISEL-NEXT:    s_or_b32 s6, s6, s7
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT:    s_add_i32 s4, s4, s6
-; GFX11-GISEL-NEXT:    s_cmp_lt_i32 s5, 31
-; GFX11-GISEL-NEXT:    s_movk_i32 s6, 0x7e00
-; GFX11-GISEL-NEXT:    s_cselect_b32 s4, s4, 0x7c00
-; GFX11-GISEL-NEXT:    s_cmp_lg_u32 s2, 0
-; GFX11-GISEL-NEXT:    s_cselect_b32 s2, s6, 0x7c00
-; GFX11-GISEL-NEXT:    s_cmpk_eq_i32 s5, 0x40f
-; GFX11-GISEL-NEXT:    s_cselect_b32 s2, s2, s4
-; GFX11-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
-; GFX11-GISEL-NEXT:    s_or_b32 s2, s3, s2
-; GFX11-GISEL-NEXT:    s_mov_b32 s3, 0x31016000
-; GFX11-GISEL-NEXT:    v_mov_b32_e32 v0, s2
-; GFX11-GISEL-NEXT:    s_mov_b32 s2, -1
-; GFX11-GISEL-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-GISEL-NEXT:    s_endpgm
+; GFX11-SAFE-GISEL-LABEL: fptrunc_f64_to_f16:
+; GFX11-SAFE-GISEL:       ; %bb.0:
+; GFX11-SAFE-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-SAFE-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-SAFE-GISEL-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX11-SAFE-GISEL-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX11-SAFE-GISEL-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX11-SAFE-GISEL-NEXT:    s_addk_i32 s4, 0xfc10
+; GFX11-SAFE-GISEL-NEXT:    s_and_b32 s5, s5, 0xffe
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s2, s6, s2
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX11-SAFE-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s2, s5, s2
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX11-SAFE-GISEL-NEXT:    s_sub_i32 s6, 1, s4
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX11-SAFE-GISEL-NEXT:    s_max_i32 s6, s6, 0
+; GFX11-SAFE-GISEL-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX11-SAFE-GISEL-NEXT:    s_min_i32 s6, s6, 13
+; GFX11-SAFE-GISEL-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-SAFE-GISEL-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s2, s2, s7
+; GFX11-SAFE-GISEL-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX11-SAFE-GISEL-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-SAFE-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s6, s9, s6
+; GFX11-SAFE-GISEL-NEXT:    s_cmp_lt_i32 s4, 1
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX11-SAFE-GISEL-NEXT:    s_and_b32 s6, s2, 7
+; GFX11-SAFE-GISEL-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX11-SAFE-GISEL-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX11-SAFE-GISEL-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-SAFE-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s6, s7, s6
+; GFX11-SAFE-GISEL-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-SAFE-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-SAFE-GISEL-NEXT:    s_add_i32 s2, s2, s6
+; GFX11-SAFE-GISEL-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; GFX11-SAFE-GISEL-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX11-SAFE-GISEL-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX11-SAFE-GISEL-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX11-SAFE-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-SAFE-GISEL-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX11-SAFE-GISEL-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-SAFE-GISEL-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-SAFE-GISEL-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX11-SAFE-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX11-SAFE-GISEL-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-SAFE-GISEL-NEXT:    s_endpgm
+;
+; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16:
+; GFX11-UNSAFE-GISEL-TRUE16:       ; %bb.0:
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_addk_i32 s4, 0xfc10
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_and_b32 s5, s5, 0xffe
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s2, s6, s2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s2, s5, s2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_sub_i32 s6, 1, s4
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_max_i32 s6, s6, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s2, s2, s7
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s6, s9, s6
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cmp_lt_i32 s4, 1
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_and_b32 s6, s2, 7
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s6, s7, s6
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_add_i32 s2, s2, s6
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    v_mov_b16_e32 v0.l, s2
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_endpgm
+;
+; GFX11-UNSAFE-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16:
+; GFX11-UNSAFE-GISEL-FAKE16:       ; %bb.0:
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_bfe_u32 s4, s3, 0xb0014
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_lshr_b32 s5, s3, 8
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_and_b32 s6, s3, 0x1ff
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_addk_i32 s4, 0xfc10
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_and_b32 s5, s5, 0xffe
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s2, s6, s2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s2, s5, s2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_sub_i32 s6, 1, s4
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s8, s2, 0x1000
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_max_i32 s6, s6, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_lshl_b32 s7, s4, 12
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_min_i32 s6, s6, 13
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_lshl_b32 s5, s5, 9
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_lshr_b32 s9, s8, s6
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s2, s2, s7
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_lshl_b32 s6, s9, s6
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s5, s5, 0x7c00
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, s8
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s6, s9, s6
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cmp_lt_i32 s4, 1
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s6, s2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_and_b32 s6, s2, 7
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_lshr_b32 s2, s2, 2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cmp_eq_u32 s6, 3
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s7, 1, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s6, 5
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s6, s7, s6
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cmp_lg_u32 s6, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s6, 1, 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_add_i32 s2, s2, s6
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cmp_gt_i32 s4, 30
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, 0x7c00, s2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cmpk_eq_i32 s4, 0x40f
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_cselect_b32 s2, s5, s2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_lshr_b32 s3, s3, 16
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_and_b32 s3, s3, 0x8000
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_or_b32 s2, s3, s2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    v_mov_b32_e32 v0, s2
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_endpgm
   %result = fptrunc double %in to half
   %result_i16 = bitcast half %result to i16
   store i16 %result_i16, ptr addrspace(1) %out
@@ -564,8 +680,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(ptr addrspace(1) %out, double
 ; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
-; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-GISEL-NEXT:    s_mov_b32 s2, -1
+; VI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
 ; VI-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; VI-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; VI-GISEL-NEXT:    s_endpgm
@@ -586,8 +702,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(ptr addrspace(1) %out, double
 ; GFX10-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
 ; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX10-GISEL-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX10-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX10-GISEL-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX10-GISEL-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX10-GISEL-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX10-GISEL-NEXT:    s_endpgm
@@ -609,8 +725,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(ptr addrspace(1) %out, double
 ; GFX11-SAFE-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-SAFE-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-SAFE-GISEL-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX11-SAFE-GISEL-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-SAFE-GISEL-NEXT:    s_mov_b32 s2, -1
+; GFX11-SAFE-GISEL-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-SAFE-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-SAFE-GISEL-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
 ; GFX11-SAFE-GISEL-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
@@ -645,8 +761,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(ptr addrspace(1) %out, double
 ; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    v_cvt_f16_f32_e32 v0.l, v0
 ; GFX11-UNSAFE-GISEL-TRUE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
@@ -657,8 +773,8 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(ptr addrspace(1) %out, double
 ; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x24
 ; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    v_cvt_f32_f64_e32 v0, s[2:3]
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_mov_b32 s2, -1
+; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)
 ; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX11-UNSAFE-GISEL-FAKE16-NEXT:    buffer_store_b16 v0, off, s[0:3], 0
@@ -1908,46 +2024,47 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
 ; VI-GISEL:       ; %bb.0:
 ; VI-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; VI-GISEL-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v1
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0x1ff, v1
-; VI-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0
+; VI-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; VI-GISEL-NEXT:    v_and_b32_e32 v4, 0x1ff, v1
+; VI-GISEL-NEXT:    v_add_u32_e32 v2, vcc, 0xfffffc10, v2
+; VI-GISEL-NEXT:    v_or_b32_e32 v0, v4, v0
+; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
 ; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
+; VI-GISEL-NEXT:    v_and_b32_e32 v3, 0xffe, v3
 ; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-GISEL-NEXT:    v_and_b32_e32 v2, 0xffe, v2
-; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 20, v1
-; VI-GISEL-NEXT:    s_movk_i32 s4, 0x3f1
-; VI-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0
-; VI-GISEL-NEXT:    v_sub_u32_e32 v3, vcc, s4, v1
-; VI-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v0
-; VI-GISEL-NEXT:    v_med3_i32 v3, v3, 0, 13
-; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v4, v3, v2
-; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v3, v3, v4
-; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v3, v2
-; VI-GISEL-NEXT:    s_movk_i32 s4, 0xfc10
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; VI-GISEL-NEXT:    v_add_u32_e32 v1, vcc, s4, v1
-; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v3, 12, v1
-; VI-GISEL-NEXT:    v_or_b32_e32 v2, v4, v2
-; VI-GISEL-NEXT:    v_or_b32_e32 v3, v0, v3
-; VI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-GISEL-NEXT:    v_and_b32_e32 v3, 7, v2
-; VI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v3
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v3
-; VI-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; VI-GISEL-NEXT:    v_or_b32_e32 v3, v3, v4
-; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; VI-GISEL-NEXT:    v_add_u32_e32 v2, vcc, v2, v3
-; VI-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7c00
-; VI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
-; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x7e00
+; VI-GISEL-NEXT:    v_or_b32_e32 v0, v3, v0
 ; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; VI-GISEL-NEXT:    s_movk_i32 s4, 0x40f
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc
-; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s4, v1
-; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v5, 12, v2
+; VI-GISEL-NEXT:    v_sub_u32_e32 v6, vcc, 1, v2
+; VI-GISEL-NEXT:    v_or_b32_e32 v5, v0, v5
+; VI-GISEL-NEXT:    v_med3_i32 v6, v6, 0, 13
+; VI-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
+; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v7, v6, v0
+; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
+; VI-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; VI-GISEL-NEXT:    v_or_b32_e32 v0, v7, v0
+; VI-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v2
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v5, v0, vcc
+; VI-GISEL-NEXT:    v_and_b32_e32 v5, 7, v0
+; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
+; VI-GISEL-NEXT:    v_cmp_lt_i32_e64 s[4:5], 5, v5
+; VI-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; VI-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
+; VI-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
+; VI-GISEL-NEXT:    v_add_u32_e32 v0, vcc, v0, v5
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x7c00
+; VI-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v2
+; VI-GISEL-NEXT:    v_lshlrev_b32_e32 v3, 9, v3
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; VI-GISEL-NEXT:    v_mov_b32_e32 v4, 0x40f
+; VI-GISEL-NEXT:    v_or_b32_e32 v3, 0x7c00, v3
+; VI-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v4
+; VI-GISEL-NEXT:    v_mov_b32_e32 v2, 0x8000
+; VI-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; VI-GISEL-NEXT:    v_and_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-GISEL-NEXT:    v_or_b32_e32 v0, v1, v0
 ; VI-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-SDAG-LABEL: fabs_fptrunc_f64_to_f16:
@@ -1994,38 +2111,39 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
 ; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v1
 ; GFX10-GISEL-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 20, v1
+; GFX10-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
+; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
 ; GFX10-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT:    v_sub_nc_u32_e32 v3, 0x3f1, v1
-; GFX10-GISEL-NEXT:    v_add_nc_u32_e32 v1, 0xfffffc10, v1
+; GFX10-GISEL-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
 ; GFX10-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX10-GISEL-NEXT:    v_med3_i32 v2, v3, 0, 13
-; GFX10-GISEL-NEXT:    v_or_b32_e32 v3, 0x1000, v0
-; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v4, v2, v3
-; GFX10-GISEL-NEXT:    v_lshlrev_b32_e32 v2, v2, v4
-; GFX10-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v3
-; GFX10-GISEL-NEXT:    v_lshl_or_b32 v3, v1, 12, v0
-; GFX10-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v1
-; GFX10-GISEL-NEXT:    v_or_b32_e32 v2, v4, v2
-; GFX10-GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, 7, v2
-; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX10-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v3
-; GFX10-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v3
+; GFX10-GISEL-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
+; GFX10-GISEL-NEXT:    v_and_or_b32 v0, 0xffe, v3, v0
+; GFX10-GISEL-NEXT:    v_med3_i32 v3, v4, 0, 13
+; GFX10-GISEL-NEXT:    v_or_b32_e32 v4, 0x1000, v0
+; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
+; GFX10-GISEL-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
+; GFX10-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX10-GISEL-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
 ; GFX10-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX10-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v1
-; GFX10-GISEL-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX10-GISEL-NEXT:    v_add_nc_u32_e32 v2, v2, v3
-; GFX10-GISEL-NEXT:    v_mov_b32_e32 v3, 0x7e00
-; GFX10-GISEL-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
+; GFX10-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX10-GISEL-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX10-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX10-GISEL-NEXT:    v_and_b32_e32 v4, 7, v3
+; GFX10-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
+; GFX10-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX10-GISEL-NEXT:    v_cmp_lt_i32_e64 s4, 5, v4
+; GFX10-GISEL-NEXT:    s_or_b32 s4, vcc_lo, s4
 ; GFX10-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX10-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v3, vcc_lo
-; GFX10-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v1
-; GFX10-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX10-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s4
+; GFX10-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX10-GISEL-NEXT:    v_add_nc_u32_e32 v3, v3, v4
+; GFX10-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX10-GISEL-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
+; GFX10-GISEL-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX10-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX10-GISEL-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX10-GISEL-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
 ; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX11-SDAG-LABEL: fabs_fptrunc_f64_to_f16:
@@ -2081,45 +2199,48 @@ define half @fabs_fptrunc_f64_to_f16(double %x) {
 ; GFX11-GISEL-NEXT:    v_and_b32_e32 v1, 0x7fffffff, v1
 ; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
 ; GFX11-GISEL-NEXT:    v_and_or_b32 v0, 0x1ff, v1, v0
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 8, v1
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 20, v1
+; GFX11-GISEL-NEXT:    v_bfe_u32 v2, v1, 20, 11
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 8, v1
 ; GFX11-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_sub_nc_u32_e32 v3, 0x3f1, v1
-; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v1, 0xfffffc10, v1
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v2, 0xfffffc10, v2
 ; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_or_b32 v0, 0xffe, v2, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_med3_i32 v2, v3, 0, 13
-; GFX11-GISEL-NEXT:    v_or_b32_e32 v3, 0x1000, v0
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v4, v2, v3
-; GFX11-GISEL-NEXT:    v_lshlrev_b32_e32 v2, v2, v4
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v2, v3
-; GFX11-GISEL-NEXT:    v_lshl_or_b32 v3, v1, 12, v0
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v1
-; GFX11-GISEL-NEXT:    v_or_b32_e32 v2, v4, v2
+; GFX11-GISEL-NEXT:    v_sub_nc_u32_e32 v4, 1, v2
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT:    v_and_or_b32 v0, 0xffe, v3, v0
+; GFX11-GISEL-NEXT:    v_med3_i32 v3, v4, 0, 13
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_or_b32_e32 v4, 0x1000, v0
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v5, v3, v4
 ; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
-; GFX11-GISEL-NEXT:    v_and_b32_e32 v3, 7, v2
-; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 5, v3
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v3
+; GFX11-GISEL-NEXT:    v_lshlrev_b32_e32 v3, v3, v5
+; GFX11-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, v3, v4
+; GFX11-GISEL-NEXT:    v_lshl_or_b32 v4, v2, 12, v0
 ; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 31, v1
-; GFX11-GISEL-NEXT:    v_or_b32_e32 v3, v3, v4
-; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT:    v_dual_mov_b32 v3, 0x7e00 :: v_dual_add_nc_u32 v2, v2, v3
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e32 v2, 0x7c00, v2, vcc_lo
+; GFX11-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 1, v2
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_or_b32_e32 v3, v5, v3
+; GFX11-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-NEXT:    v_and_b32_e32 v4, 7, v3
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v3, 2, v3
+; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 3, v4
+; GFX11-GISEL-NEXT:    v_cmp_lt_i32_e64 s0, 5, v4
+; GFX11-GISEL-NEXT:    s_or_b32 s0, vcc_lo, s0
 ; GFX11-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0
+; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-NEXT:    v_add_nc_u32_e32 v3, v3, v4
+; GFX11-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc_lo, 30, v2
+; GFX11-GISEL-NEXT:    v_lshl_or_b32 v0, v0, 9, 0x7c00
 ; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e32 v0, 0x7c00, v3, vcc_lo
-; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v1
-; GFX11-GISEL-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
+; GFX11-GISEL-NEXT:    v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
+; GFX11-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
+; GFX11-GISEL-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
+; GFX11-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-NEXT:    v_and_or_b32 v0, 0x8000, v1, v0
 ; GFX11-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %t = fptrunc double %x to half
   %a = call half @llvm.fabs.f16(half %t)
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
index b3ca80771144c..332e65874e45f 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.v2f16.no.fast.math.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=amdgpu9.50 -global-isel=0 < %s | FileCheck -check-prefixes=GFX950,GFX950-SDAG %s
-; RUN: llc -mtriple=amdgpu9.50 -global-isel=1 -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
+; RUN: llc -mtriple=amdgpu9.50 -global-isel=1 < %s | FileCheck -check-prefixes=GFX950,GFX950-GISEL %s
 
 define <2 x half> @v_test_cvt_v2f32_v2f16(<2 x float> %src) {
 ; GFX950-LABEL: v_test_cvt_v2f32_v2f16:
@@ -289,96 +289,181 @@ define half @fptrunc_v16f32_v16f16_extract_uses(<16 x float> %vec_float) {
 }
 
 define <2 x half> @v_test_cvt_v2f64_v2f16(<2 x double> %src) {
-; GFX950-LABEL: v_test_cvt_v2f64_v2f16:
-; GFX950:       ; %bb.0:
-; GFX950-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-NEXT:    s_movk_i32 s0, 0x1ff
-; GFX950-NEXT:    v_and_or_b32 v0, v1, s0, v0
-; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX950-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
-; GFX950-NEXT:    s_movk_i32 s1, 0xffe
-; GFX950-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX950-NEXT:    v_bfe_u32 v5, v1, 20, 11
-; GFX950-NEXT:    v_and_or_b32 v0, v4, s1, v0
-; GFX950-NEXT:    v_sub_u32_e32 v6, 0x3f1, v5
-; GFX950-NEXT:    v_or_b32_e32 v4, 0x1000, v0
-; GFX950-NEXT:    v_med3_i32 v6, v6, 0, 13
-; GFX950-NEXT:    v_lshrrev_b32_e32 v7, v6, v4
-; GFX950-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
-; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v4
-; GFX950-NEXT:    v_add_u32_e32 v5, 0xfffffc10, v5
-; GFX950-NEXT:    v_lshl_or_b32 v6, v5, 12, v0
-; GFX950-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; GFX950-NEXT:    v_or_b32_e32 v4, v7, v4
-; GFX950-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
-; GFX950-NEXT:    s_movk_i32 s2, 0x40f
-; GFX950-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
-; GFX950-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
-; GFX950-NEXT:    v_and_b32_e32 v6, 7, v4
-; GFX950-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
-; GFX950-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
-; GFX950-NEXT:    s_mov_b32 s3, 0x8000
-; GFX950-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
-; GFX950-NEXT:    s_nop 1
-; GFX950-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GFX950-NEXT:    v_or_b32_e32 v6, v6, v7
-; GFX950-NEXT:    v_add_u32_e32 v4, v4, v6
-; GFX950-NEXT:    v_mov_b32_e32 v6, 0x7c00
-; GFX950-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
-; GFX950-NEXT:    v_mov_b32_e32 v7, 0x7e00
-; GFX950-NEXT:    s_nop 0
-; GFX950-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
-; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; GFX950-NEXT:    s_nop 1
-; GFX950-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc
-; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v5
-; GFX950-NEXT:    s_nop 1
-; GFX950-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
-; GFX950-NEXT:    v_and_or_b32 v0, v1, s3, v0
-; GFX950-NEXT:    v_and_or_b32 v1, v3, s0, v2
-; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX950-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
-; GFX950-NEXT:    v_bfe_u32 v4, v3, 20, 11
-; GFX950-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX950-NEXT:    v_and_or_b32 v1, v2, s1, v1
-; GFX950-NEXT:    v_sub_u32_e32 v5, 0x3f1, v4
-; GFX950-NEXT:    v_or_b32_e32 v2, 0x1000, v1
-; GFX950-NEXT:    v_med3_i32 v5, v5, 0, 13
-; GFX950-NEXT:    v_lshrrev_b32_e32 v8, v5, v2
-; GFX950-NEXT:    v_lshlrev_b32_e32 v5, v5, v8
-; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v2
-; GFX950-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
-; GFX950-NEXT:    v_lshl_or_b32 v5, v4, 12, v1
-; GFX950-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX950-NEXT:    v_or_b32_e32 v2, v8, v2
-; GFX950-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
-; GFX950-NEXT:    s_mov_b32 s0, 0x5040100
-; GFX950-NEXT:    s_nop 0
-; GFX950-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
-; GFX950-NEXT:    v_and_b32_e32 v5, 7, v2
-; GFX950-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v5
-; GFX950-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
-; GFX950-NEXT:    s_nop 0
-; GFX950-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
-; GFX950-NEXT:    s_nop 1
-; GFX950-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX950-NEXT:    v_or_b32_e32 v5, v5, v8
-; GFX950-NEXT:    v_add_u32_e32 v2, v2, v5
-; GFX950-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v4
-; GFX950-NEXT:    s_nop 1
-; GFX950-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
-; GFX950-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; GFX950-NEXT:    s_nop 1
-; GFX950-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
-; GFX950-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v4
-; GFX950-NEXT:    s_nop 1
-; GFX950-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX950-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
-; GFX950-NEXT:    v_and_or_b32 v1, v2, s3, v1
-; GFX950-NEXT:    v_perm_b32 v0, v1, v0, s0
-; GFX950-NEXT:    s_setpc_b64 s[30:31]
+; GFX950-SDAG-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-SDAG:       ; %bb.0:
+; GFX950-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SDAG-NEXT:    s_movk_i32 s0, 0x1ff
+; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v1, s0, v0
+; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 8, v1
+; GFX950-SDAG-NEXT:    s_movk_i32 s1, 0xffe
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_bfe_u32 v5, v1, 20, 11
+; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v4, s1, v0
+; GFX950-SDAG-NEXT:    v_sub_u32_e32 v6, 0x3f1, v5
+; GFX950-SDAG-NEXT:    v_or_b32_e32 v4, 0x1000, v0
+; GFX950-SDAG-NEXT:    v_med3_i32 v6, v6, 0, 13
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v7, v6, v4
+; GFX950-SDAG-NEXT:    v_lshlrev_b32_e32 v6, v6, v7
+; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v6, v4
+; GFX950-SDAG-NEXT:    v_add_u32_e32 v5, 0xfffffc10, v5
+; GFX950-SDAG-NEXT:    v_lshl_or_b32 v6, v5, 12, v0
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_or_b32_e32 v4, v7, v4
+; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-SDAG-NEXT:    s_movk_i32 s2, 0x40f
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SDAG-NEXT:    v_and_b32_e32 v6, 7, v4
+; GFX950-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v6
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 2, v4
+; GFX950-SDAG-NEXT:    s_mov_b32 s3, 0x8000
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-SDAG-NEXT:    s_nop 1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_or_b32_e32 v6, v6, v7
+; GFX950-SDAG-NEXT:    v_add_u32_e32 v4, v4, v6
+; GFX950-SDAG-NEXT:    v_mov_b32_e32 v6, 0x7c00
+; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v5
+; GFX950-SDAG-NEXT:    v_mov_b32_e32 v7, 0x7e00
+; GFX950-SDAG-NEXT:    s_nop 0
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SDAG-NEXT:    s_nop 1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v0, v6, v7, vcc
+; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v5
+; GFX950-SDAG-NEXT:    s_nop 1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX950-SDAG-NEXT:    v_and_or_b32 v0, v1, s3, v0
+; GFX950-SDAG-NEXT:    v_and_or_b32 v1, v3, s0, v2
+; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 8, v3
+; GFX950-SDAG-NEXT:    v_bfe_u32 v4, v3, 20, 11
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_and_or_b32 v1, v2, s1, v1
+; GFX950-SDAG-NEXT:    v_sub_u32_e32 v5, 0x3f1, v4
+; GFX950-SDAG-NEXT:    v_or_b32_e32 v2, 0x1000, v1
+; GFX950-SDAG-NEXT:    v_med3_i32 v5, v5, 0, 13
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v8, v5, v2
+; GFX950-SDAG-NEXT:    v_lshlrev_b32_e32 v5, v5, v8
+; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, v5, v2
+; GFX950-SDAG-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
+; GFX950-SDAG-NEXT:    v_lshl_or_b32 v5, v4, 12, v1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_or_b32_e32 v2, v8, v2
+; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-SDAG-NEXT:    s_mov_b32 s0, 0x5040100
+; GFX950-SDAG-NEXT:    s_nop 0
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX950-SDAG-NEXT:    v_and_b32_e32 v5, 7, v2
+; GFX950-SDAG-NEXT:    v_cmp_lt_i32_e32 vcc, 5, v5
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SDAG-NEXT:    s_nop 0
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v5
+; GFX950-SDAG-NEXT:    s_nop 1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SDAG-NEXT:    v_or_b32_e32 v5, v5, v8
+; GFX950-SDAG-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX950-SDAG-NEXT:    v_cmp_gt_i32_e32 vcc, 31, v4
+; GFX950-SDAG-NEXT:    s_nop 1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-SDAG-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SDAG-NEXT:    s_nop 1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
+; GFX950-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, s2, v4
+; GFX950-SDAG-NEXT:    s_nop 1
+; GFX950-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-SDAG-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SDAG-NEXT:    v_and_or_b32 v1, v2, s3, v1
+; GFX950-SDAG-NEXT:    v_perm_b32 v0, v1, v0, s0
+; GFX950-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX950-GISEL-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-GISEL:       ; %bb.0:
+; GFX950-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v7, 0x1ff
+; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v1, v7, v0
+; GFX950-GISEL-NEXT:    v_bfe_u32 v4, v1, 20, 11
+; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-GISEL-NEXT:    v_add_u32_e32 v4, 0xfffffc10, v4
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v6, 0xffe
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v5, v6, v0
+; GFX950-GISEL-NEXT:    v_sub_u32_e32 v10, 1, v4
+; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-GISEL-NEXT:    v_lshl_or_b32 v9, v4, 12, v0
+; GFX950-GISEL-NEXT:    v_med3_i32 v10, v10, 0, 13
+; GFX950-GISEL-NEXT:    v_or_b32_e32 v0, 0x1000, v0
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v11, v10, v0
+; GFX950-GISEL-NEXT:    v_lshlrev_b32_e32 v10, v10, v11
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v10, v0
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v8, 0x7c00
+; GFX950-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-GISEL-NEXT:    v_or_b32_e32 v0, v11, v0
+; GFX950-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-GISEL-NEXT:    v_and_or_b32 v2, v3, v7, v2
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GFX950-GISEL-NEXT:    v_and_b32_e32 v9, 7, v0
+; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v9
+; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v9
+; GFX950-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 2, v0
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[0:1]
+; GFX950-GISEL-NEXT:    v_add_u32_e32 v0, v0, v9
+; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v4
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v9, 0x40f
+; GFX950-GISEL-NEXT:    s_nop 0
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
+; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v9
+; GFX950-GISEL-NEXT:    v_mov_b32_e32 v4, 0x8000
+; GFX950-GISEL-NEXT:    s_nop 0
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX950-GISEL-NEXT:    v_and_or_b32 v0, v1, v4, v0
+; GFX950-GISEL-NEXT:    v_bfe_u32 v1, v3, 20, 11
+; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-GISEL-NEXT:    v_add_u32_e32 v1, 0xfffffc10, v1
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v5, 8, v3
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-GISEL-NEXT:    v_and_or_b32 v2, v5, v6, v2
+; GFX950-GISEL-NEXT:    v_sub_u32_e32 v7, 1, v1
+; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX950-GISEL-NEXT:    v_lshl_or_b32 v6, v1, 12, v2
+; GFX950-GISEL-NEXT:    v_med3_i32 v7, v7, 0, 13
+; GFX950-GISEL-NEXT:    v_or_b32_e32 v2, 0x1000, v2
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v10, v7, v2
+; GFX950-GISEL-NEXT:    v_lshlrev_b32_e32 v7, v7, v10
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, v7, v2
+; GFX950-GISEL-NEXT:    v_lshl_or_b32 v5, v5, 9, v8
+; GFX950-GISEL-NEXT:    v_and_b32_e32 v0, 0xffff, v0
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-GISEL-NEXT:    v_or_b32_e32 v2, v10, v2
+; GFX950-GISEL-NEXT:    v_cmp_gt_i32_e32 vcc, 1, v1
+; GFX950-GISEL-NEXT:    s_nop 1
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-GISEL-NEXT:    v_and_b32_e32 v6, 7, v2
+; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e64 s[0:1], 5, v6
+; GFX950-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
+; GFX950-GISEL-NEXT:    v_add_u32_e32 v2, v2, v6
+; GFX950-GISEL-NEXT:    v_cmp_lt_i32_e32 vcc, 30, v1
+; GFX950-GISEL-NEXT:    s_nop 1
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc
+; GFX950-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v9
+; GFX950-GISEL-NEXT:    s_nop 1
+; GFX950-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v5, vcc
+; GFX950-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-GISEL-NEXT:    v_and_or_b32 v1, v2, v4, v1
+; GFX950-GISEL-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
+; GFX950-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %res = fptrunc <2 x double> %src to <2 x half>
   ret <2 x half> %res
 }

