[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Stop using changeTo in legalizer actions (PR #209203)
Petar Avramovic via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Jul 16 07:36:15 PDT 2026
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/209203
>From 68786c86b35da231d864680fd88dc1d58ac9e16f Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Mon, 13 Jul 2026 16:48:32 +0200
Subject: [PATCH] AMDGPU/GlobalISel: Stop using changeTo in legaizer actions
Use changeElementSizeTo or changeElementCountTo to preserve extended LLT.
---
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 48 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll | 19 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll | 138 +-
.../AMDGPU/GlobalISel/fp-int-conversions.ll | 2 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll | 14 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 409 +++--
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 368 +++--
...legalize-llvm.amdgcn.image.store.2d.d16.ll | 14 +-
.../CodeGen/AMDGPU/GlobalISel/llvm.powi.ll | 36 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll | 2 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll | 19 +-
llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll | 1334 +++++++++------
llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll | 1454 +++++++++++------
llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll | 1296 +++++++++------
llvm/test/CodeGen/AMDGPU/lrint.ll | 8 +-
llvm/test/CodeGen/AMDGPU/lround.ll | 40 +-
llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll | 4 +-
17 files changed, 3310 insertions(+), 1895 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 5afc1905cfde5..f08110bf0a4bc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -1156,9 +1156,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
FPTruncActions.scalarize(0).lower();
getActionDefinitionsBuilder(G_FPEXT)
- .legalFor({{S64, S32}, {S32, S16}})
- .narrowScalarFor({{S64, S16}}, changeTo(0, S32))
- .scalarize(0);
+ .legalFor({{S64, S32}, {S32, S16}})
+ .narrowScalarFor({{S64, S16}}, changeElementSizeTo(0, S32))
+ .scalarize(0);
auto &FSubActions = getActionDefinitionsBuilder({G_FSUB, G_STRICT_FSUB});
if (ST.has16BitInsts()) {
@@ -1224,7 +1224,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// TODO: Split s1->s64 during regbankselect for VALU.
auto &IToFP = getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
.legalFor({{S32, S32}, {S64, S32}})
- .widenScalarFor({{S16, S32}}, changeTo(0, S32))
+ .widenScalarFor({{S16, S32}}, changeElementSizeTo(0, S32))
.lowerIf(typeIs(1, S1))
.customFor({{S32, S64}, {S64, S64}});
if (ST.has16BitInsts())
@@ -1237,8 +1237,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
auto &FPToI = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
.legalFor({{S32, S32}, {S32, S64}})
.customFor({{S64, S32}, {S64, S64}})
- .widenScalarFor({{S32, S16}}, changeTo(1, S32))
- .narrowScalarFor({{S64, S16}}, changeTo(0, S32));
+ .widenScalarFor({{S32, S16}}, changeElementSizeTo(1, S32))
+ .narrowScalarFor({{S64, S16}}, changeElementSizeTo(0, S32));
if (ST.has16BitInsts())
FPToI.legalFor({{S16, S16}});
else
@@ -1254,7 +1254,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.legalFor({{S32, S32}, {S32, S64}, {S16, S32}})
.legalFor(ST.has16BitInsts(), {{S16, S16}})
.legalFor(ST.hasVCvtPkIU16F32(), {{V2S16, V2S32}})
- .narrowScalarFor({{S64, S16}}, changeTo(0, S32));
+ .narrowScalarFor({{S64, S16}}, changeElementSizeTo(0, S32));
// If available, widen width <16 to i16, intead of i32 so v_cvt_i16/u16_f16 can be used.
if (ST.has16BitInsts())
@@ -1933,14 +1933,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
// TODO: Support 16-bit shift amounts for all types
Shifts.widenScalarIf(
- [=](const LegalityQuery &Query) {
- // Use 16-bit shift amounts for any 16-bit shift. Otherwise we want a
- // 32-bit amount.
- const LLT ValTy = Query.Types[0];
- const LLT AmountTy = Query.Types[1];
- return ValTy.isScalar() && ValTy.getSizeInBits() <= 16 &&
- AmountTy.getSizeInBits() < 16;
- }, changeTo(1, S16));
+ [=](const LegalityQuery &Query) {
+ // Use 16-bit shift amounts for any 16-bit shift. Otherwise we want a
+ // 32-bit amount.
+ const LLT ValTy = Query.Types[0];
+ const LLT AmountTy = Query.Types[1];
+ return ValTy.isScalar() && ValTy.getSizeInBits() <= 16 &&
+ AmountTy.getSizeInBits() < 16;
+ },
+ changeElementSizeTo(1, S16));
Shifts.maxScalarIf(typeIs(0, S16), 1, S16);
Shifts.clampScalar(1, S32, S32);
Shifts.widenScalarToNextPow2(0, 16);
@@ -2070,7 +2071,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
.legalForCartesianProduct(AllS64Vectors, {S64})
.clampNumElements(0, V16S32, V32S32)
.clampNumElements(0, V2S64, V16S64)
- .fewerElementsIf(isWideVec16(0), changeTo(0, V2S16))
+ .fewerElementsIf(isWideVec16(0),
+ changeElementCountTo(0, ElementCount::getFixed(2)))
.moreElementsIf(isIllegalRegisterType(ST, 0),
moreElementsToNextExistingRegClass(0));
@@ -2136,7 +2138,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
oneMoreElement(BigTyIdx))
.fewerElementsIf(all(typeIs(0, S16), vectorWiderThan(1, 32),
elementTypeIs(1, S16)),
- changeTo(1, V2S16))
+ changeElementCountTo(1, ElementCount::getFixed(2)))
// Clamp the little scalar to s8-s256 and make it a power of 2. It's
// not worth considering the multiples of 64 since 2*192 and 2*384
// are not valid.
@@ -2157,12 +2159,12 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (Op == G_MERGE_VALUES) {
Builder.widenScalarIf(
- // TODO: Use 16-bit shifts if legal for 8-bit values?
- [=](const LegalityQuery &Query) {
- const LLT Ty = Query.Types[LitTyIdx];
- return Ty.getSizeInBits() < 32;
- },
- changeTo(LitTyIdx, S32));
+ // TODO: Use 16-bit shifts if legal for 8-bit values?
+ [=](const LegalityQuery &Query) {
+ const LLT Ty = Query.Types[LitTyIdx];
+ return Ty.getSizeInBits() < 32;
+ },
+ changeElementSizeTo(LitTyIdx, S32));
}
Builder.widenScalarIf(
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
index c94425b8897f8..d553f16d49013 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
@@ -949,9 +949,24 @@ define <3 x i16> @v_andn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {
; GFX6-LABEL: v_andn2_v3i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, v1, v3
-; GFX6-NEXT: v_bfi_b32 v0, v2, 0, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index e7e161060f4af..af02638e03189 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -30,24 +30,24 @@ define i8 @v_ashr_i8(i8 %value, i8 %amount) {
; GFX10-LABEL: v_ashr_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX10-NEXT: v_ashrrev_i16 v0, v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_ashr_i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ashr_i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 8
; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, v1, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = ashr i8 %value, %amount
@@ -1987,108 +1987,86 @@ define <4 x i2> @v_ashr_v4i2(<4 x i2> %value, <4 x i2> %amount) {
; GFX8-LABEL: v_ashr_v4i2:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, 14, v3
-; GFX8-NEXT: v_lshlrev_b16_e32 v2, 14, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v1, 14, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 14, v0
-; GFX8-NEXT: v_and_b32_e32 v7, 3, v7
-; GFX8-NEXT: v_ashrrev_i16_e32 v3, 14, v3
-; GFX8-NEXT: v_and_b32_e32 v6, 3, v6
-; GFX8-NEXT: v_ashrrev_i16_e32 v2, 14, v2
-; GFX8-NEXT: v_and_b32_e32 v5, 3, v5
-; GFX8-NEXT: v_ashrrev_i16_e32 v1, 14, v1
; GFX8-NEXT: v_and_b32_e32 v4, 3, v4
-; GFX8-NEXT: v_ashrrev_i16_e32 v0, 14, v0
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 2
; GFX8-NEXT: v_ashrrev_i16_e32 v0, v4, v0
-; GFX8-NEXT: v_ashrrev_i16_e32 v1, v5, v1
-; GFX8-NEXT: v_ashrrev_i16_e32 v2, v6, v2
-; GFX8-NEXT: v_ashrrev_i16_e32 v3, v7, v3
+; GFX8-NEXT: v_and_b32_e32 v4, 3, v5
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 2
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, v4, v1
+; GFX8-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 2
+; GFX8-NEXT: v_ashrrev_i16_e32 v2, v4, v2
+; GFX8-NEXT: v_and_b32_e32 v4, 3, v7
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 2
+; GFX8-NEXT: v_ashrrev_i16_e32 v3, v4, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ashr_v4i2:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
-; GFX9-NEXT: v_perm_b32 v1, v3, v2, s4
-; GFX9-NEXT: v_pk_lshlrev_b16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX9-NEXT: v_and_b32_e32 v3, 3, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 3, v4
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 2
+; GFX9-NEXT: v_ashrrev_i16_e32 v0, v4, v0
; GFX9-NEXT: v_and_b32_e32 v4, 3, v5
-; GFX9-NEXT: v_and_b32_e32 v2, 3, v6
-; GFX9-NEXT: v_and_b32_e32 v5, 3, v7
-; GFX9-NEXT: v_pk_lshlrev_b16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX9-NEXT: v_pk_ashrrev_i16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX9-NEXT: v_perm_b32 v2, v5, v2, s4
-; GFX9-NEXT: v_pk_ashrrev_i16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX9-NEXT: v_pk_ashrrev_i16 v2, v2, v1
-; GFX9-NEXT: v_perm_b32 v1, v4, v3, s4
-; GFX9-NEXT: v_pk_ashrrev_i16 v0, v1, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 2
+; GFX9-NEXT: v_ashrrev_i16_e32 v1, v4, v1
+; GFX9-NEXT: v_and_b32_e32 v4, 3, v6
+; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 2
+; GFX9-NEXT: v_ashrrev_i16_e32 v2, v4, v2
+; GFX9-NEXT: v_and_b32_e32 v4, 3, v7
+; GFX9-NEXT: v_bfe_i32 v3, v3, 0, 2
+; GFX9-NEXT: v_ashrrev_i16_e32 v3, v4, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ashr_v4i2:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX10-NEXT: v_and_b32_e32 v2, 3, v4
-; GFX10-NEXT: v_and_b32_e32 v3, 3, v6
-; GFX10-NEXT: v_and_b32_e32 v4, 3, v7
-; GFX10-NEXT: v_pk_lshlrev_b16 v0, 14, v0 op_sel_hi:[0,1]
+; GFX10-NEXT: v_and_b32_e32 v4, 3, v4
+; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 2
; GFX10-NEXT: v_and_b32_e32 v5, 3, v5
-; GFX10-NEXT: v_pk_lshlrev_b16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX10-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX10-NEXT: v_pk_ashrrev_i16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX10-NEXT: v_perm_b32 v2, v5, v2, 0x5040100
-; GFX10-NEXT: v_pk_ashrrev_i16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX10-NEXT: v_pk_ashrrev_i16 v0, v2, v0
-; GFX10-NEXT: v_pk_ashrrev_i16 v2, v3, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; GFX10-NEXT: v_bfe_i32 v1, v1, 0, 2
+; GFX10-NEXT: v_and_b32_e32 v6, 3, v6
+; GFX10-NEXT: v_bfe_i32 v2, v2, 0, 2
+; GFX10-NEXT: v_and_b32_e32 v7, 3, v7
+; GFX10-NEXT: v_bfe_i32 v3, v3, 0, 2
+; GFX10-NEXT: v_ashrrev_i16 v0, v4, v0
+; GFX10-NEXT: v_ashrrev_i16 v1, v5, v1
+; GFX10-NEXT: v_ashrrev_i16 v2, v6, v2
+; GFX10-NEXT: v_ashrrev_i16 v3, v7, v3
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_ashr_v4i2:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
-; GFX11-TRUE16-NEXT: v_and_b16 v2.h, v5.l, 3
-; GFX11-TRUE16-NEXT: v_and_b16 v2.l, v4.l, 3
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_and_b16 v4.h, v7.l, 3
-; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_and_b16 v4.l, v6.l, 3
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v3, 14, v1 op_sel_hi:[0,1]
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v1, v2, v0
-; GFX11-TRUE16-NEXT: v_pk_ashrrev_i16 v3, v4, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v3.h
+; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 2
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 2
+; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 2
+; GFX11-TRUE16-NEXT: v_and_b16 v4.l, v4.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v5.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, v6.l, 3
+; GFX11-TRUE16-NEXT: v_and_b16 v2.h, v7.l, 3
+; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 2
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, v4.l, v0.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v1.l, v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v2.l, v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_ashrrev_i16 v3.l, v2.h, v3.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_ashr_v4i2:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 3, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 3, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v7
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, 14, v0 op_sel_hi:[0,1]
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 3, v4
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 3, v5
-; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v0, 14, v0 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v2, 0x5040100
-; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v1, 14, v1 op_sel_hi:[0,1]
-; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_pk_ashrrev_i16 v2, v3, v1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v2
+; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v6
+; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 3, v7
+; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 2
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, v4, v0
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v1, v5, v1
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v2, v6, v2
+; GFX11-FAKE16-NEXT: v_ashrrev_i16 v3, v7, v3
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%result = ashr <4 x i2> %value, %amount
ret <4 x i2> %result
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
index 88496708fa917..7317d24d3e1be 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
@@ -2,7 +2,7 @@
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu10.10 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GCN,PREGFX12,TRUE16
; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,PREGFX12,PREGFX12-FAKE16
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,GFX12
+; RUN: llc -global-isel -mtriple=amdgpu12.00 < %s | FileCheck %s --check-prefixes=GCN,FAKE16,GFX12
define amdgpu_ps void @s_fptoui_f16_to_i16(half inreg %x, ptr addrspace(1) %out) {
; PREGFX12-FAKE16-LABEL: s_fptoui_f16_to_i16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
index 1213749b0e656..1c5825c3f2633 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fpext.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu12.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdpal -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-amd-amdpal -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
define amdgpu_ps float @fpext_f16_to_f32_uniform(half inreg %a) {
; GFX11-LABEL: fpext_f16_to_f32_uniform:
@@ -89,9 +89,9 @@ define amdgpu_ps void @fpext_f16_to_f64_uniform(half inreg %a, ptr addrspace(1)
;
; GFX12-LABEL: fpext_f16_to_f64_uniform:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_cvt_f32_f16_e32 v2, s0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; GFX12-NEXT: s_cvt_f32_f16 s0, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-NEXT: v_cvt_f64_f32_e32 v[2:3], s0
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX12-NEXT: s_endpgm
%result = fpext half %a to double
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 0bfad55132a82..c814e1c4ec7f1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -227,36 +227,73 @@ define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-LABEL: v_fshl_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 7, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v1
+; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v3
+; GFX8-NEXT: s_mul_i32 s5, s4, -7
+; GFX8-NEXT: v_mul_hi_u32 v3, v3, s5
+; GFX8-NEXT: v_readfirstlane_b32 s5, v3
+; GFX8-NEXT: s_add_i32 s4, s4, s5
+; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4
+; GFX8-NEXT: v_mul_lo_u32 v3, v3, -7
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, -7, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, -7, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x2493
-; GFX8-NEXT: v_mul_u32_u24_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v3, 7
-; GFX8-NEXT: v_mul_lo_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_sub_u16_e32 v1, v2, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, 7, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_i7:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b16 v2.l, 0x7f, v2.l
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
+; GFX11-NEXT: v_and_b32_e32 v2, 0x7f, v2
; GFX11-NEXT: v_and_b16 v0.h, 0x7f, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 7, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cvt_u32_u16_e32 v3, v2.l
-; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_u32_u24_e32 v3, 0x2493, v3
-; GFX11-NEXT: v_mul_lo_u16 v1.l, v3.h, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u16 v0.h, v2.l, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: s_mul_i32 s1, s0, -7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_add_i32 s0, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v2, -7, v3
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_nc_u32_e32 v3, -7, v2
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_nc_u16 v1.l, 6, v2.l
+; GFX11-NEXT: v_and_b16 v1.h, 0x7f, v2.l
+; GFX11-NEXT: v_and_b16 v1.l, 0x7f, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b16 v0.l, 7, v0.l
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i7:
; GFX9: ; %bb.0:
@@ -373,11 +410,10 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX8-LABEL: s_fshl_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
-; GFX8-NEXT: s_and_b32 s3, s2, 7
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX8-NEXT: s_xor_b32 s2, s2, -1
+; GFX8-NEXT: s_and_b32 s3, s2, 7
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
-; GFX8-NEXT: s_and_b32 s2, s2, 7
+; GFX8-NEXT: s_andn2_b32 s2, 7, s2
; GFX8-NEXT: s_lshl_b32 s0, s0, s3
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
; GFX8-NEXT: s_or_b32 s0, s0, s1
@@ -388,9 +424,8 @@ define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_and_b32 s3, s2, 7
; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_xor_b32 s2, s2, -1
+; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_and_b32 s2, s2, 7
; GFX11-NEXT: s_lshl_b32 s0, s0, s3
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -437,24 +472,30 @@ define i8 @v_fshl_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX8-LABEL: v_fshl_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v1, 7, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 7, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
+; GFX8-NEXT: v_mov_b32_e32 v3, 1
+; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-NEXT: v_and_b16 v0.h, v2.l, 7
-; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: v_xor_b16 v1.l, v2.l, -1
+; GFX11-NEXT: v_and_b16 v1.h, v2.l, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
+; GFX11-NEXT: v_and_b16 v1.l, v1.l, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.l, v0.h
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_i8:
; GFX9: ; %bb.0:
@@ -731,23 +772,21 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s4, s1, 8
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
+; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshr_b32 s5, s2, 8
; GFX8-NEXT: s_and_b32 s6, s2, 7
-; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX8-NEXT: s_xor_b32 s2, s2, -1
; GFX8-NEXT: s_lshr_b32 s1, s1, 1
-; GFX8-NEXT: s_and_b32 s2, s2, 7
+; GFX8-NEXT: s_andn2_b32 s2, 7, s2
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
+; GFX8-NEXT: s_and_b32 s2, s4, 0xff
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s5, 7
-; GFX8-NEXT: s_and_b32 s2, s4, 0xff
-; GFX8-NEXT: s_lshl_b32 s1, s3, s1
; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
-; GFX8-NEXT: s_xor_b32 s3, s5, -1
+; GFX8-NEXT: s_lshl_b32 s1, s3, s1
; GFX8-NEXT: s_lshr_b32 s2, s2, 1
-; GFX8-NEXT: s_and_b32 s3, s3, 7
+; GFX8-NEXT: s_andn2_b32 s3, 7, s5
; GFX8-NEXT: s_lshr_b32 s2, s2, s3
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
@@ -760,20 +799,18 @@ define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX11: ; %bb.0:
; GFX11-NEXT: s_lshr_b32 s4, s1, 8
; GFX11-NEXT: s_lshr_b32 s5, s2, 8
-; GFX11-NEXT: s_and_b32 s6, s2, 7
; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, s6
-; GFX11-NEXT: s_and_b32 s6, s5, 7
+; GFX11-NEXT: s_and_b32 s6, s2, 7
; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-NEXT: s_xor_b32 s5, s5, -1
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_xor_b32 s2, s2, -1
+; GFX11-NEXT: s_lshl_b32 s0, s0, s6
+; GFX11-NEXT: s_and_b32 s6, s5, 7
; GFX11-NEXT: s_lshr_b32 s4, s4, 1
-; GFX11-NEXT: s_and_b32 s5, s5, 7
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s5
; GFX11-NEXT: s_lshr_b32 s1, s1, 1
-; GFX11-NEXT: s_and_b32 s2, s2, 7
+; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
; GFX11-NEXT: s_lshl_b32 s3, s3, s6
; GFX11-NEXT: s_lshr_b32 s4, s4, s5
; GFX11-NEXT: s_lshr_b32 s1, s1, s2
@@ -873,37 +910,58 @@ define i16 @v_fshl_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX8-LABEL: v_fshl_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX8-NEXT: v_bfe_u32 v4, v2, 8, 3
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, v4, v3
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v1, 7, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff00, v3
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v6, 7, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v6, v0
+; GFX8-NEXT: v_mov_b32_e32 v6, 1
+; GFX8-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 7, v5
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, v1, v3
+; GFX8-NEXT: v_xor_b32_e32 v3, -1, v5
+; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_and_b32_e32 v3, 7, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, v3, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_v2i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b16 v0.h, 8, v2.l
-; GFX11-NEXT: v_lshrrev_b16 v1.h, 8, v1.l
-; GFX11-NEXT: v_and_b16 v2.h, 0xff00, v0.l
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v0
; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
+; GFX11-NEXT: v_xor_b16 v2.h, v2.l, -1
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v3.l
+; GFX11-NEXT: v_xor_b16 v1.h, v4.l, -1
+; GFX11-NEXT: v_and_b16 v3.l, v4.l, 7
; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
-; GFX11-NEXT: v_and_b16 v0.h, v0.h, 7
-; GFX11-NEXT: v_or_b16 v1.h, v2.h, v1.h
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshrrev_b16 v1.l, 1, v1.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, 1, v0.h
+; GFX11-NEXT: v_and_b16 v1.h, v1.h, 7
+; GFX11-NEXT: v_and_b16 v2.h, v2.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v3.l, v3.l, v5.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.h, v0.h
+; GFX11-NEXT: v_lshrrev_b16 v1.l, v2.h, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b16 v0.h, v3.l, v0.h
; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.h, v0.h, v1.h
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b16 v0.l, v2.l, v0.l
-; GFX11-NEXT: v_and_b16 v0.h, 0xff00, v0.h
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshrrev_b16 v0.l, 8, v0.l
+; GFX11-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v2i8:
@@ -1051,13 +1109,12 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshr_b32 s5, s0, 24
; GFX8-NEXT: s_lshl_b32 s0, s0, s11
; GFX8-NEXT: s_and_b32 s11, s1, 0xff
+; GFX8-NEXT: s_and_b32 s11, 0xffff, s11
; GFX8-NEXT: s_lshr_b32 s8, s2, 8
; GFX8-NEXT: s_lshr_b32 s9, s2, 16
; GFX8-NEXT: s_lshr_b32 s10, s2, 24
-; GFX8-NEXT: s_and_b32 s11, 0xffff, s11
-; GFX8-NEXT: s_xor_b32 s2, s2, -1
; GFX8-NEXT: s_lshr_b32 s11, s11, 1
-; GFX8-NEXT: s_and_b32 s2, s2, 7
+; GFX8-NEXT: s_andn2_b32 s2, 7, s2
; GFX8-NEXT: s_lshr_b32 s2, s11, s2
; GFX8-NEXT: s_lshr_b32 s6, s1, 8
; GFX8-NEXT: s_or_b32 s0, s0, s2
@@ -1065,9 +1122,8 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshl_b32 s2, s3, s2
; GFX8-NEXT: s_and_b32 s3, s6, 0xff
; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX8-NEXT: s_xor_b32 s6, s8, -1
; GFX8-NEXT: s_lshr_b32 s3, s3, 1
-; GFX8-NEXT: s_and_b32 s6, s6, 7
+; GFX8-NEXT: s_andn2_b32 s6, 7, s8
; GFX8-NEXT: s_lshr_b32 s3, s3, s6
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_or_b32 s2, s2, s3
@@ -1075,16 +1131,14 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshl_b32 s3, s4, s3
; GFX8-NEXT: s_and_b32 s4, s7, 0xff
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX8-NEXT: s_xor_b32 s6, s9, -1
; GFX8-NEXT: s_lshr_b32 s4, s4, 1
-; GFX8-NEXT: s_and_b32 s6, s6, 7
+; GFX8-NEXT: s_andn2_b32 s6, 7, s9
; GFX8-NEXT: s_lshr_b32 s4, s4, s6
; GFX8-NEXT: s_or_b32 s3, s3, s4
; GFX8-NEXT: s_and_b32 s4, s10, 7
; GFX8-NEXT: s_lshl_b32 s4, s5, s4
-; GFX8-NEXT: s_xor_b32 s5, s10, -1
; GFX8-NEXT: s_lshr_b32 s1, s1, 25
-; GFX8-NEXT: s_and_b32 s5, s5, 7
+; GFX8-NEXT: s_andn2_b32 s5, 7, s10
; GFX8-NEXT: s_and_b32 s2, s2, 0xff
; GFX8-NEXT: s_lshr_b32 s1, s1, s5
; GFX8-NEXT: s_and_b32 s0, s0, 0xff
@@ -1101,44 +1155,40 @@ define amdgpu_ps i32 @s_fshl_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
;
; GFX11-LABEL: s_fshl_v4i8:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s11, s1, 0xff
+; GFX11-NEXT: s_and_b32 s10, s1, 0xff
; GFX11-NEXT: s_lshr_b32 s6, s1, 8
+; GFX11-NEXT: s_and_b32 s10, 0xffff, s10
; GFX11-NEXT: s_lshr_b32 s8, s2, 8
; GFX11-NEXT: s_lshr_b32 s9, s2, 16
-; GFX11-NEXT: s_lshr_b32 s10, s2, 24
+; GFX11-NEXT: s_lshr_b32 s11, s2, 24
; GFX11-NEXT: s_and_b32 s12, s2, 7
-; GFX11-NEXT: s_and_b32 s11, 0xffff, s11
-; GFX11-NEXT: s_xor_b32 s2, s2, -1
-; GFX11-NEXT: s_lshr_b32 s11, s11, 1
-; GFX11-NEXT: s_and_b32 s2, s2, 7
-; GFX11-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-NEXT: s_lshr_b32 s2, s11, s2
-; GFX11-NEXT: s_and_b32 s11, s8, 7
-; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
-; GFX11-NEXT: s_xor_b32 s8, s8, -1
+; GFX11-NEXT: s_lshr_b32 s10, s10, 1
+; GFX11-NEXT: s_and_not1_b32 s2, 7, s2
; GFX11-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-NEXT: s_lshr_b32 s6, s6, 1
-; GFX11-NEXT: s_and_b32 s8, s8, 7
; GFX11-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-NEXT: s_lshr_b32 s5, s0, 24
-; GFX11-NEXT: s_lshr_b32 s7, s1, 16
; GFX11-NEXT: s_lshl_b32 s0, s0, s12
-; GFX11-NEXT: s_lshl_b32 s3, s3, s11
-; GFX11-NEXT: s_lshr_b32 s6, s6, s8
+; GFX11-NEXT: s_lshr_b32 s2, s10, s2
+; GFX11-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-NEXT: s_or_b32 s0, s0, s2
-; GFX11-NEXT: s_or_b32 s2, s3, s6
-; GFX11-NEXT: s_and_b32 s3, s7, 0xff
-; GFX11-NEXT: s_xor_b32 s7, s9, -1
-; GFX11-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX11-NEXT: s_and_b32 s7, s7, 7
-; GFX11-NEXT: s_lshr_b32 s3, s3, 1
+; GFX11-NEXT: s_and_b32 s2, 0xffff, s6
+; GFX11-NEXT: s_lshr_b32 s7, s1, 16
+; GFX11-NEXT: s_and_b32 s6, s8, 7
+; GFX11-NEXT: s_lshr_b32 s2, s2, 1
+; GFX11-NEXT: s_and_not1_b32 s8, 7, s8
+; GFX11-NEXT: s_lshl_b32 s3, s3, s6
+; GFX11-NEXT: s_lshr_b32 s2, s2, s8
+; GFX11-NEXT: s_and_b32 s6, s7, 0xff
+; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_and_b32 s3, 0xffff, s6
; GFX11-NEXT: s_and_b32 s6, s9, 7
-; GFX11-NEXT: s_lshr_b32 s3, s3, s7
-; GFX11-NEXT: s_xor_b32 s7, s10, -1
+; GFX11-NEXT: s_lshr_b32 s3, s3, 1
+; GFX11-NEXT: s_and_not1_b32 s7, 7, s9
; GFX11-NEXT: s_lshl_b32 s4, s4, s6
-; GFX11-NEXT: s_and_b32 s6, s10, 7
+; GFX11-NEXT: s_lshr_b32 s3, s3, s7
+; GFX11-NEXT: s_and_b32 s6, s11, 7
; GFX11-NEXT: s_lshr_b32 s1, s1, 25
-; GFX11-NEXT: s_and_b32 s7, s7, 7
+; GFX11-NEXT: s_and_not1_b32 s7, 7, s11
; GFX11-NEXT: s_lshl_b32 s5, s5, s6
; GFX11-NEXT: s_lshr_b32 s1, s1, s7
; GFX11-NEXT: s_or_b32 s3, s4, s3
@@ -1316,64 +1366,107 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-LABEL: v_fshl_v4i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX8-NEXT: v_bfe_u32 v4, v2, 8, 3
-; GFX8-NEXT: v_lshlrev_b16_e32 v3, v4, v3
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v0
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v5, 7, v2
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, v5, v4
-; GFX8-NEXT: s_mov_b32 s4, 0xc0c0105
-; GFX8-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff00
-; GFX8-NEXT: v_and_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v5, 7
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT: v_and_b32_sdwa v6, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, v6, v4
-; GFX8-NEXT: v_mov_b32_e32 v6, 0xff
-; GFX8-NEXT: v_and_b32_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v6, 8
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_mov_b32_e32 v8, 1
+; GFX8-NEXT: v_xor_b32_e32 v10, -1, v2
+; GFX8-NEXT: v_and_b32_e32 v6, 7, v2
+; GFX8-NEXT: v_lshrrev_b16_sdwa v9, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_and_b32_e32 v10, 7, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v6, v6, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v9, v10, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX8-NEXT: v_or_b32_e32 v6, v6, v9
+; GFX8-NEXT: v_and_b32_e32 v9, 7, v5
+; GFX8-NEXT: v_xor_b32_e32 v5, -1, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_and_b32_e32 v5, 7, v5
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, v9, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xff
+; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_mov_b32_e32 v4, 7
+; GFX8-NEXT: v_mov_b32_e32 v8, -1
+; GFX8-NEXT: v_and_b32_sdwa v5, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v7, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_xor_b32_sdwa v9, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 25, v1
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, v9, v7
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-NEXT: v_and_b32_sdwa v1, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0
-; GFX8-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, 8
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshl_v4i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b16 v3.l, 8, v1.l
-; GFX11-NEXT: v_and_b16 v3.h, 0xff00, v0.l
-; GFX11-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v1
-; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX11-NEXT: v_or_b16 v3.l, v3.h, v3.l
-; GFX11-NEXT: v_and_b16 v3.h, v4.l, 7
-; GFX11-NEXT: v_and_b16 v4.l, 0xff00, v0.h
-; GFX11-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.l
-; GFX11-NEXT: v_and_b16 v1.l, v2.l, 7
-; GFX11-NEXT: v_or_b16 v2.l, v4.l, v6.l
-; GFX11-NEXT: v_and_b16 v4.l, v5.l, 7
-; GFX11-NEXT: v_or_b16 v0.h, v0.h, v1.h
-; GFX11-NEXT: v_and_b16 v1.h, v2.h, 7
-; GFX11-NEXT: v_lshlrev_b16 v3.l, v3.h, v3.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, v1.l, v0.l
-; GFX11-NEXT: v_lshlrev_b16 v1.l, v4.l, v2.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b16 v2.l, v1.h, v0.h
-; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0xc0c0105
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, v2, v1, 0xc0c0105
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 24, v2
+; GFX11-NEXT: v_and_b16 v3.l, 0xff, v3.l
+; GFX11-NEXT: v_xor_b16 v3.h, v4.l, -1
+; GFX11-NEXT: v_and_b16 v4.l, v4.l, 7
+; GFX11-NEXT: v_and_b16 v4.h, 0xff, v6.l
+; GFX11-NEXT: v_xor_b16 v5.h, v10.l, -1
+; GFX11-NEXT: v_lshrrev_b16 v3.l, 1, v3.l
+; GFX11-NEXT: v_and_b16 v3.h, v3.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v4.l, v4.l, v5.l
+; GFX11-NEXT: v_xor_b16 v5.l, v9.l, -1
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 24, v0
+; GFX11-NEXT: v_and_b16 v0.h, v2.l, 7
+; GFX11-NEXT: v_and_b16 v2.h, 0xff, v1.l
+; GFX11-NEXT: v_xor_b16 v2.l, v2.l, -1
+; GFX11-NEXT: v_lshrrev_b16 v3.l, v3.h, v3.l
+; GFX11-NEXT: v_and_b16 v3.h, v9.l, 7
+; GFX11-NEXT: v_lshrrev_b16 v4.h, 1, v4.h
+; GFX11-NEXT: v_and_b16 v5.l, v5.l, 7
+; GFX11-NEXT: v_and_b16 v6.l, v10.l, 7
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 25, v1
+; GFX11-NEXT: v_and_b16 v1.l, v5.h, 7
+; GFX11-NEXT: v_lshrrev_b16 v2.h, 1, v2.h
+; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
+; GFX11-NEXT: v_or_b16 v4.l, v4.l, v3.l
+; GFX11-NEXT: v_lshlrev_b16 v1.h, v3.h, v7.l
+; GFX11-NEXT: v_lshrrev_b16 v3.l, v5.l, v4.h
+; GFX11-NEXT: v_lshlrev_b16 v3.h, v6.l, v8.l
+; GFX11-NEXT: v_lshrrev_b16 v1.l, v1.l, v9.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v2.l, v2.h
+; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v4
+; GFX11-NEXT: v_or_b16 v3.l, v1.h, v3.l
+; GFX11-NEXT: v_or_b16 v1.l, v3.h, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_or_b32 v0, 0xff, v0, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshl_v4i8:
; GFX9: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 9ab63e303c895..f48a6fe809160 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -229,33 +229,72 @@ define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {
; GFX8-LABEL: v_fshr_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
+; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 7, v0
+; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX8-NEXT: v_readfirstlane_b32 s4, v3
+; GFX8-NEXT: s_mul_i32 s5, s4, -7
+; GFX8-NEXT: v_mul_hi_u32 v3, v3, s5
+; GFX8-NEXT: v_readfirstlane_b32 s5, v3
+; GFX8-NEXT: s_add_i32 s4, s4, s5
+; GFX8-NEXT: v_mul_hi_u32 v3, v2, s4
+; GFX8-NEXT: v_mul_lo_u32 v3, v3, -7
+; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v3
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, -7, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_add_u32_e32 v3, vcc, -7, v2
+; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 7, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_sub_u16_e32 v3, 6, v2
; GFX8-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0x7f, v3
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-NEXT: v_mov_b32_e32 v1, 0x2493
-; GFX8-NEXT: v_mul_u32_u24_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v3, 7
-; GFX8-NEXT: v_mul_lo_u16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_sub_u16_e32 v1, v2, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_i7:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b16 v2.l, 0x7f, v2.l
-; GFX11-NEXT: v_and_b16 v0.h, 0x7f, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 7, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cvt_u32_u16_e32 v3, v2.l
-; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mul_u32_u24_e32 v3, 0x2493, v3
-; GFX11-NEXT: v_mul_lo_u16 v1.l, v3.h, 7
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v3, 7
+; GFX11-NEXT: v_and_b32_e32 v2, 0x7f, v2
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_and_b16 v1.l, 0x7f, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_rcp_iflag_f32_e32 v3, v3
+; GFX11-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
+; GFX11-NEXT: v_cvt_u32_f32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: s_mul_i32 s1, s0, -7
+; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_add_i32 s0, s0, s1
+; GFX11-NEXT: v_mul_hi_u32 v5, v2, s0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_sub_nc_u16 v0.h, v2.l, v1.l
-; GFX11-NEXT: v_lshrrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: v_mad_u64_u32 v[3:4], null, v5, -7, v[2:3]
+; GFX11-NEXT: v_add_nc_u32_e32 v2, -7, v3
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX11-NEXT: v_add_nc_u32_e32 v3, -7, v2
+; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, 7, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX11-NEXT: v_sub_nc_u16 v0.h, 6, v2.l
+; GFX11-NEXT: v_and_b16 v1.h, 0x7f, v2.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b16 v0.h, 0x7f, v0.h
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i7:
; GFX9: ; %bb.0:
@@ -371,10 +410,9 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX8-LABEL: s_fshr_i8:
; GFX8: ; %bb.0:
-; GFX8-NEXT: s_xor_b32 s3, s2, -1
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: s_and_b32 s3, s3, 7
+; GFX8-NEXT: s_andn2_b32 s3, 7, s2
; GFX8-NEXT: s_and_b32 s2, s2, 7
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, s3
@@ -384,10 +422,9 @@ define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
;
; GFX11-LABEL: s_fshr_i8:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_xor_b32 s3, s2, -1
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_and_b32 s3, s3, 7
+; GFX11-NEXT: s_and_not1_b32 s3, 7, s2
; GFX11-NEXT: s_and_b32 s2, s2, 7
; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
; GFX11-NEXT: s_lshl_b32 s0, s0, s3
@@ -437,21 +474,28 @@ define i8 @v_fshr_i8(i8 %lhs, i8 %rhs, i8 %amt) {
; GFX8-LABEL: v_fshr_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v1, 7, v2
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0
+; GFX8-NEXT: v_xor_b32_e32 v3, -1, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 7, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v3, v0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_xor_b16 v0.h, v2.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_and_b16 v1.h, v2.l, 7
+; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b16 v0.h, v0.h, 7
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.h, v1.l
; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
-; GFX11-NEXT: v_and_b16 v0.h, v2.l, 7
-; GFX11-NEXT: v_lshrrev_b16 v0.l, v0.h, v0.l
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_i8:
; GFX9: ; %bb.0:
@@ -726,20 +770,18 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
; GFX8-LABEL: s_fshr_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_lshr_b32 s4, s1, 8
-; GFX8-NEXT: s_xor_b32 s6, s2, -1
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
; GFX8-NEXT: s_lshr_b32 s5, s2, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: s_and_b32 s6, s6, 7
+; GFX8-NEXT: s_andn2_b32 s6, 7, s2
; GFX8-NEXT: s_and_b32 s2, s2, 7
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, s6
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
-; GFX8-NEXT: s_xor_b32 s2, s5, -1
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_lshl_b32 s1, s3, 1
-; GFX8-NEXT: s_and_b32 s2, s2, 7
+; GFX8-NEXT: s_andn2_b32 s2, 7, s5
; GFX8-NEXT: s_and_b32 s3, s4, 0xff
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s2, s5, 7
@@ -754,18 +796,16 @@ define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 in
;
; GFX11-LABEL: s_fshr_v2i8:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_xor_b32 s5, s2, -1
-; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_lshr_b32 s4, s1, 8
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_and_b32 s5, s5, 7
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s2
; GFX11-NEXT: s_lshr_b32 s6, s2, 8
-; GFX11-NEXT: s_lshl_b32 s0, s0, s5
-; GFX11-NEXT: s_xor_b32 s5, s6, -1
; GFX11-NEXT: s_and_b32 s4, s4, 0xff
+; GFX11-NEXT: s_lshl_b32 s0, s0, s5
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_lshl_b32 s3, s3, 1
-; GFX11-NEXT: s_and_b32 s5, s5, 7
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s6
; GFX11-NEXT: s_and_b32 s6, s6, 7
; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
; GFX11-NEXT: s_and_b32 s2, s2, 7
@@ -870,36 +910,57 @@ define i16 @v_fshr_v2i8(i16 %lhs.arg, i16 %rhs.arg, i16 %amt.arg) {
; GFX8-LABEL: v_fshr_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
-; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX8-NEXT: v_bfe_u32 v4, v2, 8, 3
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v1, 7, v2
-; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v4, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_xor_b32_e32 v6, -1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v6, 7, v6
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v6, v0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_xor_b32_e32 v2, -1, v5
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, v2, v1
+; GFX8-NEXT: v_and_b32_e32 v2, 7, v5
+; GFX8-NEXT: v_lshrrev_b16_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_v2i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b16 v0.h, 8, v2.l
-; GFX11-NEXT: v_lshrrev_b16 v1.h, 8, v1.l
-; GFX11-NEXT: v_and_b16 v2.h, 0xff00, v0.l
-; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 8, v1
+; GFX11-NEXT: v_xor_b16 v1.h, v2.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_xor_b16 v0.h, v3.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v2.h, 1, v4.l
+; GFX11-NEXT: v_and_b16 v3.l, v3.l, 7
+; GFX11-NEXT: v_and_b16 v3.h, 0xff, v5.l
; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
; GFX11-NEXT: v_and_b16 v0.h, v0.h, 7
-; GFX11-NEXT: v_or_b16 v1.h, v2.h, v1.h
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-NEXT: v_and_b16 v1.h, v1.h, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b16 v0.h, v0.h, v2.h
+; GFX11-NEXT: v_lshrrev_b16 v2.h, v3.l, v3.h
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v1.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v1.l, v2.l, v1.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b16 v0.h, v0.h, v2.h
; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.l
-; GFX11-NEXT: v_lshrrev_b16 v0.h, v0.h, v1.h
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshrrev_b16 v0.l, v2.l, v0.l
-; GFX11-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX11-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v2i8:
@@ -1046,7 +1107,6 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshr_b32 s6, s1, 8
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_lshr_b32 s8, s1, 24
-; GFX8-NEXT: s_xor_b32 s12, s2, -1
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshr_b32 s3, s0, 8
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
@@ -1055,33 +1115,30 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_lshr_b32 s11, s2, 24
; GFX8-NEXT: s_lshl_b32 s0, s0, 1
-; GFX8-NEXT: s_and_b32 s12, s12, 7
+; GFX8-NEXT: s_andn2_b32 s12, 7, s2
; GFX8-NEXT: s_and_b32 s2, s2, 7
; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
; GFX8-NEXT: s_lshl_b32 s0, s0, s12
; GFX8-NEXT: s_lshr_b32 s1, s1, s2
-; GFX8-NEXT: s_xor_b32 s2, s9, -1
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_lshl_b32 s1, s3, 1
-; GFX8-NEXT: s_and_b32 s2, s2, 7
+; GFX8-NEXT: s_andn2_b32 s2, 7, s9
; GFX8-NEXT: s_and_b32 s3, s6, 0xff
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s2, s9, 7
; GFX8-NEXT: s_and_b32 s3, 0xffff, s3
; GFX8-NEXT: s_lshr_b32 s2, s3, s2
-; GFX8-NEXT: s_xor_b32 s3, s10, -1
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s2, s4, 1
-; GFX8-NEXT: s_and_b32 s3, s3, 7
+; GFX8-NEXT: s_andn2_b32 s3, 7, s10
; GFX8-NEXT: s_and_b32 s4, s7, 0xff
; GFX8-NEXT: s_lshl_b32 s2, s2, s3
; GFX8-NEXT: s_and_b32 s3, s10, 7
; GFX8-NEXT: s_and_b32 s4, 0xffff, s4
; GFX8-NEXT: s_lshr_b32 s3, s4, s3
-; GFX8-NEXT: s_xor_b32 s4, s11, -1
; GFX8-NEXT: s_or_b32 s2, s2, s3
; GFX8-NEXT: s_lshl_b32 s3, s5, 1
-; GFX8-NEXT: s_and_b32 s4, s4, 7
+; GFX8-NEXT: s_andn2_b32 s4, 7, s11
; GFX8-NEXT: s_and_b32 s1, s1, 0xff
; GFX8-NEXT: s_lshl_b32 s3, s3, s4
; GFX8-NEXT: s_and_b32 s4, s11, 7
@@ -1104,42 +1161,38 @@ define amdgpu_ps i32 @s_fshr_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg, i32 in
; GFX11-NEXT: s_lshr_b32 s7, s1, 16
; GFX11-NEXT: s_lshr_b32 s8, s1, 24
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshr_b32 s3, s0, 8
; GFX11-NEXT: s_lshr_b32 s9, s2, 8
; GFX11-NEXT: s_lshr_b32 s10, s2, 16
; GFX11-NEXT: s_lshr_b32 s11, s2, 24
-; GFX11-NEXT: s_xor_b32 s12, s2, -1
+; GFX11-NEXT: s_and_not1_b32 s12, 7, s2
; GFX11-NEXT: s_and_b32 s2, s2, 7
; GFX11-NEXT: s_and_b32 s1, 0xffff, s1
-; GFX11-NEXT: s_lshr_b32 s3, s0, 8
-; GFX11-NEXT: s_lshr_b32 s1, s1, s2
-; GFX11-NEXT: s_xor_b32 s2, s9, -1
; GFX11-NEXT: s_and_b32 s6, s6, 0xff
; GFX11-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-NEXT: s_lshr_b32 s5, s0, 24
; GFX11-NEXT: s_lshl_b32 s0, s0, 1
-; GFX11-NEXT: s_and_b32 s12, s12, 7
-; GFX11-NEXT: s_lshl_b32 s3, s3, 1
-; GFX11-NEXT: s_and_b32 s2, s2, 7
+; GFX11-NEXT: s_lshr_b32 s1, s1, s2
+; GFX11-NEXT: s_lshl_b32 s2, s3, 1
+; GFX11-NEXT: s_and_not1_b32 s3, 7, s9
; GFX11-NEXT: s_and_b32 s9, s9, 7
; GFX11-NEXT: s_and_b32 s6, 0xffff, s6
; GFX11-NEXT: s_lshl_b32 s0, s0, s12
-; GFX11-NEXT: s_lshl_b32 s2, s3, s2
+; GFX11-NEXT: s_lshl_b32 s2, s2, s3
; GFX11-NEXT: s_lshr_b32 s3, s6, s9
; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: s_or_b32 s1, s2, s3
-; GFX11-NEXT: s_xor_b32 s2, s10, -1
-; GFX11-NEXT: s_lshl_b32 s3, s4, 1
+; GFX11-NEXT: s_lshl_b32 s2, s4, 1
; GFX11-NEXT: s_and_b32 s4, s7, 0xff
-; GFX11-NEXT: s_and_b32 s2, s2, 7
+; GFX11-NEXT: s_and_not1_b32 s3, 7, s10
; GFX11-NEXT: s_and_b32 s6, s10, 7
; GFX11-NEXT: s_and_b32 s4, 0xffff, s4
-; GFX11-NEXT: s_lshl_b32 s2, s3, s2
+; GFX11-NEXT: s_lshl_b32 s2, s2, s3
; GFX11-NEXT: s_lshr_b32 s3, s4, s6
-; GFX11-NEXT: s_xor_b32 s4, s11, -1
-; GFX11-NEXT: s_lshl_b32 s5, s5, 1
-; GFX11-NEXT: s_and_b32 s4, s4, 7
+; GFX11-NEXT: s_lshl_b32 s4, s5, 1
+; GFX11-NEXT: s_and_not1_b32 s5, 7, s11
; GFX11-NEXT: s_and_b32 s6, s11, 7
-; GFX11-NEXT: s_lshl_b32 s4, s5, s4
+; GFX11-NEXT: s_lshl_b32 s4, s4, s5
; GFX11-NEXT: s_lshr_b32 s5, s8, s6
; GFX11-NEXT: s_or_b32 s2, s2, s3
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
@@ -1320,67 +1373,108 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-LABEL: v_fshr_v4i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-; GFX8-NEXT: v_bfe_u32 v4, v2, 8, 3
-; GFX8-NEXT: v_lshrrev_b16_sdwa v3, v4, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v0
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v5, 7, v2
-; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v4
-; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v4, 0xffffff00
-; GFX8-NEXT: v_and_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v5, 7
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT: v_and_b32_sdwa v6, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b16_sdwa v4, v6, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v6, 0xff
-; GFX8-NEXT: v_and_b32_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v6, 8
-; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v6, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_xor_b32_e32 v7, -1, v2
+; GFX8-NEXT: v_lshlrev_b16_e32 v6, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v7, 7, v7
+; GFX8-NEXT: v_lshlrev_b16_e32 v6, v7, v6
+; GFX8-NEXT: v_and_b32_e32 v7, 7, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 8, v2
+; GFX8-NEXT: v_lshrrev_b16_sdwa v7, v7, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX8-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX8-NEXT: v_xor_b32_e32 v7, -1, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v7, 7, v7
+; GFX8-NEXT: v_and_b32_e32 v5, 7, v5
+; GFX8-NEXT: v_lshlrev_b16_e32 v3, v7, v3
+; GFX8-NEXT: v_lshrrev_b16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_mov_b32_e32 v7, -1
+; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX8-NEXT: v_mov_b32_e32 v4, 1
+; GFX8-NEXT: v_xor_b32_sdwa v9, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b16_sdwa v5, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
+; GFX8-NEXT: v_lshlrev_b16_e32 v5, v9, v5
+; GFX8-NEXT: v_mov_b32_e32 v9, 7
+; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT: v_xor_b32_sdwa v4, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v8, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v4, 7, v4
+; GFX8-NEXT: v_and_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, v10, v8
+; GFX8-NEXT: v_lshlrev_b16_e32 v0, v4, v0
+; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v8
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX8-NEXT: v_and_b32_sdwa v1, v2, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b16_e32 v0, v1, v0
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v1, 8
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fshr_v4i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b16 v3.l, 8, v1.l
-; GFX11-NEXT: v_and_b16 v3.h, 0xff00, v0.l
-; GFX11-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 24, v1
+; GFX11-NEXT: v_xor_b16 v1.h, v7.l, -1
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v11, 24, v2
+; GFX11-NEXT: v_lshlrev_b16 v2.h, 1, v3.l
+; GFX11-NEXT: v_and_b16 v3.l, v7.l, 7
+; GFX11-NEXT: v_and_b16 v1.h, v1.h, 7
+; GFX11-NEXT: v_and_b16 v3.h, 0xff, v4.l
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v0
+; GFX11-NEXT: v_xor_b16 v4.l, v10.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v1.h, v1.h, v2.h
+; GFX11-NEXT: v_lshrrev_b16 v2.h, v3.l, v3.h
+; GFX11-NEXT: v_xor_b16 v3.h, v11.l, -1
+; GFX11-NEXT: v_xor_b16 v0.h, v2.l, -1
+; GFX11-NEXT: v_lshlrev_b16 v3.l, 1, v5.l
+; GFX11-NEXT: v_and_b16 v4.l, v4.l, 7
+; GFX11-NEXT: v_and_b16 v4.h, v10.l, 7
+; GFX11-NEXT: v_and_b16 v5.l, 0xff, v8.l
+; GFX11-NEXT: v_lshlrev_b16 v5.h, 1, v6.l
+; GFX11-NEXT: v_and_b16 v3.h, v3.h, 7
+; GFX11-NEXT: v_and_b16 v6.l, v11.l, 7
+; GFX11-NEXT: v_lshlrev_b16 v0.l, 1, v0.l
+; GFX11-NEXT: v_and_b16 v0.h, v0.h, 7
+; GFX11-NEXT: v_and_b16 v2.l, v2.l, 7
; GFX11-NEXT: v_and_b16 v1.l, 0xff, v1.l
-; GFX11-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
-; GFX11-NEXT: v_or_b16 v3.l, v3.h, v3.l
-; GFX11-NEXT: v_and_b16 v3.h, v4.l, 7
-; GFX11-NEXT: v_and_b16 v4.l, 0xff00, v0.h
-; GFX11-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX11-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.l
-; GFX11-NEXT: v_and_b16 v1.l, v2.l, 7
-; GFX11-NEXT: v_or_b16 v2.l, v4.l, v6.l
-; GFX11-NEXT: v_and_b16 v4.l, v5.l, 7
-; GFX11-NEXT: v_or_b16 v0.h, v0.h, v1.h
-; GFX11-NEXT: v_and_b16 v1.h, v2.h, 7
-; GFX11-NEXT: v_lshrrev_b16 v2.h, v3.h, v3.l
-; GFX11-NEXT: v_lshrrev_b16 v0.l, v1.l, v0.l
-; GFX11-NEXT: v_lshrrev_b16 v1.l, v4.l, v2.l
+; GFX11-NEXT: v_or_b16 v7.l, v1.h, v2.h
+; GFX11-NEXT: v_lshlrev_b16 v1.h, v4.l, v3.l
+; GFX11-NEXT: v_lshrrev_b16 v2.h, v4.h, v5.l
+; GFX11-NEXT: v_lshlrev_b16 v3.l, v3.h, v5.h
+; GFX11-NEXT: v_lshrrev_b16 v3.h, v6.l, v9.l
+; GFX11-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
+; GFX11-NEXT: v_lshrrev_b16 v0.h, v2.l, v1.l
+; GFX11-NEXT: v_and_b32_e32 v4, 0xff, v7
+; GFX11-NEXT: v_or_b16 v1.l, v1.h, v2.h
+; GFX11-NEXT: v_or_b16 v2.l, v3.l, v3.h
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshrrev_b16 v0.h, v1.h, v0.h
-; GFX11-NEXT: v_lshlrev_b16 v1.h, 8, v2.h
+; GFX11-NEXT: v_or_b16 v0.l, v0.l, v0.h
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX11-NEXT: v_or_b16 v0.l, v0.l, v1.h
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b16 v0.h, v0.h, v1.l
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_or_b32 v0, 0xff, v0, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 24, v2
+; GFX11-NEXT: v_or3_b32 v0, v0, v1, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX9-LABEL: v_fshr_v4i8:
; GFX9: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
index 25cfa8c7ca8d6..9657f2ec27268 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
@@ -258,15 +258,15 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; GFX81-NEXT: [[AND:%[0-9]+]]:_(i32) = G_AND [[BITCAST]], [[C1]]
; GFX81-NEXT: [[SHL:%[0-9]+]]:_(i32) = G_SHL [[LSHR]], [[C]](i32)
; GFX81-NEXT: [[OR:%[0-9]+]]:_(i32) = G_OR [[AND]], [[SHL]]
- ; GFX81-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](i32)
+ ; GFX81-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR]](i32)
; GFX81-NEXT: [[AND1:%[0-9]+]]:_(i32) = G_AND [[BITCAST1]], [[C1]]
; GFX81-NEXT: [[C2:%[0-9]+]]:_(i32) = G_CONSTANT i32 0
; GFX81-NEXT: [[SHL1:%[0-9]+]]:_(i32) = G_SHL [[C2]], [[C]](i32)
; GFX81-NEXT: [[OR1:%[0-9]+]]:_(i32) = G_OR [[AND1]], [[SHL1]]
- ; GFX81-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](i32)
+ ; GFX81-NEXT: [[BITCAST3:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR1]](i32)
; GFX81-NEXT: [[OR2:%[0-9]+]]:_(i32) = G_OR [[C2]], [[SHL1]]
- ; GFX81-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](i32)
- ; GFX81-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x i16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x s16>), [[BITCAST3]](<2 x s16>), [[BITCAST4]](<2 x s16>)
+ ; GFX81-NEXT: [[BITCAST4:%[0-9]+]]:_(<2 x i16>) = G_BITCAST [[OR2]](i32)
+ ; GFX81-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<6 x i16>) = G_CONCAT_VECTORS [[BITCAST2]](<2 x i16>), [[BITCAST3]](<2 x i16>), [[BITCAST4]](<2 x i16>)
; GFX81-NEXT: [[BITCAST5:%[0-9]+]]:_(<3 x i32>) = G_BITCAST [[CONCAT_VECTORS]](<6 x i16>)
; GFX81-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BITCAST5]](<3 x i32>), 7, [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<3 x f16>), align 8, addrspace 8)
; GFX81-NEXT: S_ENDPGM 0
@@ -359,11 +359,11 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t,
; UNPACKED-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[COPY10]](<2 x f16>), [[COPY11]](<2 x f16>)
; UNPACKED-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32)
; UNPACKED-NEXT: [[BITCAST:%[0-9]+]]:_(<4 x i16>) = G_BITCAST [[CONCAT_VECTORS]](<4 x f16>)
- ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(<2 x s16>), [[UV1:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[BITCAST]](<4 x i16>)
- ; UNPACKED-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x s16>)
+ ; UNPACKED-NEXT: [[UV:%[0-9]+]]:_(<2 x i16>), [[UV1:%[0-9]+]]:_(<2 x i16>) = G_UNMERGE_VALUES [[BITCAST]](<4 x i16>)
+ ; UNPACKED-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[UV]](<2 x i16>)
; UNPACKED-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 16
; UNPACKED-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C]](i32)
- ; UNPACKED-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x s16>)
+ ; UNPACKED-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[UV1]](<2 x i16>)
; UNPACKED-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32)
; UNPACKED-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[BITCAST1]](i32), [[LSHR]](i32), [[BITCAST2]](i32), [[LSHR1]](i32)
; UNPACKED-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR2]](<4 x i32>), 15, [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<4 x f16>), addrspace 8)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
index ec1bf960b56f2..1914250370219 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll
@@ -27,40 +27,46 @@ define i16 @v_powi_f16(i16 %l, i32 %r) {
; GFX8-LABEL: v_powi_f16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX8-NEXT: v_log_f32_e32 v0, v0
-; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v1, v0
-; GFX8-NEXT: v_exp_f32_e32 v0, v0
+; GFX8-NEXT: v_log_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX8-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX8-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX8-NEXT: v_mul_legacy_f32_e32 v0, v0, v1
; GFX8-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX8-NEXT: v_exp_f16_e32 v0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: v_powi_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX11-TRUE16-NEXT: v_log_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_log_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v1, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.h
; GFX11-TRUE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX11-TRUE16-NEXT: v_exp_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_powi_f16:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_log_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_log_f32_e32 v0, v0
-; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v1, v0
-; GFX11-FAKE16-NEXT: v_exp_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
; GFX11-FAKE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX11-FAKE16-NEXT: v_mul_dx9_zero_f32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX11-FAKE16-NEXT: v_exp_f16_e32 v0, v0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%l.cast = bitcast i16 %l to half
%res = call half @llvm.powi.f16.i32(half %l.cast, i32 %r)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
index a4b0645e0b76e..864037d713ad2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll
@@ -29,8 +29,8 @@ define i8 @v_lshr_i8(i8 %value, i8 %amount) {
; GFX10PLUS-LABEL: v_lshr_i8:
; GFX10PLUS: ; %bb.0:
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX10PLUS-NEXT: v_lshrrev_b16 v0, v1, v0
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = lshr i8 %value, %amount
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
index e8aecb318b07b..c226f7f9289ee 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX6 %s
+; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s
@@ -948,9 +948,24 @@ define <3 x i16> @v_orn2_v3i16(<3 x i16> %src0, <3 x i16> %src1) {
; GFX6-LABEL: v_orn2_v3i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v5
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX6-NEXT: v_xor_b32_e32 v2, -1, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_xor_b32_e32 v3, 0xfff5, v3
+; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX6-NEXT: v_bfi_b32 v0, v2, v0, -1
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
index bb924b1d5fec9..b2dc34d99bf76 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp.f64.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
define double @v_exp_f64(double %in) #0 {
; SI-SDAG-LABEL: v_exp_f64:
@@ -8429,220 +8429,23 @@ define double @v_exp_f64_0() #0 {
}
define double @v_exp_f64_from_fpext_f16(half %src) #0 {
-; SI-LABEL: v_exp_f64_from_fpext_f16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x652b82fe
-; SI-NEXT: s_mov_b32 s5, 0x3ff71547
-; SI-NEXT: s_brev_b32 s8, -2
-; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; SI-NEXT: v_mov_b32_e32 v5, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v4, 0
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: v_bfi_b32 v5, s8, v5, v3
-; SI-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
-; SI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
-; SI-NEXT: s_mov_b32 s4, 0xfefa39ef
-; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NEXT: s_mov_b32 s5, 0xbfe62e42
-; SI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; SI-NEXT: s_mov_b32 s4, 0x3b39803f
-; SI-NEXT: s_mov_b32 s5, 0xbc7abc9e
-; SI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; SI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; SI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; SI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; SI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: s_mov_b32 s4, 0x623fde64
-; SI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; SI-NEXT: s_mov_b32 s5, 0x3efa0199
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x14761f6e
-; SI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; SI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x11122322
-; SI-NEXT: s_mov_b32 s5, 0x3f811111
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x555502a1
-; SI-NEXT: s_mov_b32 s5, 0x3fa55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x55555511
-; SI-NEXT: s_mov_b32 s5, 0x3fc55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 11
-; SI-NEXT: s_mov_b32 s5, 0x3fe00000
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s4, 0
-; SI-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s5, 0x40900000
-; SI-NEXT: s_mov_b32 s6, 0
-; SI-NEXT: s_mov_b32 s7, 0xc090cc00
-; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; SI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; SI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; SI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; SI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_exp_f64_from_fpext_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x652b82fe
-; VI-NEXT: s_mov_b32 s5, 0x3ff71547
-; VI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; VI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; VI-NEXT: s_mov_b32 s6, 0
-; VI-NEXT: s_mov_b32 s7, 0xc090cc00
-; VI-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0xfefa39ef
-; VI-NEXT: s_mov_b32 s5, 0xbfe62e42
-; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; VI-NEXT: s_mov_b32 s4, 0x3b39803f
-; VI-NEXT: s_mov_b32 s5, 0xbc7abc9e
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; VI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; VI-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: s_mov_b32 s4, 0x623fde64
-; VI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; VI-NEXT: s_mov_b32 s5, 0x3efa0199
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x14761f6e
-; VI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; VI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x11122322
-; VI-NEXT: s_mov_b32 s5, 0x3f811111
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x555502a1
-; VI-NEXT: s_mov_b32 s5, 0x3fa55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x55555511
-; VI-NEXT: s_mov_b32 s5, 0x3fc55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 11
-; VI-NEXT: s_mov_b32 s5, 0x3fe00000
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0
-; VI-NEXT: s_mov_b32 s5, 0x40900000
-; VI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; VI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; VI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-LABEL: v_exp_f64_from_fpext_f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x652b82fe
-; GFX900-NEXT: s_mov_b32 s5, 0x3ff71547
-; GFX900-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; GFX900-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; GFX900-NEXT: s_mov_b32 s6, 0
-; GFX900-NEXT: s_mov_b32 s7, 0xc090cc00
-; GFX900-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0xfefa39ef
-; GFX900-NEXT: s_mov_b32 s5, 0xbfe62e42
-; GFX900-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; GFX900-NEXT: s_mov_b32 s4, 0x3b39803f
-; GFX900-NEXT: s_mov_b32 s5, 0xbc7abc9e
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; GFX900-NEXT: s_mov_b32 s5, 0x3e5ade15
-; GFX900-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: s_mov_b32 s4, 0x623fde64
-; GFX900-NEXT: s_mov_b32 s5, 0x3ec71dee
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3efa0199
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x14761f6e
-; GFX900-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x1852b7b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3f56c16c
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x11122322
-; GFX900-NEXT: s_mov_b32 s5, 0x3f811111
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x555502a1
-; GFX900-NEXT: s_mov_b32 s5, 0x3fa55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x55555511
-; GFX900-NEXT: s_mov_b32 s5, 0x3fc55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 11
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe00000
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0
-; GFX900-NEXT: s_mov_b32 s5, 0x40900000
-; GFX900-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX900-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
- %fpext = fpext half %src to double
- %result = call double @llvm.exp.f64(double %fpext)
- ret double %result
-}
-
-define double @v_exp_f64_from_fpext_f32(float %src) #0 {
-; SI-SDAG-LABEL: v_exp_f64_from_fpext_f32:
+; SI-SDAG-LABEL: v_exp_f64_from_fpext_f16:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
-; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x43300000
-; SI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; SI-SDAG-NEXT: s_brev_b32 s4, -2
-; SI-SDAG-NEXT: v_bfi_b32 v5, s4, v4, v3
+; SI-SDAG-NEXT: s_brev_b32 s8, -2
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, 0x43300000
; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0
-; SI-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-SDAG-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; SI-SDAG-NEXT: v_bfi_b32 v5, s8, v5, v3
+; SI-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -8697,88 +8500,90 @@ define double @v_exp_f64_from_fpext_f32(float %src) #0 {
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; SI-GISEL-LABEL: v_exp_f64_from_fpext_f32:
+; SI-GISEL-LABEL: v_exp_f64_from_fpext_f16:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x652b82fe
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3ff71547
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; SI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-GISEL-NEXT: v_mov_b32_e32 v6, -1
-; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v3
-; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
-; SI-GISEL-NEXT: v_add_f64 v[8:9], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x432fffff
-; SI-GISEL-NEXT: v_add_f64 v[4:5], v[8:9], -v[4:5]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[6:7]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xfefa39ef
-; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe62e42
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[10:11], v[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3b39803f
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3c7abc9e
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[6:7]
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
+; SI-GISEL-NEXT: v_mul_f64 v[0:1], v[2:3], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[12:13], v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[12:13], -v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x3b39803f
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[8:9], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3c7abc9e
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[10:11], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[14:15], v[6:7]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 11
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[0:1]
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v10
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
-; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SDAG-LABEL: v_exp_f64_from_fpext_f32:
+; VI-SDAG-LABEL: v_exp_f64_from_fpext_f16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; VI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
-; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
; VI-SDAG-NEXT: s_mov_b32 s6, 0
; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
@@ -8826,17 +8631,18 @@ define double @v_exp_f64_from_fpext_f32(float %src) #0 {
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-GISEL-LABEL: v_exp_f64_from_fpext_f32:
+; VI-GISEL-LABEL: v_exp_f64_from_fpext_f16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xfefa39ef
-; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fe62e42
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
@@ -8886,19 +8692,20 @@ define double @v_exp_f64_from_fpext_f32(float %src) #0 {
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-SDAG-LABEL: v_exp_f64_from_fpext_f32:
+; GFX900-SDAG-LABEL: v_exp_f64_from_fpext_f16:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
-; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
@@ -8946,17 +8753,18 @@ define double @v_exp_f64_from_fpext_f32(float %src) #0 {
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-GISEL-LABEL: v_exp_f64_from_fpext_f32:
+; GFX900-GISEL-LABEL: v_exp_f64_from_fpext_f16:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xfefa39ef
-; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fe62e42
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
@@ -9005,210 +8813,792 @@ define double @v_exp_f64_from_fpext_f32(float %src) #0 {
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
- %fpext = fpext float %src to double
+ %fpext = fpext half %src to double
%result = call double @llvm.exp.f64(double %fpext)
ret double %result
}
-define double @v_exp_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
-; SI-LABEL: v_exp_f64_from_fpext_math_f16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x652b82fe
-; SI-NEXT: s_mov_b32 s5, 0x3ff71547
-; SI-NEXT: s_brev_b32 s10, -2
-; SI-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v0
-; SI-NEXT: v_mov_b32_e32 v0, 0
-; SI-NEXT: s_mov_b32 s8, 0xfefa39ef
-; SI-NEXT: s_mov_b32 s9, 0xbfe62e42
-; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v1
-; SI-NEXT: v_mul_f64 v[4:5], v[2:3], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x3b39803f
-; SI-NEXT: v_bfi_b32 v1, s10, v6, v5
-; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[0:1]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
-; SI-NEXT: v_add_f64 v[0:1], v[6:7], -v[0:1]
-; SI-NEXT: s_mov_b32 s5, 0xbc7abc9e
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; SI-NEXT: v_fma_f64 v[4:5], v[0:1], s[8:9], v[2:3]
-; SI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; SI-NEXT: v_fma_f64 v[4:5], v[0:1], s[4:5], v[4:5]
-; SI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; SI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; SI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: s_mov_b32 s4, 0x623fde64
-; SI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; SI-NEXT: s_mov_b32 s5, 0x3efa0199
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x14761f6e
-; SI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; SI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x11122322
-; SI-NEXT: s_mov_b32 s5, 0x3f811111
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x555502a1
-; SI-NEXT: s_mov_b32 s5, 0x3fa55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x55555511
-; SI-NEXT: s_mov_b32 s5, 0x3fc55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 11
-; SI-NEXT: s_mov_b32 s5, 0x3fe00000
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s4, 0
-; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s5, 0x40900000
-; SI-NEXT: s_mov_b32 s6, 0
-; SI-NEXT: s_mov_b32 s7, 0xc090cc00
-; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; SI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[2:3]
-; SI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[2:3]
-; SI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; SI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
+define double @v_exp_f64_from_fpext_f32(float %src) #0 {
+; SI-SDAG-LABEL: v_exp_f64_from_fpext_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x43300000
+; SI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; SI-SDAG-NEXT: s_brev_b32 s4, -2
+; SI-SDAG-NEXT: v_bfi_b32 v5, s4, v4, v3
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; SI-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SI-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; SI-SDAG-NEXT: s_mov_b32 s5, 0xbc7abc9e
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 11
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0
+; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; SI-SDAG-NEXT: s_mov_b32 s6, 0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; SI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: v_exp_f64_from_fpext_math_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x652b82fe
-; VI-NEXT: s_mov_b32 s5, 0x3ff71547
-; VI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; VI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; VI-NEXT: s_mov_b32 s6, 0
-; VI-NEXT: s_mov_b32 s7, 0xc090cc00
-; VI-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0xfefa39ef
-; VI-NEXT: s_mov_b32 s5, 0xbfe62e42
-; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; VI-NEXT: s_mov_b32 s4, 0x3b39803f
-; VI-NEXT: s_mov_b32 s5, 0xbc7abc9e
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; VI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; VI-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: s_mov_b32 s4, 0x623fde64
-; VI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; VI-NEXT: s_mov_b32 s5, 0x3efa0199
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x14761f6e
-; VI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; VI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x11122322
-; VI-NEXT: s_mov_b32 s5, 0x3f811111
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x555502a1
-; VI-NEXT: s_mov_b32 s5, 0x3fa55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x55555511
-; VI-NEXT: s_mov_b32 s5, 0x3fc55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 11
-; VI-NEXT: s_mov_b32 s5, 0x3fe00000
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0
-; VI-NEXT: s_mov_b32 s5, 0x40900000
-; VI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; VI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; VI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_exp_f64_from_fpext_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, -1
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v3
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[2:3], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x432fffff
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[8:9], -v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xfefa39ef
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe62e42
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[10:11], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x3b39803f
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3c7abc9e
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp_f64_from_fpext_math_f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x652b82fe
-; GFX900-NEXT: s_mov_b32 s5, 0x3ff71547
-; GFX900-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; GFX900-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; GFX900-NEXT: s_mov_b32 s6, 0
-; GFX900-NEXT: s_mov_b32 s7, 0xc090cc00
-; GFX900-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0xfefa39ef
-; GFX900-NEXT: s_mov_b32 s5, 0xbfe62e42
-; GFX900-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; GFX900-NEXT: s_mov_b32 s4, 0x3b39803f
-; GFX900-NEXT: s_mov_b32 s5, 0xbc7abc9e
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; GFX900-NEXT: s_mov_b32 s5, 0x3e5ade15
-; GFX900-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: s_mov_b32 s4, 0x623fde64
-; GFX900-NEXT: s_mov_b32 s5, 0x3ec71dee
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3efa0199
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x14761f6e
-; GFX900-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x1852b7b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3f56c16c
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x11122322
-; GFX900-NEXT: s_mov_b32 s5, 0x3f811111
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x555502a1
-; GFX900-NEXT: s_mov_b32 s5, 0x3fa55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x55555511
-; GFX900-NEXT: s_mov_b32 s5, 0x3fc55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 11
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe00000
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0
-; GFX900-NEXT: s_mov_b32 s5, 0x40900000
-; GFX900-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX900-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; VI-SDAG-LABEL: v_exp_f64_from_fpext_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; VI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; VI-SDAG-NEXT: s_mov_b32 s6, 0
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbc7abc9e
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 11
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f64_from_fpext_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xfefa39ef
+; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fe62e42
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_exp_f64_from_fpext_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbc7abc9e
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 11
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX900-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp_f64_from_fpext_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xfefa39ef
+; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fe62e42
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %fpext = fpext float %src to double
+ %result = call double @llvm.exp.f64(double %fpext)
+ ret double %result
+}
+
+define double @v_exp_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
+; SI-SDAG-LABEL: v_exp_f64_from_fpext_math_f16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
+; SI-SDAG-NEXT: s_brev_b32 s10, -2
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x43300000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; SI-SDAG-NEXT: s_mov_b32 s8, 0xfefa39ef
+; SI-SDAG-NEXT: s_mov_b32 s9, 0xbfe62e42
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[2:3], v1
+; SI-SDAG-NEXT: v_mul_f64 v[4:5], v[2:3], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; SI-SDAG-NEXT: v_bfi_b32 v1, s10, v6, v5
+; SI-SDAG-NEXT: v_add_f64 v[6:7], v[4:5], v[0:1]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
+; SI-SDAG-NEXT: v_add_f64 v[0:1], v[6:7], -v[0:1]
+; SI-SDAG-NEXT: s_mov_b32 s5, 0xbc7abc9e
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[8:9], v[2:3]
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[4:5], v[4:5]
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 11
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0
+; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; SI-SDAG-NEXT: s_mov_b32 s6, 0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; SI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[2:3]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[2:3]
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
+; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_exp_f64_from_fpext_math_f16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, -1
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x432fffff
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3ff71547
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x652b82fe
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x3b39803f
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3c7abc9e
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0x3e5ade15
+; SI-GISEL-NEXT: v_mul_f64 v[0:1], v[2:3], v[0:1]
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[12:13], v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[12:13], -v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[8:9], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[10:11], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[14:15], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[0:1]
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v10
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-SDAG-LABEL: v_exp_f64_from_fpext_math_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; VI-SDAG-NEXT: s_mov_b32 s6, 0
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbc7abc9e
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 11
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp_f64_from_fpext_math_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0xfefa39ef
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fe62e42
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_exp_f64_from_fpext_math_f16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x652b82fe
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ff71547
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfe62e42
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbc7abc9e
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 11
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX900-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp_f64_from_fpext_math_f16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x652b82fe
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x3ff71547
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0xfefa39ef
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fe62e42
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to double
%result = call double @llvm.exp.f64(double %fpext)
@@ -9934,3 +10324,7 @@ define double @v_exp_f64_contract_nnan_ninf(double %in) #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX900: {{.*}}
+; SI: {{.*}}
+; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
index b0a6710b83e67..10fe4f48aba48 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp10.f64.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
define double @v_exp10_f64(double %in) #0 {
; SI-SDAG-LABEL: v_exp10_f64:
@@ -9185,238 +9185,23 @@ define double @v_exp10_f64_0() #0 {
}
define double @v_exp10_f64_from_fpext_f16(half %src) #0 {
-; SI-LABEL: v_exp10_f64_from_fpext_f16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x979a371
-; SI-NEXT: s_mov_b32 s5, 0x400a934f
-; SI-NEXT: s_brev_b32 s8, -2
-; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; SI-NEXT: v_mov_b32_e32 v5, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v4, 0
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: v_bfi_b32 v5, s8, v5, v3
-; SI-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
-; SI-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x509f79ff
-; SI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; SI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-NEXT: s_mov_b32 s5, 0xbfd34413
-; SI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; SI-NEXT: s_mov_b32 s4, 0xa994fd21
-; SI-NEXT: s_mov_b32 s5, 0x3c49dc1d
-; SI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x494ea3e9
-; SI-NEXT: s_mov_b32 s5, 0xbcaf48ad
-; SI-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0xbbb55516
-; SI-NEXT: s_mov_b32 s5, 0x40026bb1
-; SI-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; SI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; SI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; SI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: s_mov_b32 s4, 0x623fde64
-; SI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; SI-NEXT: s_mov_b32 s5, 0x3efa0199
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x14761f6e
-; SI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; SI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x11122322
-; SI-NEXT: s_mov_b32 s5, 0x3f811111
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x555502a1
-; SI-NEXT: s_mov_b32 s5, 0x3fa55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x55555511
-; SI-NEXT: s_mov_b32 s5, 0x3fc55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 11
-; SI-NEXT: s_mov_b32 s5, 0x3fe00000
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s4, 0
-; SI-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s5, 0x40900000
-; SI-NEXT: s_mov_b32 s6, 0
-; SI-NEXT: s_mov_b32 s7, 0xc090cc00
-; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; SI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; SI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; SI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; SI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_exp10_f64_from_fpext_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x979a371
-; VI-NEXT: s_mov_b32 s5, 0x400a934f
-; VI-NEXT: s_mov_b32 s6, 0
-; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; VI-NEXT: s_mov_b32 s7, 0xc090cc00
-; VI-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x509f79ff
-; VI-NEXT: s_mov_b32 s5, 0xbfd34413
-; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; VI-NEXT: s_mov_b32 s4, 0xa994fd21
-; VI-NEXT: s_mov_b32 s5, 0x3c49dc1d
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x494ea3e9
-; VI-NEXT: s_mov_b32 s5, 0xbcaf48ad
-; VI-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0xbbb55516
-; VI-NEXT: s_mov_b32 s5, 0x40026bb1
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; VI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; VI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; VI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: s_mov_b32 s4, 0x623fde64
-; VI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; VI-NEXT: s_mov_b32 s5, 0x3efa0199
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x14761f6e
-; VI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; VI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x11122322
-; VI-NEXT: s_mov_b32 s5, 0x3f811111
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x555502a1
-; VI-NEXT: s_mov_b32 s5, 0x3fa55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x55555511
-; VI-NEXT: s_mov_b32 s5, 0x3fc55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 11
-; VI-NEXT: s_mov_b32 s5, 0x3fe00000
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0
-; VI-NEXT: s_mov_b32 s5, 0x40900000
-; VI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; VI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; VI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-LABEL: v_exp10_f64_from_fpext_f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x979a371
-; GFX900-NEXT: s_mov_b32 s5, 0x400a934f
-; GFX900-NEXT: s_mov_b32 s6, 0
-; GFX900-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX900-NEXT: s_mov_b32 s7, 0xc090cc00
-; GFX900-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x509f79ff
-; GFX900-NEXT: s_mov_b32 s5, 0xbfd34413
-; GFX900-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; GFX900-NEXT: s_mov_b32 s4, 0xa994fd21
-; GFX900-NEXT: s_mov_b32 s5, 0x3c49dc1d
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x494ea3e9
-; GFX900-NEXT: s_mov_b32 s5, 0xbcaf48ad
-; GFX900-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0xbbb55516
-; GFX900-NEXT: s_mov_b32 s5, 0x40026bb1
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; GFX900-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; GFX900-NEXT: s_mov_b32 s5, 0x3e5ade15
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: s_mov_b32 s4, 0x623fde64
-; GFX900-NEXT: s_mov_b32 s5, 0x3ec71dee
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3efa0199
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x14761f6e
-; GFX900-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x1852b7b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3f56c16c
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x11122322
-; GFX900-NEXT: s_mov_b32 s5, 0x3f811111
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x555502a1
-; GFX900-NEXT: s_mov_b32 s5, 0x3fa55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x55555511
-; GFX900-NEXT: s_mov_b32 s5, 0x3fc55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 11
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe00000
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0
-; GFX900-NEXT: s_mov_b32 s5, 0x40900000
-; GFX900-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX900-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
- %fpext = fpext half %src to double
- %result = call double @llvm.exp10.f64(double %fpext)
- ret double %result
-}
-
-define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
-; SI-SDAG-LABEL: v_exp10_f64_from_fpext_f32:
+; SI-SDAG-LABEL: v_exp10_f64_from_fpext_f16:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x979a371
; SI-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
-; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x43300000
-; SI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; SI-SDAG-NEXT: s_brev_b32 s4, -2
-; SI-SDAG-NEXT: v_bfi_b32 v5, s4, v4, v3
+; SI-SDAG-NEXT: s_brev_b32 s8, -2
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v5, 0x43300000
; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0
-; SI-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-SDAG-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; SI-SDAG-NEXT: v_bfi_b32 v5, s8, v5, v3
+; SI-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
@@ -9477,92 +9262,94 @@ define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; SI-GISEL-LABEL: v_exp10_f64_from_fpext_f32:
+; SI-GISEL-LABEL: v_exp10_f64_from_fpext_f16:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
-; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x979a371
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x400a934f
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; SI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
; SI-GISEL-NEXT: v_mov_b32_e32 v6, -1
-; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v3
-; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
-; SI-GISEL-NEXT: v_add_f64 v[8:9], v[2:3], v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x432fffff
-; SI-GISEL-NEXT: v_add_f64 v[4:5], v[8:9], -v[4:5]
-; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[6:7]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x509f79ff
-; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fd34413
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[10:11], v[0:1]
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xa994fd21
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xbc49dc1d
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[6:7]
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
-; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x509f79ff
+; SI-GISEL-NEXT: v_mul_f64 v[0:1], v[2:3], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fd34413
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[12:13], v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[12:13], -v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xa994fd21
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[8:9], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0xbc49dc1d
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[10:11], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x494ea3e9
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0xbcaf48ad
+; SI-GISEL-NEXT: v_mul_f64 v[10:11], v[4:5], v[14:15]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0xbbb55516
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x40026bb1
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e5ade15
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 11
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[0:1]
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v10
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
-; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
-; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
-; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
-; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
-; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SDAG-LABEL: v_exp10_f64_from_fpext_f32:
+; VI-SDAG-LABEL: v_exp10_f64_from_fpext_f16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x979a371
; VI-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
; VI-SDAG-NEXT: s_mov_b32 s6, 0
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
; VI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
; VI-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
-; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
; VI-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
@@ -9618,17 +9405,18 @@ define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-GISEL-LABEL: v_exp10_f64_from_fpext_f32:
+; VI-GISEL-LABEL: v_exp10_f64_from_fpext_f16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x509f79ff
-; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fd34413
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0xa994fd21
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbc49dc1d
+; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
@@ -9684,17 +9472,18 @@ define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-SDAG-LABEL: v_exp10_f64_from_fpext_f32:
+; GFX900-SDAG-LABEL: v_exp10_f64_from_fpext_f16:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x979a371
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
-; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
@@ -9750,17 +9539,18 @@ define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-GISEL-LABEL: v_exp10_f64_from_fpext_f32:
+; GFX900-GISEL-LABEL: v_exp10_f64_from_fpext_f16:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x509f79ff
-; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fd34413
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0xa994fd21
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbc49dc1d
+; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
@@ -9815,228 +9605,864 @@ define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
- %fpext = fpext float %src to double
+ %fpext = fpext half %src to double
%result = call double @llvm.exp10.f64(double %fpext)
ret double %result
}
-define double @v_exp10_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
-; SI-LABEL: v_exp10_f64_from_fpext_math_f16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: s_mov_b32 s4, 0x979a371
-; SI-NEXT: s_mov_b32 s5, 0x400a934f
-; SI-NEXT: s_brev_b32 s10, -2
-; SI-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: v_mov_b32_e32 v6, 0x43300000
-; SI-NEXT: s_mov_b32 s6, -1
-; SI-NEXT: s_mov_b32 s7, 0x432fffff
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v0
-; SI-NEXT: v_mov_b32_e32 v0, 0
-; SI-NEXT: s_mov_b32 s8, 0x509f79ff
-; SI-NEXT: s_mov_b32 s9, 0xbfd34413
-; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v1
-; SI-NEXT: v_mul_f64 v[4:5], v[2:3], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0xa994fd21
-; SI-NEXT: v_bfi_b32 v1, s10, v6, v5
-; SI-NEXT: v_add_f64 v[6:7], v[4:5], v[0:1]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
-; SI-NEXT: v_add_f64 v[0:1], v[6:7], -v[0:1]
-; SI-NEXT: s_mov_b32 s5, 0x3c49dc1d
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
-; SI-NEXT: v_fma_f64 v[4:5], v[0:1], s[8:9], v[2:3]
-; SI-NEXT: s_mov_b32 s6, 0x494ea3e9
-; SI-NEXT: v_fma_f64 v[4:5], v[0:1], s[4:5], v[4:5]
-; SI-NEXT: s_mov_b32 s7, 0xbcaf48ad
-; SI-NEXT: v_mul_f64 v[6:7], v[4:5], s[6:7]
-; SI-NEXT: s_mov_b32 s4, 0xbbb55516
-; SI-NEXT: s_mov_b32 s5, 0x40026bb1
-; SI-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; SI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; SI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; SI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: s_mov_b32 s4, 0x623fde64
-; SI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; SI-NEXT: s_mov_b32 s5, 0x3efa0199
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x14761f6e
-; SI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; SI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x11122322
-; SI-NEXT: s_mov_b32 s5, 0x3f811111
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x555502a1
-; SI-NEXT: s_mov_b32 s5, 0x3fa55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x55555511
-; SI-NEXT: s_mov_b32 s5, 0x3fc55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 11
-; SI-NEXT: s_mov_b32 s5, 0x3fe00000
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s4, 0
-; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s5, 0x40900000
-; SI-NEXT: s_mov_b32 s6, 0
-; SI-NEXT: s_mov_b32 s7, 0xc090cc00
-; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; SI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[2:3]
-; SI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[2:3]
-; SI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; SI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_exp10_f64_from_fpext_math_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x979a371
-; VI-NEXT: s_mov_b32 s5, 0x400a934f
-; VI-NEXT: s_mov_b32 s6, 0
-; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; VI-NEXT: s_mov_b32 s7, 0xc090cc00
-; VI-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x509f79ff
-; VI-NEXT: s_mov_b32 s5, 0xbfd34413
-; VI-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; VI-NEXT: s_mov_b32 s4, 0xa994fd21
-; VI-NEXT: s_mov_b32 s5, 0x3c49dc1d
-; VI-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x494ea3e9
-; VI-NEXT: s_mov_b32 s5, 0xbcaf48ad
-; VI-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0xbbb55516
-; VI-NEXT: s_mov_b32 s5, 0x40026bb1
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; VI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; VI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; VI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: s_mov_b32 s4, 0x623fde64
-; VI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; VI-NEXT: s_mov_b32 s5, 0x3efa0199
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x14761f6e
-; VI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; VI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x11122322
-; VI-NEXT: s_mov_b32 s5, 0x3f811111
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x555502a1
-; VI-NEXT: s_mov_b32 s5, 0x3fa55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x55555511
-; VI-NEXT: s_mov_b32 s5, 0x3fc55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 11
-; VI-NEXT: s_mov_b32 s5, 0x3fe00000
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0
-; VI-NEXT: s_mov_b32 s5, 0x40900000
-; VI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; VI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; VI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+define double @v_exp10_f64_from_fpext_f32(float %src) #0 {
+; SI-SDAG-LABEL: v_exp10_f64_from_fpext_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x979a371
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x43300000
+; SI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; SI-SDAG-NEXT: s_brev_b32 s4, -2
+; SI-SDAG-NEXT: v_bfi_b32 v5, s4, v4, v3
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0
+; SI-SDAG-NEXT: v_add_f64 v[6:7], v[2:3], v[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[6:7], -v[4:5]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SI-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3c49dc1d
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x494ea3e9
+; SI-SDAG-NEXT: s_mov_b32 s5, 0xbcaf48ad
+; SI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xbbb55516
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 11
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0
+; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; SI-SDAG-NEXT: s_mov_b32 s6, 0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; SI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp10_f64_from_fpext_math_f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x979a371
-; GFX900-NEXT: s_mov_b32 s5, 0x400a934f
-; GFX900-NEXT: s_mov_b32 s6, 0
-; GFX900-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX900-NEXT: s_mov_b32 s7, 0xc090cc00
-; GFX900-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x509f79ff
-; GFX900-NEXT: s_mov_b32 s5, 0xbfd34413
-; GFX900-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
-; GFX900-NEXT: s_mov_b32 s4, 0xa994fd21
-; GFX900-NEXT: s_mov_b32 s5, 0x3c49dc1d
-; GFX900-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x494ea3e9
-; GFX900-NEXT: s_mov_b32 s5, 0xbcaf48ad
-; GFX900-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0xbbb55516
-; GFX900-NEXT: s_mov_b32 s5, 0x40026bb1
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; GFX900-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; GFX900-NEXT: s_mov_b32 s5, 0x3e5ade15
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: s_mov_b32 s4, 0x623fde64
-; GFX900-NEXT: s_mov_b32 s5, 0x3ec71dee
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3efa0199
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x14761f6e
-; GFX900-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x1852b7b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3f56c16c
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x11122322
-; GFX900-NEXT: s_mov_b32 s5, 0x3f811111
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x555502a1
-; GFX900-NEXT: s_mov_b32 s5, 0x3fa55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x55555511
-; GFX900-NEXT: s_mov_b32 s5, 0x3fc55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 11
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe00000
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0
-; GFX900-NEXT: s_mov_b32 s5, 0x40900000
-; GFX900-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX900-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_exp10_f64_from_fpext_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
+; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, -1
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v3
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[2:3], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x432fffff
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[8:9], -v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x509f79ff
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fd34413
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[10:11], v[0:1]
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0xa994fd21
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xbc49dc1d
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-SDAG-LABEL: v_exp10_f64_from_fpext_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x979a371
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
+; VI-SDAG-NEXT: s_mov_b32 s6, 0
+; VI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3c49dc1d
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x494ea3e9
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbcaf48ad
+; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xbbb55516
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 11
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f64_from_fpext_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x509f79ff
+; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fd34413
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0xa994fd21
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbc49dc1d
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_exp10_f64_from_fpext_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x979a371
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
+; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3c49dc1d
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x494ea3e9
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbcaf48ad
+; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xbbb55516
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 11
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX900-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp10_f64_from_fpext_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x509f79ff
+; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fd34413
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0xa994fd21
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbc49dc1d
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %fpext = fpext float %src to double
+ %result = call double @llvm.exp10.f64(double %fpext)
+ ret double %result
+}
+
+define double @v_exp10_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
+; SI-SDAG-LABEL: v_exp10_f64_from_fpext_math_f16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x979a371
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
+; SI-SDAG-NEXT: s_brev_b32 s10, -2
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0x43300000
+; SI-SDAG-NEXT: s_mov_b32 s6, -1
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x432fffff
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; SI-SDAG-NEXT: s_mov_b32 s8, 0x509f79ff
+; SI-SDAG-NEXT: s_mov_b32 s9, 0xbfd34413
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[2:3], v1
+; SI-SDAG-NEXT: v_mul_f64 v[4:5], v[2:3], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
+; SI-SDAG-NEXT: v_bfi_b32 v1, s10, v6, v5
+; SI-SDAG-NEXT: v_add_f64 v[6:7], v[4:5], v[0:1]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[4:5]|, s[6:7]
+; SI-SDAG-NEXT: v_add_f64 v[0:1], v[6:7], -v[0:1]
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3c49dc1d
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[8:9], v[2:3]
+; SI-SDAG-NEXT: s_mov_b32 s6, 0x494ea3e9
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[0:1], s[4:5], v[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xbcaf48ad
+; SI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xbbb55516
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 11
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0
+; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; SI-SDAG-NEXT: s_mov_b32 s6, 0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; SI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[2:3]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[2:3]
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
+; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_exp10_f64_from_fpext_math_f16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, -1
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x432fffff
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x400a934f
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x509f79ff
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fd34413
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x979a371
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xa994fd21
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0xbc49dc1d
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[2:3], v2
+; SI-GISEL-NEXT: v_mov_b32_e32 v14, 0x494ea3e9
+; SI-GISEL-NEXT: v_mov_b32_e32 v15, 0xbcaf48ad
+; SI-GISEL-NEXT: v_mul_f64 v[0:1], v[2:3], v[0:1]
+; SI-GISEL-NEXT: v_and_b32_e32 v5, 0x80000000, v1
+; SI-GISEL-NEXT: v_or_b32_e32 v5, 0x43300000, v5
+; SI-GISEL-NEXT: v_add_f64 v[12:13], v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[6:7]
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[12:13], -v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0xbbb55516
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[8:9], v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x40026bb1
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], -v[0:1], v[10:11], v[4:5]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mul_f64 v[10:11], v[4:5], v[14:15]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e5ade15
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[0:1]
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; SI-GISEL-NEXT: v_fma_f64 v[0:1], v[4:5], v[0:1], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v10
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[2:3], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[2:3], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-SDAG-LABEL: v_exp10_f64_from_fpext_math_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x979a371
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
+; VI-SDAG-NEXT: s_mov_b32 s6, 0
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3c49dc1d
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x494ea3e9
+; VI-SDAG-NEXT: s_mov_b32 s5, 0xbcaf48ad
+; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xbbb55516
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 11
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp10_f64_from_fpext_math_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
+; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x509f79ff
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fd34413
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0xa994fd21
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbc49dc1d
+; VI-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_exp10_f64_from_fpext_math_f16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x979a371
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x400a934f
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_mul_f64 v[2:3], v[0:1], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x509f79ff
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbfd34413
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xa994fd21
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3c49dc1d
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[2:3], s[4:5], v[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x494ea3e9
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0xbcaf48ad
+; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xbbb55516
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40026bb1
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 11
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX900-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp10_f64_from_fpext_math_f16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x979a371
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x400a934f
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x509f79ff
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x3fd34413
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0xa994fd21
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbc49dc1d
+; GFX900-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xbbb55516
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x40026bb1
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[2:3]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[4:5], v[0:1]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], -v[2:3], v[6:7], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x494ea3e9
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xbcaf48ad
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to double
%result = call double @llvm.exp10.f64(double %fpext)
@@ -10834,3 +11260,7 @@ define double @v_exp10_f64_contract_nnan_ninf(double %in) #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX900: {{.*}}
+; SI: {{.*}}
+; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
index 799cb8eedf94a..2dc1ff2765503 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.f64.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
define double @v_exp2_f64(double %in) #0 {
; SI-SDAG-LABEL: v_exp2_f64:
@@ -8182,295 +8182,105 @@ define double @v_exp2_f64_0() #0 {
}
define double @v_exp2_f64_from_fpext_f16(half %src) #0 {
-; SI-LABEL: v_exp2_f64_from_fpext_f16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v3, v0
-; SI-NEXT: s_brev_b32 s6, -2
-; SI-NEXT: v_mov_b32_e32 v4, 0x43300000
-; SI-NEXT: v_mov_b32_e32 v2, 0
-; SI-NEXT: v_cvt_f64_f32_e32 v[0:1], v3
-; SI-NEXT: v_bfi_b32 v3, s6, v4, v3
-; SI-NEXT: s_mov_b32 s4, -1
-; SI-NEXT: s_mov_b32 s5, 0x432fffff
-; SI-NEXT: v_add_f64 v[4:5], v[0:1], v[2:3]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
-; SI-NEXT: v_add_f64 v[2:3], v[4:5], -v[2:3]
-; SI-NEXT: s_mov_b32 s4, 0x3b39803f
-; SI-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; SI-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
-; SI-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
-; SI-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; SI-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0xfefa39ef
-; SI-NEXT: s_mov_b32 s5, 0x3fe62e42
-; SI-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; SI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; SI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; SI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: s_mov_b32 s4, 0x623fde64
-; SI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; SI-NEXT: s_mov_b32 s5, 0x3efa0199
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x14761f6e
-; SI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; SI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x11122322
-; SI-NEXT: s_mov_b32 s5, 0x3f811111
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x555502a1
-; SI-NEXT: s_mov_b32 s5, 0x3fa55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x55555511
-; SI-NEXT: s_mov_b32 s5, 0x3fc55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 11
-; SI-NEXT: s_mov_b32 s5, 0x3fe00000
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s4, 0
-; SI-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s5, 0x40900000
-; SI-NEXT: s_mov_b32 s6, 0
-; SI-NEXT: s_mov_b32 s7, 0xc090cc00
-; SI-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; SI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; SI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; SI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; SI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_exp2_f64_from_fpext_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x3b39803f
-; VI-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; VI-NEXT: s_mov_b32 s6, 0
-; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; VI-NEXT: s_mov_b32 s7, 0xc090cc00
-; VI-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
-; VI-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
-; VI-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0xfefa39ef
-; VI-NEXT: s_mov_b32 s5, 0x3fe62e42
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; VI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; VI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; VI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: s_mov_b32 s4, 0x623fde64
-; VI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; VI-NEXT: s_mov_b32 s5, 0x3efa0199
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x14761f6e
-; VI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; VI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x11122322
-; VI-NEXT: s_mov_b32 s5, 0x3f811111
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x555502a1
-; VI-NEXT: s_mov_b32 s5, 0x3fa55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x55555511
-; VI-NEXT: s_mov_b32 s5, 0x3fc55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 11
-; VI-NEXT: s_mov_b32 s5, 0x3fe00000
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0
-; VI-NEXT: s_mov_b32 s5, 0x40900000
-; VI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; VI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; VI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-LABEL: v_exp2_f64_from_fpext_f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3b39803f
-; GFX900-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; GFX900-NEXT: s_mov_b32 s6, 0
-; GFX900-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX900-NEXT: s_mov_b32 s7, 0xc090cc00
-; GFX900-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
-; GFX900-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
-; GFX900-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0xfefa39ef
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe62e42
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; GFX900-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; GFX900-NEXT: s_mov_b32 s5, 0x3e5ade15
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: s_mov_b32 s4, 0x623fde64
-; GFX900-NEXT: s_mov_b32 s5, 0x3ec71dee
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3efa0199
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x14761f6e
-; GFX900-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x1852b7b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3f56c16c
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x11122322
-; GFX900-NEXT: s_mov_b32 s5, 0x3f811111
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x555502a1
-; GFX900-NEXT: s_mov_b32 s5, 0x3fa55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x55555511
-; GFX900-NEXT: s_mov_b32 s5, 0x3fc55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 11
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe00000
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0
-; GFX900-NEXT: s_mov_b32 s5, 0x40900000
-; GFX900-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX900-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
- %fpext = fpext half %src to double
- %result = call double @llvm.exp2.f64(double %fpext)
- ret double %result
-}
-
-define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
-; SI-SDAG-LABEL: v_exp2_f64_from_fpext_f32:
+; SI-SDAG-LABEL: v_exp2_f64_from_fpext_f16:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[1:2], v0
-; SI-SDAG-NEXT: s_brev_b32 s4, -2
-; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x43300000
-; SI-SDAG-NEXT: v_bfi_b32 v4, s4, v3, v0
-; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0
-; SI-SDAG-NEXT: v_add_f64 v[5:6], v[1:2], v[3:4]
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v3, v0
+; SI-SDAG-NEXT: s_brev_b32 s6, -2
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x43300000
+; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v3
+; SI-SDAG-NEXT: v_bfi_b32 v3, s6, v4, v3
; SI-SDAG-NEXT: s_mov_b32 s4, -1
; SI-SDAG-NEXT: s_mov_b32 s5, 0x432fffff
-; SI-SDAG-NEXT: v_add_f64 v[3:4], v[5:6], -v[3:4]
-; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[1:2]|, s[4:5]
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], v[2:3]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, s[4:5]
+; SI-SDAG-NEXT: v_add_f64 v[2:3], v[4:5], -v[2:3]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
-; SI-SDAG-NEXT: v_add_f64 v[5:6], v[1:2], -v[3:4]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; SI-SDAG-NEXT: v_mul_f64 v[7:8], v[5:6], s[4:5]
+; SI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
-; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[5:6], s[4:5], v[7:8]
-; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0xfca7ab0c
-; SI-SDAG-NEXT: v_mov_b32_e32 v8, 0x3e928af3
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
; SI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], s[4:5], v[7:8]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
; SI-SDAG-NEXT: s_mov_b32 s4, 11
; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
-; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v0, v[3:4]
-; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], 1.0
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
; SI-SDAG-NEXT: s_mov_b32 s4, 0
-; SI-SDAG-NEXT: v_fma_f64 v[3:4], v[5:6], v[7:8], 1.0
+; SI-SDAG-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
; SI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
; SI-SDAG-NEXT: s_mov_b32 s6, 0
; SI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
-; SI-SDAG-NEXT: v_ldexp_f64 v[3:4], v[3:4], v0
-; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[1:2]
-; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[1:2]
-; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x7ff00000
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; SI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[4:5]
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; SI-GISEL-LABEL: v_exp2_f64_from_fpext_f32:
+; SI-GISEL-LABEL: v_exp2_f64_from_fpext_f16:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v4, -1
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x432fffff
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xfefa39ef
; SI-GISEL-NEXT: v_and_b32_e32 v3, 0x80000000, v1
; SI-GISEL-NEXT: v_or_b32_e32 v3, 0x43300000, v3
-; SI-GISEL-NEXT: v_add_f64 v[6:7], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[0:1], v[2:3]
; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[4:5]
-; SI-GISEL-NEXT: v_add_f64 v[2:3], v[6:7], -v[2:3]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x3b39803f
+; SI-GISEL-NEXT: v_add_f64 v[2:3], v[8:9], -v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe62e42
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; SI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3c7abc9e
-; SI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0xfefa39ef
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe62e42
-; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[8:9]
-; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x6a5dcb37
-; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3e5ade15
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e5ade15
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], v[6:7]
; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[10:11], v[12:13]
-; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
-; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[6:7]
; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7c89e6b0
; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3efa0199
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
@@ -8492,32 +8302,33 @@ define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
; SI-GISEL-NEXT: v_mov_b32_e32 v10, 11
; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe00000
; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
-; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
-; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
-; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
-; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
-; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[6:7]
-; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x7ff00000
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v10
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; VI-SDAG-LABEL: v_exp2_f64_from_fpext_f32:
+; VI-SDAG-LABEL: v_exp2_f64_from_fpext_f16:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
; VI-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
; VI-SDAG-NEXT: s_mov_b32 s6, 0
-; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
; VI-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
@@ -8567,15 +8378,16 @@ define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; VI-GISEL-LABEL: v_exp2_f64_from_fpext_f32:
+; VI-GISEL-LABEL: v_exp2_f64_from_fpext_f16:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
-; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
; VI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
@@ -8625,15 +8437,16 @@ define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-SDAG-LABEL: v_exp2_f64_from_fpext_f32:
+; GFX900-SDAG-LABEL: v_exp2_f64_from_fpext_f16:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
-; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
; GFX900-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
@@ -8683,15 +8496,16 @@ define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-GISEL-LABEL: v_exp2_f64_from_fpext_f32:
+; GFX900-GISEL-LABEL: v_exp2_f64_from_fpext_f16:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
-; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
; GFX900-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
@@ -8740,204 +8554,768 @@ define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
- %fpext = fpext float %src to double
+ %fpext = fpext half %src to double
%result = call double @llvm.exp2.f64(double %fpext)
ret double %result
}
-define double @v_exp2_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
-; SI-LABEL: v_exp2_f64_from_fpext_math_f16:
-; SI: ; %bb.0:
-; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; SI-NEXT: s_brev_b32 s10, -2
-; SI-NEXT: v_mov_b32_e32 v4, 0x43300000
-; SI-NEXT: s_mov_b32 s4, -1
-; SI-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; SI-NEXT: s_mov_b32 s5, 0x432fffff
-; SI-NEXT: s_mov_b32 s6, 0x3b39803f
-; SI-NEXT: s_mov_b32 s7, 0x3c7abc9e
-; SI-NEXT: v_cvt_f32_f16_e32 v1, v0
-; SI-NEXT: v_mov_b32_e32 v0, 0
-; SI-NEXT: s_mov_b32 s8, 0xfefa39ef
-; SI-NEXT: s_mov_b32 s9, 0x3fe62e42
-; SI-NEXT: v_cvt_f64_f32_e32 v[2:3], v1
-; SI-NEXT: v_bfi_b32 v1, s10, v4, v1
-; SI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; SI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; SI-NEXT: v_add_f64 v[4:5], v[2:3], v[0:1]
-; SI-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[4:5]
-; SI-NEXT: v_add_f64 v[0:1], v[4:5], -v[0:1]
-; SI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; SI-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
-; SI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; SI-NEXT: v_add_f64 v[4:5], v[2:3], -v[0:1]
-; SI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; SI-NEXT: v_mul_f64 v[8:9], v[4:5], s[6:7]
-; SI-NEXT: s_mov_b32 s6, 0
-; SI-NEXT: v_fma_f64 v[4:5], v[4:5], s[8:9], v[8:9]
-; SI-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; SI-NEXT: s_mov_b32 s4, 0x623fde64
-; SI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; SI-NEXT: s_mov_b32 s5, 0x3efa0199
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x14761f6e
-; SI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; SI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x11122322
-; SI-NEXT: s_mov_b32 s5, 0x3f811111
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x555502a1
-; SI-NEXT: s_mov_b32 s5, 0x3fa55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0x55555511
-; SI-NEXT: s_mov_b32 s5, 0x3fc55555
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 11
-; SI-NEXT: s_mov_b32 s5, 0x3fe00000
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; SI-NEXT: s_mov_b32 s4, 0
-; SI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s5, 0x40900000
-; SI-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
-; SI-NEXT: s_mov_b32 s7, 0xc090cc00
-; SI-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
-; SI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[2:3]
-; SI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[2:3]
-; SI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; SI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; SI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; SI-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
-; SI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; SI-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-LABEL: v_exp2_f64_from_fpext_math_f16:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_add_f16_e32 v0, v0, v1
-; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; VI-NEXT: s_mov_b32 s4, 0x3b39803f
-; VI-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; VI-NEXT: s_mov_b32 s6, 0
-; VI-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; VI-NEXT: s_mov_b32 s7, 0xc090cc00
-; VI-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
-; VI-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
-; VI-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; VI-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0xfefa39ef
-; VI-NEXT: s_mov_b32 s5, 0x3fe62e42
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; VI-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; VI-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; VI-NEXT: s_mov_b32 s5, 0x3e5ade15
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; VI-NEXT: s_mov_b32 s4, 0x623fde64
-; VI-NEXT: s_mov_b32 s5, 0x3ec71dee
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; VI-NEXT: s_mov_b32 s5, 0x3efa0199
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x14761f6e
-; VI-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x1852b7b0
-; VI-NEXT: s_mov_b32 s5, 0x3f56c16c
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x11122322
-; VI-NEXT: s_mov_b32 s5, 0x3f811111
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x555502a1
-; VI-NEXT: s_mov_b32 s5, 0x3fa55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0x55555511
-; VI-NEXT: s_mov_b32 s5, 0x3fc55555
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 11
-; VI-NEXT: s_mov_b32 s5, 0x3fe00000
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; VI-NEXT: s_mov_b32 s4, 0
-; VI-NEXT: s_mov_b32 s5, 0x40900000
-; VI-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; VI-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; VI-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; VI-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; VI-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; VI-NEXT: s_and_b64 vcc, s[4:5], vcc
-; VI-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; VI-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; VI-NEXT: s_setpc_b64 s[30:31]
+define double @v_exp2_f64_from_fpext_f32(float %src) #0 {
+; SI-SDAG-LABEL: v_exp2_f64_from_fpext_f32:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[1:2], v0
+; SI-SDAG-NEXT: s_brev_b32 s4, -2
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x43300000
+; SI-SDAG-NEXT: v_bfi_b32 v4, s4, v3, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0
+; SI-SDAG-NEXT: v_add_f64 v[5:6], v[1:2], v[3:4]
+; SI-SDAG-NEXT: s_mov_b32 s4, -1
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x432fffff
+; SI-SDAG-NEXT: v_add_f64 v[3:4], v[5:6], -v[3:4]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[1:2]|, s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; SI-SDAG-NEXT: v_add_f64 v[5:6], v[1:2], -v[3:4]
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
+; SI-SDAG-NEXT: v_mul_f64 v[7:8], v[5:6], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
+; SI-SDAG-NEXT: v_fma_f64 v[5:6], v[5:6], s[4:5], v[7:8]
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0xfca7ab0c
+; SI-SDAG-NEXT: v_mov_b32_e32 v8, 0x3e928af3
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], s[4:5], v[7:8]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 11
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], s[4:5]
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v0, v[3:4]
+; SI-SDAG-NEXT: v_fma_f64 v[7:8], v[5:6], v[7:8], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s4, 0
+; SI-SDAG-NEXT: v_fma_f64 v[3:4], v[5:6], v[7:8], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; SI-SDAG-NEXT: s_mov_b32 s6, 0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; SI-SDAG-NEXT: v_ldexp_f64 v[3:4], v[3:4], v0
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[1:2]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[1:2]
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
+; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX900-LABEL: v_exp2_f64_from_fpext_math_f16:
-; GFX900: ; %bb.0:
-; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
-; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX900-NEXT: s_mov_b32 s4, 0x3b39803f
-; GFX900-NEXT: s_mov_b32 s5, 0x3c7abc9e
-; GFX900-NEXT: s_mov_b32 s6, 0
-; GFX900-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
-; GFX900-NEXT: s_mov_b32 s7, 0xc090cc00
-; GFX900-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
-; GFX900-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
-; GFX900-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
-; GFX900-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0xfefa39ef
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe62e42
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
-; GFX900-NEXT: v_mov_b32_e32 v7, 0x3e928af3
-; GFX900-NEXT: s_mov_b32 s4, 0x6a5dcb37
-; GFX900-NEXT: s_mov_b32 s5, 0x3e5ade15
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
-; GFX900-NEXT: s_mov_b32 s4, 0x623fde64
-; GFX900-NEXT: s_mov_b32 s5, 0x3ec71dee
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x7c89e6b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3efa0199
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x14761f6e
-; GFX900-NEXT: s_mov_b32 s5, 0x3f2a01a0
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x1852b7b0
-; GFX900-NEXT: s_mov_b32 s5, 0x3f56c16c
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x11122322
-; GFX900-NEXT: s_mov_b32 s5, 0x3f811111
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x555502a1
-; GFX900-NEXT: s_mov_b32 s5, 0x3fa55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0x55555511
-; GFX900-NEXT: s_mov_b32 s5, 0x3fc55555
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 11
-; GFX900-NEXT: s_mov_b32 s5, 0x3fe00000
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
-; GFX900-NEXT: s_mov_b32 s4, 0
-; GFX900-NEXT: s_mov_b32 s5, 0x40900000
-; GFX900-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX900-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
-; GFX900-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
-; GFX900-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
-; GFX900-NEXT: v_mov_b32_e32 v4, 0x7ff00000
-; GFX900-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX900-NEXT: s_and_b64 vcc, s[4:5], vcc
-; GFX900-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
-; GFX900-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
-; GFX900-NEXT: s_setpc_b64 s[30:31]
+; SI-GISEL-LABEL: v_exp2_f64_from_fpext_f32:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, -1
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x432fffff
+; SI-GISEL-NEXT: v_and_b32_e32 v3, 0x80000000, v1
+; SI-GISEL-NEXT: v_or_b32_e32 v3, 0x43300000, v3
+; SI-GISEL-NEXT: v_add_f64 v[6:7], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[4:5]
+; SI-GISEL-NEXT: v_add_f64 v[2:3], v[6:7], -v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x3b39803f
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3c7abc9e
+; SI-GISEL-NEXT: v_mul_f64 v[8:9], v[4:5], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0xfefa39ef
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3fe62e42
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x6a5dcb37
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3e5ade15
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[10:11], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v8, v[2:3]
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v8
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x7ff00000
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-SDAG-LABEL: v_exp2_f64_from_fpext_f32:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
+; VI-SDAG-NEXT: s_mov_b32 s6, 0
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 11
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp2_f64_from_fpext_f32:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; VI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_exp2_f64_from_fpext_f32:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 11
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX900-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp2_f64_from_fpext_f32:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; GFX900-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %fpext = fpext float %src to double
+ %result = call double @llvm.exp2.f64(double %fpext)
+ ret double %result
+}
+
+define double @v_exp2_f64_from_fpext_math_f16(half %src0, half %src1) #0 {
+; SI-SDAG-LABEL: v_exp2_f64_from_fpext_math_f16:
+; SI-SDAG: ; %bb.0:
+; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-SDAG-NEXT: s_brev_b32 s10, -2
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x43300000
+; SI-SDAG-NEXT: s_mov_b32 s4, -1
+; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x432fffff
+; SI-SDAG-NEXT: s_mov_b32 s6, 0x3b39803f
+; SI-SDAG-NEXT: s_mov_b32 s7, 0x3c7abc9e
+; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v0
+; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0
+; SI-SDAG-NEXT: s_mov_b32 s8, 0xfefa39ef
+; SI-SDAG-NEXT: s_mov_b32 s9, 0x3fe62e42
+; SI-SDAG-NEXT: v_cvt_f64_f32_e32 v[2:3], v1
+; SI-SDAG-NEXT: v_bfi_b32 v1, s10, v4, v1
+; SI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; SI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[2:3], v[0:1]
+; SI-SDAG-NEXT: v_cmp_gt_f64_e64 vcc, |v[2:3]|, s[4:5]
+; SI-SDAG-NEXT: v_add_f64 v[0:1], v[4:5], -v[0:1]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
+; SI-SDAG-NEXT: v_add_f64 v[4:5], v[2:3], -v[0:1]
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; SI-SDAG-NEXT: v_mul_f64 v[8:9], v[4:5], s[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s6, 0
+; SI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[8:9], v[8:9]
+; SI-SDAG-NEXT: v_cvt_i32_f64_e32 v8, v[0:1]
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 11
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; SI-SDAG-NEXT: s_mov_b32 s4, 0
+; SI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; SI-SDAG-NEXT: v_fma_f64 v[0:1], v[4:5], v[6:7], 1.0
+; SI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; SI-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v8
+; SI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[2:3]
+; SI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[2:3]
+; SI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
+; SI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; SI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; SI-GISEL-LABEL: v_exp2_f64_from_fpext_math_f16:
+; SI-GISEL: ; %bb.0:
+; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
+; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, -1
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0x432fffff
+; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
+; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0xfefa39ef
+; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe62e42
+; SI-GISEL-NEXT: v_mov_b32_e32 v12, 0xfca7ab0c
+; SI-GISEL-NEXT: v_mov_b32_e32 v13, 0x3e928af3
+; SI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; SI-GISEL-NEXT: v_and_b32_e32 v3, 0x80000000, v1
+; SI-GISEL-NEXT: v_or_b32_e32 v3, 0x43300000, v3
+; SI-GISEL-NEXT: v_add_f64 v[8:9], v[0:1], v[2:3]
+; SI-GISEL-NEXT: v_cmp_gt_f64_e64 vcc, |v[0:1]|, v[4:5]
+; SI-GISEL-NEXT: v_add_f64 v[2:3], v[8:9], -v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x6a5dcb37
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
+; SI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e5ade15
+; SI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; SI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[10:11], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x623fde64
+; SI-GISEL-NEXT: v_fma_f64 v[8:9], v[4:5], v[8:9], v[12:13]
+; SI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3ec71dee
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[8:9], v[6:7]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x7c89e6b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3efa0199
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x1852b7b0
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3f56c16c
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 0x555502a1
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fa55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v10, 11
+; SI-GISEL-NEXT: v_mov_b32_e32 v11, 0x3fe00000
+; SI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[10:11]
+; SI-GISEL-NEXT: v_cvt_i32_f64_e32 v10, v[2:3]
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[6:7], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v8, 0
+; SI-GISEL-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], 1.0
+; SI-GISEL-NEXT: v_mov_b32_e32 v9, 0x40900000
+; SI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v10
+; SI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[8:9]
+; SI-GISEL-NEXT: v_mov_b32_e32 v6, 0x7ff00000
+; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; SI-GISEL-NEXT: v_mov_b32_e32 v5, 0xc090cc00
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; SI-GISEL-NEXT: v_cmp_nlt_f64_e32 vcc, v[0:1], v[4:5]
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
+; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-SDAG-LABEL: v_exp2_f64_from_fpext_math_f16:
+; VI-SDAG: ; %bb.0:
+; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
+; VI-SDAG-NEXT: s_mov_b32 s6, 0
+; VI-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; VI-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; VI-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; VI-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 11
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; VI-SDAG-NEXT: s_mov_b32 s4, 0
+; VI-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; VI-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; VI-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; VI-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; VI-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; VI-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; VI-GISEL-LABEL: v_exp2_f64_from_fpext_math_f16:
+; VI-GISEL: ; %bb.0:
+; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
+; VI-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; VI-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; VI-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; VI-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; VI-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; VI-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; VI-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; VI-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; VI-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; VI-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; VI-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; VI-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-SDAG-LABEL: v_exp2_f64_from_fpext_math_f16:
+; GFX900-SDAG: ; %bb.0:
+; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-SDAG-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX900-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3b39803f
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3c7abc9e
+; GFX900-SDAG-NEXT: s_mov_b32 s6, 0
+; GFX900-SDAG-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-SDAG-NEXT: s_mov_b32 s7, 0xc090cc00
+; GFX900-SDAG-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; GFX900-SDAG-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-SDAG-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-SDAG-NEXT: v_mul_f64 v[6:7], v[4:5], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xfefa39ef
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe62e42
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v6, 0xfca7ab0c
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0x3e928af3
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x6a5dcb37
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3e5ade15
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], s[4:5], v[6:7]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x623fde64
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3ec71dee
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x7c89e6b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3efa0199
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x14761f6e
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f2a01a0
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x1852b7b0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f56c16c
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x11122322
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3f811111
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x555502a1
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fa55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x55555511
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fc55555
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 11
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x3fe00000
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], s[4:5]
+; GFX900-SDAG-NEXT: s_mov_b32 s4, 0
+; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x40900000
+; GFX900-SDAG-NEXT: v_cmp_nlt_f64_e32 vcc, s[4:5], v[0:1]
+; GFX900-SDAG-NEXT: v_cmp_ngt_f64_e64 s[4:5], s[6:7], v[0:1]
+; GFX900-SDAG-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-SDAG-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0x7ff00000
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
+; GFX900-SDAG-NEXT: s_and_b64 vcc, s[4:5], vcc
+; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[4:5]
+; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
+; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX900-GISEL-LABEL: v_exp2_f64_from_fpext_math_f16:
+; GFX900-GISEL: ; %bb.0:
+; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX900-GISEL-NEXT: v_add_f16_e32 v0, v0, v1
+; GFX900-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x3b39803f
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3c7abc9e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfefa39ef
+; GFX900-GISEL-NEXT: v_cvt_f64_f32_e32 v[0:1], v0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe62e42
+; GFX900-GISEL-NEXT: v_rndne_f64_e32 v[2:3], v[0:1]
+; GFX900-GISEL-NEXT: v_add_f64 v[4:5], v[0:1], -v[2:3]
+; GFX900-GISEL-NEXT: v_cvt_i32_f64_e32 v2, v[2:3]
+; GFX900-GISEL-NEXT: v_mul_f64 v[6:7], v[4:5], v[6:7]
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[6:7]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0x6a5dcb37
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0x3e5ade15
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0xfca7ab0c
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3e928af3
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x623fde64
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3ec71dee
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x7c89e6b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3efa0199
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x14761f6e
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f2a01a0
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x1852b7b0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f56c16c
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x11122322
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3f811111
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x555502a1
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fa55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 0x55555511
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fc55555
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v8, 11
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v9, 0x3fe00000
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
+; GFX900-GISEL-NEXT: v_fma_f64 v[6:7], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], 1.0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v6, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v7, 0xc090cc00
+; GFX900-GISEL-NEXT: v_cmp_nlt_f64_e64 s[4:5], v[0:1], v[6:7]
+; GFX900-GISEL-NEXT: v_ldexp_f64 v[2:3], v[4:5], v2
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v5, 0x40900000
+; GFX900-GISEL-NEXT: v_cmp_ngt_f64_e32 vcc, v[0:1], v[4:5]
+; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x7ff00000
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, v0, v3, vcc
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v2, s[4:5]
+; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[4:5]
+; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
%fadd = fadd half %src0, %src1
%fpext = fpext half %fadd to double
%result = call double @llvm.exp2.f64(double %fpext)
@@ -9639,3 +10017,7 @@ define double @v_exp2_f64_contract_nnan_ninf(double %in) #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX900: {{.*}}
+; SI: {{.*}}
+; VI: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/lrint.ll b/llvm/test/CodeGen/AMDGPU/lrint.ll
index 3ef75191648a2..61820afd9b774 100644
--- a/llvm/test/CodeGen/AMDGPU/lrint.ll
+++ b/llvm/test/CodeGen/AMDGPU/lrint.ll
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub --version 5
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GFX9,GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,GFX11,GFX11-GISEL,GFX11-GISEL-FAKE16 %s
declare float @llvm.rint.f32(float)
declare i32 @llvm.lrint.i32.f32(float)
diff --git a/llvm/test/CodeGen/AMDGPU/lround.ll b/llvm/test/CodeGen/AMDGPU/lround.ll
index 4f7bdc52e4ebf..887735af85b7d 100644
--- a/llvm/test/CodeGen/AMDGPU/lround.ll
+++ b/llvm/test/CodeGen/AMDGPU/lround.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --extra_scrub --version 5
; RUN: llc -global-isel=0 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GFX9-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10-GISEL %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GFX10-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-SDAG-TRUE16 %s
; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-SDAG,GFX11-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-GISEL-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-GISEL-TRUE16 %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.00 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11-GISEL,GFX11-GISEL-FAKE16 %s
define i32 @intrinsic_lround_i32_f32(float %arg) {
; GFX9-SDAG-LABEL: intrinsic_lround_i32_f32:
@@ -924,8 +924,9 @@ define i32 @intrinsic_lround_i32_f16(half %arg) {
; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0x3c00
; GFX9-GISEL-NEXT: v_cmp_ge_f16_e64 vcc, |v2|, 0.5
; GFX9-GISEL-NEXT: v_cndmask_b32_e32 v2, 0, v3, vcc
-; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9-GISEL-NEXT: v_bfi_b32 v0, s4, v2, v0
+; GFX9-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX9-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
+; GFX9-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
; GFX9-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX9-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
@@ -949,9 +950,11 @@ define i32 @intrinsic_lround_i32_f16(half %arg) {
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: v_trunc_f16_e32 v1, v0
; GFX10-GISEL-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
; GFX10-GISEL-NEXT: v_cmp_ge_f16_e64 s4, |v2|, 0.5
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s4
-; GFX10-GISEL-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX10-GISEL-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX10-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX10-GISEL-NEXT: v_add_f16_e32 v0, v1, v0
; GFX10-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; GFX10-GISEL-NEXT: v_cvt_i32_f32_e32 v0, v0
@@ -995,16 +998,17 @@ define i32 @intrinsic_lround_i32_f16(half %arg) {
; GFX11-GISEL-TRUE16-LABEL: intrinsic_lround_i32_f16:
; GFX11-GISEL-TRUE16: ; %bb.0: ; %entry
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_trunc_f16_e32 v1.h, v1.l
-; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e32 v1.l, v1.l, v1.h
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_trunc_f16_e32 v0.h, v0.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e32 v1.l, v0.l, v0.h
+; GFX11-GISEL-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cmp_ge_f16_e64 s0, |v1.l|, 0.5
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b16 v1.l, 0, 0x3c00, s0
+; GFX11-GISEL-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
-; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v1.h, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-TRUE16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
@@ -1014,16 +1018,18 @@ define i32 @intrinsic_lround_i32_f16(half %arg) {
; GFX11-GISEL-FAKE16: ; %bb.0: ; %entry
; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-FAKE16-NEXT: v_trunc_f16_e32 v1, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-FAKE16-NEXT: v_sub_f16_e32 v2, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff8000, v0
; GFX11-GISEL-FAKE16-NEXT: v_cmp_ge_f16_e64 s0, |v2|, 0.5
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x3c00, s0
-; GFX11-GISEL-FAKE16-NEXT: v_bfi_b32 v0, 0x7fff, v2, v0
+; GFX11-GISEL-FAKE16-NEXT: v_and_b32_e32 v2, 0x7fff, v2
; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e32 v0, v1, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-FAKE16-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
index ef7e06883a84f..f2fbb1bd4e43d 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgpu11.50 < %s | FileCheck %s --check-prefixes=CHECK,SDAG
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.50 < %s | FileCheck %s --check-prefixes=CHECK,GISEL-GFX11
+; RUN: llc -global-isel=1 -mtriple=amdgpu11.50 < %s | FileCheck %s --check-prefixes=CHECK,GISEL-GFX11
; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 < %s | FileCheck %s --check-prefixes=CHECK,SDAG
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 < %s | FileCheck %s --check-prefixes=CHECK,GISEL-GFX12
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.00 < %s | FileCheck %s --check-prefixes=CHECK,GISEL-GFX12
define amdgpu_vs float @sitofp_i32_to_f32(i32 inreg %val) {
; CHECK-LABEL: sitofp_i32_to_f32:
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