[llvm-branch-commits] [llvm] [AMDGPU] Upstream True16 runlines for various tests (PR #209891)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Jul 15 13:53:30 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: Domenic Nutile (saxlungs)
<details>
<summary>Changes</summary>
PR stack:
https://github.com/llvm/llvm-project/pull/209891 <- YOU ARE HERE
https://github.com/llvm/llvm-project/pull/209890
https://github.com/llvm/llvm-project/pull/209889
https://github.com/llvm/llvm-project/pull/209888
<sub>Stack created with <a href="https://github.com/github/gh-stack">GitHub Stacks CLI</a> • <a href="https://gh.io/stacks-feedback">Give Feedback 💬</a></sub>
---
Patch is 640.49 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209891.diff
21 Files Affected:
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll (+5-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll (+2559-652)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll (+1177-284)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll (+322-149)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll (+290-137)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll (+218-100)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll (+416-303)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll (+438-322)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll (+107-32)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+191-95)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll (+102-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll (+85-42)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll (+57-28)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll (+30-15)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll (+4-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll (+4-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll (+4-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll (+259-97)
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+1270-764)
- (modified) llvm/test/CodeGen/AMDGPU/mul.ll (+4-2)
- (modified) llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll (+121-29)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
index 048f5710c880c..c1742bff4b06f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgpu10.10 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX10 %s
-; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX11 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX11-TRUE16 %s
+; RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -global-isel < %s | FileCheck -check-prefixes=CHECK,GFX11,GFX11-FAKE16 %s
declare i32 @llvm.amdgcn.ballot.i32(i1)
declare i32 @llvm.ctpop.i32(i32)
@@ -478,3 +479,6 @@ exit:
store i32 %ballot, ptr addrspace(1) %out
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-FAKE16: {{.*}}
+; GFX11-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
index 89f73ba07d58d..fce5fd01065cc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
@@ -1,8 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) {
; GFX9-LABEL: atomic_swap_i32_1d:
@@ -37,21 +39,65 @@ define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: atomic_swap_i32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_swap_i32_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_swap_i32_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_swap_i32_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_swap_i32_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float
@@ -91,21 +137,65 @@ define amdgpu_ps float @atomic_add_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: atomic_add_i32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_add_i32_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_add_i32_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_add_i32_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_add_i32_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float
@@ -145,21 +235,65 @@ define amdgpu_ps float @atomic_sub_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: atomic_sub_i32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_sub_i32_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_sub_i32_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_sub_i32_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_sub_i32_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float
@@ -199,21 +333,65 @@ define amdgpu_ps float @atomic_smin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: atomic_smin_i32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_smin_i32_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_smin_i32_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_smin_i32_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX12-FAKE16-LABEL: atomic_smin_i32_1d:
+; GFX12-FAKE16: ; %bb.0: ; %main_body
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX12-FAKE16-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
+; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX12-FAKE16-NEXT: ; return to shader part epilog
main_body:
%v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i16(i32 %data, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
%out = bitcast i32 %v to float
@@ -253,21 +431,65 @@ define amdgpu_ps float @atomic_umin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: ; return to shader part epilog
;
-; GFX12-LABEL: atomic_umin_i32_1d:
-; GFX12: ; %bb.0: ; %main_body
-; GFX12-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-NEXT: s_mov_b32 s0, s2
-; GFX12-NEXT: s_mov_b32 s1, s3
-; GFX12-NEXT: s_mov_b32 s2, s4
-; GFX12-NEXT: s_mov_b32 s3, s5
-; GFX12-NEXT: v_lshl_or_b32 v1, s0, 16, v1
-; GFX12-NEXT: s_mov_b32 s4, s6
-; GFX12-NEXT: s_mov_b32 s5, s7
-; GFX12-NEXT: s_mov_b32 s6, s8
-; GFX12-NEXT: s_mov_b32 s7, s9
-; GFX12-NEXT: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16
-; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: ; return to shader part epilog
+; GFX11-TRUE16-LABEL: atomic_umin_i32_1d:
+; GFX11-TRUE16: ; %bb.0: ; %main_body
+; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX11-TRUE16-NEXT: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: ; return to shader part epilog
+;
+; GFX11-FAKE16-LABEL: atomic_umin_i32_1d:
+; GFX11-FAKE16: ; %bb.0: ; %main_body
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2
+; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
+; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4
+; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1
+; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6
+; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7
+; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8
+; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9
+; GFX11-FAKE16-NEXT: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX12-TRUE16-LABEL: atomic_umin_i32_1d:
+; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2
+; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3
+; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4
+; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5
+; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6
+; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7
+; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8
+; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9
+; GFX12-TRUE16-NEXT: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D t...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/209891
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