[llvm-branch-commits] [llvm] [CodeGen] Add initial multi-def rematerialization support (PR #197580)

[Lucas Ramirez via llvm-branch-commits]

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@@ -28,11 +29,14 @@ namespace llvm {
 ///
 /// At the moment this supports rematerializing registers that meet all of the
 /// following constraints.
-/// 1. The register is virtual and has a single defining instruction.
-/// 2. The single defining instruction is deemed rematerializable by the TII and
-///    doesn't have any physical register use that is both non-constant and
+/// 1. The register is virtual.
+/// 2. The register is defined within a single region---potentially over
+///    multiple MIs---and isn't used by a MI that is not defining part of the
+///    register before its last defining MI.
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lucas-rami wrote:

Yes that's right. This restriction essentially means that, if the rematerializer only ever rematerializes all the defs of a register together, it can treat all virtual registers as having a "single value" (the one at the end). Supporting the latter case would require it to track `VNInfo`s individually rather that virtual registers. 

https://github.com/llvm/llvm-project/pull/197580