[llvm-branch-commits] [llvm] [RISCV] Support CodeGen of Zilx extension (PR #209420)

[Pengcheng Wang via llvm-branch-commits]

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/209420

>From bf5ad3b324ff511ecc67ecf14c25cddabf9c7aa1 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Tue, 14 Jul 2026 17:56:49 +0800
Subject: [PATCH] clang-format

Created using spr 1.3.6-beta.1
---
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 9208762e8d1fe..0e69533f56a50 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3736,8 +3736,8 @@ static bool isRegRegScaleLoadOrStore(SDNode *User, SDValue Add,
     return false;
   EVT VT = cast<MemSDNode>(User)->getMemoryVT();
   if (!(VT.isScalarInteger() &&
-        (Subtarget.hasStdExtZilx() ||
-         Subtarget.hasVendorXTHeadMemIdx() || Subtarget.hasVendorXqcisls())) &&
+        (Subtarget.hasStdExtZilx() || Subtarget.hasVendorXTHeadMemIdx() ||
+         Subtarget.hasVendorXqcisls())) &&
       !((VT == MVT::f32 || VT == MVT::f64) &&
         Subtarget.hasVendorXTHeadFMemIdx()))
     return false;