[llvm-branch-commits] [llvm] AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (26) (PR #209487)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Jul 14 06:58:50 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/209487
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
>From f249e96d40ba0c13b419d86282454b1614cc7f86 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 25 Jun 2026 09:57:12 +0200
Subject: [PATCH] AMDGPU: Migrate CodeGen tests to amdgpu subarch triple (26)
Mechanically migrate the command-line target spelling on llc/opt RUN lines in
llvm/test/CodeGen/AMDGPU from -mtriple=amdgcn ... -mcpu=<gfx> to the folded
subarch triple form (e.g. -mtriple=amdgpu9.00-amd-amdhsa), dropping the
redundant -mcpu.
Co-Authored-By: Claude <noreply at anthropic.com> (Claude-Opus-4.8)
---
.../AMDGPU/NextUseAnalysis/acyclic-014bb.mir | 6 ++--
.../AMDGPU/NextUseAnalysis/acyclic-770bb.mir | 6 ++--
.../acyclic-cfg-with-self-loop.mir | 6 ++--
.../acyclic-phi-merge-distances.mir | 6 ++--
.../complex-acyclic-cfg-with-4-self-loops.mir | 6 ++--
.../complex-control-flow-11blocks.mir | 6 ++--
.../complex-control-flow-15blocks.mir | 6 ++--
.../NextUseAnalysis/complex-single-loop-a.mir | 6 ++--
.../NextUseAnalysis/complex-single-loop.mir | 6 ++--
.../double-nested-loops-complex-cfg.mir | 6 ++--
...lse_with_loops_nested_in_2_outer_loops.mir | 6 ++--
.../inner_cfg_in_2_nested_loops.mir | 6 ++--
...op_nested_in_3_outer_loops_complex_cfg.mir | 6 ++--
.../nested-loops-with-side-exits-a.mir | 6 ++--
.../NextUseAnalysis/sequence_2_loops.mir | 6 ++--
.../NextUseAnalysis/simple-loop-3blocks.mir | 6 ++--
.../NextUseAnalysis/spill-vreg-many-lanes.mir | 9 +++---
.../NextUseAnalysis/test_ers_basic_case.mir | 6 ++--
...t_ers_do_not_spill_restore_inside_loop.mir | 6 ++--
...t_ers_emit_restore_in_common_dominator.mir | 6 ++--
...st_ers_emit_restore_in_loop_preheader1.mir | 6 ++--
...st_ers_emit_restore_in_loop_preheader2.mir | 6 ++--
...st_ers_emit_restore_in_loop_preheader3.mir | 6 ++--
...st_ers_emit_restore_in_loop_preheader4.mir | 6 ++--
.../test_ers_keep_spilled_reg_live.mir | 6 ++--
.../test_ers_multiple_spills1.mir | 6 ++--
.../test_ers_multiple_spills2.mir | 6 ++--
.../test_ers_multiple_spills3.mir | 6 ++--
.../NextUseAnalysis/test_ers_nested_loops.mir | 6 ++--
...common_dominator_and_optimize_restores.mir | 6 ++--
.../test_ers_spill_loop_livethrough_reg.mir | 6 ++--
...est_ers_spill_loop_value_in_exit_block.mir | 6 ++--
.../three-tier-ranking-nested-loops.mir | 6 ++--
.../NextUseAnalysis/triple-nested-loops.mir | 6 ++--
.../NextUseAnalysis/two-sequential-loops.mir | 6 ++--
llvm/test/CodeGen/AMDGPU/minmax.ll | 32 +++++++++----------
.../CodeGen/AMDGPU/minmax3-tree-reduction.ll | 6 ++--
.../mir-dynamic-vgpr-block-size-roundtrip.mir | 2 +-
.../AMDGPU/misaligned-vgpr-regsequence.mir | 2 +-
.../misched-into-wmma-hazard-shadow.mir | 2 +-
.../test/CodeGen/AMDGPU/misched-killflags.mir | 4 +--
llvm/test/CodeGen/AMDGPU/missing-store.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll | 6 ++--
.../CodeGen/AMDGPU/mixed-wave32-wave64.ll | 2 +-
.../CodeGen/AMDGPU/mixed_wave32_wave64.ll | 4 +--
.../AMDGPU/mmo-target-flags-folding.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mmra.ll | 2 +-
.../AMDGPU/mode-register-fpconstrain.ll | 2 +-
...mode-register-fptrunc.gfx11plus-fake16.mir | 4 +--
.../mode-register-fptrunc.gfx11plus.mir | 2 +-
.../CodeGen/AMDGPU/mode-register-fptrunc.mir | 4 +--
llvm/test/CodeGen/AMDGPU/mode-register.mir | 4 +--
.../test/CodeGen/AMDGPU/modf-constant-fold.ll | 2 +-
.../AMDGPU/module-lds-false-sharing.ll | 8 ++---
.../move-addr64-rsrc-dead-subreg-writes.ll | 2 +-
.../AMDGPU/move-load-addr-to-valu-flat.mir | 2 +-
.../CodeGen/AMDGPU/move-load-addr-to-valu.mir | 2 +-
.../CodeGen/AMDGPU/move-to-valu-absdiff.mir | 4 +--
.../CodeGen/AMDGPU/move-to-valu-addsubu64.ll | 2 +-
.../AMDGPU/move-to-valu-atomicrmw-system.ll | 4 +--
.../CodeGen/AMDGPU/move-to-valu-atomicrmw.ll | 4 +--
.../CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll | 4 +--
.../CodeGen/AMDGPU/move-to-valu-lshl_add.ll | 2 +-
.../CodeGen/AMDGPU/move-to-valu-lshlrev.mir | 4 +--
...-to-valu-pseudo-scalar-trans-f16-fake16.ll | 2 +-
...-to-valu-pseudo-scalar-trans-f16-true16.ll | 2 +-
.../move-to-valu-pseudo-scalar-trans.ll | 2 +-
.../AMDGPU/move-to-valu-vimage-vsample.ll | 4 +--
.../CodeGen/AMDGPU/move-to-valu-worklist.ll | 2 +-
llvm/test/CodeGen/AMDGPU/movreld-bug.ll | 6 ++--
...uf-legalize-operands-non-ptr-intrinsics.ll | 12 +++----
.../CodeGen/AMDGPU/mubuf-legalize-operands.ll | 12 +++----
.../AMDGPU/mubuf-legalize-operands.mir | 12 +++----
.../CodeGen/AMDGPU/mubuf-offset-private.ll | 6 ++--
.../mubuf-shader-vgpr-non-ptr-intrinsics.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mubuf.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mul.i16.ll | 10 +++---
llvm/test/CodeGen/AMDGPU/mul.ll | 16 +++++-----
.../CodeGen/AMDGPU/mul24-pass-ordering.ll | 2 +-
llvm/test/CodeGen/AMDGPU/mul_int24.ll | 6 ++--
llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll | 6 ++--
.../multi-call-resource-usage-mcexpr.ll | 2 +-
.../AMDGPU/multi-divergent-exit-region.ll | 6 ++--
.../CodeGen/AMDGPU/multi-dword-vgpr-spill.ll | 4 +--
.../CodeGen/AMDGPU/multi-use-implicit-def.mir | 2 +-
llvm/test/CodeGen/AMDGPU/multilevel-break.ll | 4 +--
.../AMDGPU/naked-fn-with-frame-pointer.ll | 2 +-
llvm/test/CodeGen/AMDGPU/nand.ll | 8 ++---
.../CodeGen/AMDGPU/narrow_math_for_and.ll | 2 +-
.../AMDGPU/need-fp-from-vgpr-spills.ll | 2 +-
llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll | 2 +-
.../AMDGPU/neighboring-mfma-padding.mir | 22 ++++++-------
llvm/test/CodeGen/AMDGPU/nested-calls.ll | 6 ++--
.../CodeGen/AMDGPU/nested-loop-conditions.ll | 4 +--
llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll | 2 +-
.../AMDGPU/no-corresponding-integer-type.ll | 4 +--
.../CodeGen/AMDGPU/no-dup-inst-prefetch.ll | 4 +--
.../CodeGen/AMDGPU/no-fold-accvgpr-mov.ll | 4 +--
.../CodeGen/AMDGPU/no-fold-accvgpr-mov.mir | 6 ++--
.../CodeGen/AMDGPU/no-fold-accvgpr-read.mir | 6 ++--
101 files changed, 266 insertions(+), 267 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
index aa7b9ab544bc2..d0fbac674e523 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-014bb.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
index 88ab1476a8064..1085000dd83ec 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-770bb.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
index 38986abbcb884..366cd4b757844 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-cfg-with-self-loop.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
index fcfc2f6f2b95a..7e9cf15988231 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/acyclic-phi-merge-distances.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
index 40d5d83ed14bd..6fe28d7318b13 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-acyclic-cfg-with-4-self-loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
index bb691d97e453f..356e533e40233 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-11blocks.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
index 80751ae5f9de3..7dfc0890aabf6 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-control-flow-15blocks.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
index ac631a6a1ec14..5b4391c82a993 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop-a.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -7,7 +7,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -15,7 +15,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
index 001338cc7e4f6..0abdb905d0f2e 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/complex-single-loop.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
index 454f356b42e74..6744895e4896f 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/double-nested-loops-complex-cfg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
index c4d06ebcdc16b..f35dff5b8eab8 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/if_else_with_loops_nested_in_2_outer_loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
index 2045efede960a..c5a44b5d7c854 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/inner_cfg_in_2_nested_loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
index 96d6a47817860..465454e5aeaf1 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/loop_nested_in_3_outer_loops_complex_cfg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
index 73998b53298c2..20932f9c0331d 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/nested-loops-with-side-exits-a.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
index 94adf7ccb5938..fbcf447271740 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/sequence_2_loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
index 4e1d23d9c0a04..4338457e42221 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/simple-loop-3blocks.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
index ee2962b2df975..c0b6680d4a375 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/spill-vreg-many-lanes.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 \
+# RUN: llc -mtriple=amdgpu9.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 \
+# RUN: llc -mtriple=amdgpu9.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 \
+# RUN: llc -mtriple=amdgpu9.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -23,11 +23,10 @@
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
--- |
- define void @stack_args_vgpr_spill(<32 x float> %arg0, <32 x float> %arg1, ptr addrspace(1) %p, ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, ptr addrspace(1) %p6, ptr addrspace(1) %p7) #0 {
+ define void @stack_args_vgpr_spill(<32 x float> %arg0, <32 x float> %arg1, ptr addrspace(1) %p, ptr addrspace(1) %p1, ptr addrspace(1) %p2, ptr addrspace(1) %p3, ptr addrspace(1) %p4, ptr addrspace(1) %p5, ptr addrspace(1) %p6, ptr addrspace(1) %p7) {
ret void
}
- attributes #0 = { "target-cpu"="gfx900" }
...
---
name: stack_args_vgpr_spill
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
index 6149ed3ba97c7..a7713d7b1d91f 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_basic_case.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
index a62f0b7bf7617..69b4a4ba60ee9 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_do_not_spill_restore_inside_loop.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
index f4e5aee19feb3..97206f60d7adf 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_common_dominator.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
index c35d8c87cc512..f2c85920feb3b 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader1.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
index 6e1222c201702..1368f5b60da81 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader2.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
index dcc91c0e55847..434b3ec6c24bb 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader3.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
index c6a2c26bba45c..231fcdea8cfde 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_emit_restore_in_loop_preheader4.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
index dea9a4f52dd2c..2d3b9bf2c0c1e 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_keep_spilled_reg_live.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
index 6ae2cb8abf79d..cb14edadc7a0e 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills1.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
index 79c85daa455f6..772ac74291933 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills2.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
index 0f9a5d64ad4b7..324976cec20e5 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_multiple_spills3.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
index ea3fc76c982ca..8b1a1ae76df48 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_nested_loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
index 4af39e0d2b123..f8e354de9aa0c 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_in_common_dominator_and_optimize_restores.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
index 7566e9113b245..0d595ede9c992 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_livethrough_reg.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
index 3aa194e46fb75..eb605289042d5 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/test_ers_spill_loop_value_in_exit_block.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
index b9ffb229b2d12..d6ca54f557f3a 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/three-tier-ranking-nested-loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
index daf689192e637..904a7971321ea 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/triple-nested-loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
index 896f13aa02e65..d25842ccbf55b 100644
--- a/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
+++ b/llvm/test/CodeGen/AMDGPU/NextUseAnalysis/two-sequential-loops.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=graphics \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -6,7 +6,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-GX-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: -run-pass=amdgpu-next-use-printer \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
@@ -14,7 +14,7 @@
# RUN: -filetype=null \
# RUN: %s | FileCheck --check-prefix=CHECK-CP-JSON %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 \
+# RUN: llc -mtriple=amdgpu12.00 \
# RUN: "-passes=require<amdgpu-next-use-analysis>,print<amdgpu-next-use-analysis>" \
# RUN: -amdgpu-next-use-analysis-config=compute \
# RUN: -amdgpu-next-use-analysis-dump-distance-as-json=- \
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index c7297da7f6ebd..dba6532f06a02 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -1,20 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-TRUE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,SDAG,SDAG-GFX1170,SDAG-GFX1170-TRUE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,SDAG,SDAG-GFX1170,SDAG-GFX1170-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,GISEL,GISEL-GFX1170,GISEL-GFX1170-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1170 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,GISEL,GISEL-GFX1170,GISEL-GFX1170-FAKE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-TRUE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-FAKE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-TRUE16 %s
-; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-FAKE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-TRUE16 %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,SDAG,SDAG-GFX11,SDAG-GFX11-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX11,GISEL,GISEL-GFX11,GISEL-GFX11-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.70 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,SDAG,SDAG-GFX1170,SDAG-GFX1170-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu11.70 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,SDAG,SDAG-GFX1170,SDAG-GFX1170-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.70 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,GISEL,GISEL-GFX1170,GISEL-GFX1170-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu11.70 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1170,GISEL,GISEL-GFX1170,GISEL-GFX1170-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,SDAG,SDAG-GFX12,SDAG-GFX12-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.00 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX12,GISEL,GISEL-GFX12,GISEL-GFX12-FAKE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-TRUE16 %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,SDAG,SDAG-GFX1250,SDAG-GFX1250-FAKE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.50 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-TRUE16 %s
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgpu12.50 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX1250,GISEL,GISEL-GFX1250,GISEL-GFX1250-FAKE16 %s
define i32 @test_minmax_i32(i32 %a, i32 %b, i32 %c) {
; GFX11-LABEL: test_minmax_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
index a8f5d1d1bc4b4..ed5989352c77e 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax3-tree-reduction.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
; Test that tree-structured min/max reductions form min3/max3 efficiently.
; The key pattern is op(op(a,b), op(c,d)) which should become
diff --git a/llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir b/llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
index d72f9584fc1d2..bdaadead58974 100644
--- a/llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
+++ b/llvm/test/CodeGen/AMDGPU/mir-dynamic-vgpr-block-size-roundtrip.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=none -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.00-amd-amdpal -run-pass=none -o - %s | FileCheck %s
# Test that dynamicVGPRBlockSize round-trips through MIR serialization.
diff --git a/llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir b/llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
index 35f64a8cad934..0ecc2be0235a0 100644
--- a/llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
+++ b/llvm/test/CodeGen/AMDGPU/misaligned-vgpr-regsequence.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -start-after=si-load-store-opt %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42-amd-amdhsa -start-after=si-load-store-opt %s -o - | FileCheck %s
# CHECK: misaligned_regsequence:
# CHECK: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir b/llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
index e2082ec9f2baf..be4f075820254 100644
--- a/llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
+++ b/llvm/test/CodeGen/AMDGPU/misched-into-wmma-hazard-shadow.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=postmisched,post-RA-hazard-rec %s -o - | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=postmisched,post-RA-hazard-rec %s -o - | FileCheck --check-prefix=GCN %s
# Bring all independent V_LSHL_ADD_U32_e64 instructions into the shadow
# of the WMMA so then hazard recognizer only need to insert 4 V_NOP_e32
diff --git a/llvm/test/CodeGen/AMDGPU/misched-killflags.mir b/llvm/test/CodeGen/AMDGPU/misched-killflags.mir
index a7fa8ad5389b0..07418ab1fc4e3 100644
--- a/llvm/test/CodeGen/AMDGPU/misched-killflags.mir
+++ b/llvm/test/CodeGen/AMDGPU/misched-killflags.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass=post-RA-sched -o - %s | FileCheck %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=post-RA-sched -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -verify-machineinstrs -run-pass=post-RA-sched -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.03-amd-amdhsa -passes=post-RA-sched -o - %s | FileCheck %s
# Make sure ScheduleDAGInstrs::fixupKills does not produce invalid kill flags.
---
name: func0
diff --git a/llvm/test/CodeGen/AMDGPU/missing-store.ll b/llvm/test/CodeGen/AMDGPU/missing-store.ll
index c42c7c37765c6..5f9b3c9fd8c5d 100644
--- a/llvm/test/CodeGen/AMDGPU/missing-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/missing-store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
@ptr_load = addrspace(3) global ptr addrspace(4) poison, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll b/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
index 9e46ba839ffff..b79ad13a9254d 100644
--- a/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
+++ b/llvm/test/CodeGen/AMDGPU/mixed-vmem-types.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-GISEL %s
+; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -global-isel -mtriple=amdgpu12.00 < %s | FileCheck -check-prefixes=GFX12-GISEL %s
define amdgpu_cs void @mixed_vmem_types_sampler_reads(i32 inreg %globalTable, i32 inreg %perShaderTable, i32 inreg %descTable0, i32 inreg %descTable1, <3 x i32> inreg %WorkgroupId, i32 inreg %MultiDispatchInfo, <3 x i32> %LocalInvocationId) #0 {
; GFX11-LABEL: mixed_vmem_types_sampler_reads:
diff --git a/llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll b/llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
index e82c03c21b6ee..d9b13fc991a97 100644
--- a/llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
+++ b/llvm/test/CodeGen/AMDGPU/mixed-wave32-wave64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu10.10--amdpal -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: _amdgpu_hs_main:
diff --git a/llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll b/llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
index 6b1d9ebc778e8..85f177486b221 100644
--- a/llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
+++ b/llvm/test/CodeGen/AMDGPU/mixed_wave32_wave64.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN %s
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN %s
+; RUN: llc -mtriple=amdgpu10.10--amdpal < %s | FileCheck -check-prefixes=GCN %s
+; RUN: llc -mtriple=amdgpu11.00--amdpal < %s | FileCheck -check-prefixes=GCN %s
;
; Check that PS is wave64
; GCN-LABEL: _amdgpu_ps_main:
diff --git a/llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll b/llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
index 7871ac7d4fe7f..f9c74536b560b 100644
--- a/llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
+++ b/llvm/test/CodeGen/AMDGPU/mmo-target-flags-folding.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck --check-prefix=GCN %s
; This is used to crash due to mismatch of MMO target flags when folding
; a LOAD SDNodes with different flags.
diff --git a/llvm/test/CodeGen/AMDGPU/mmra.ll b/llvm/test/CodeGen/AMDGPU/mmra.ll
index 7cf91eb63c837..70d713e4a60cb 100644
--- a/llvm/test/CodeGen/AMDGPU/mmra.ll
+++ b/llvm/test/CodeGen/AMDGPU/mmra.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -stop-after=finalize-isel < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.00 -stop-after=finalize-isel < %s | FileCheck %s
declare void @readsMem(ptr) #0
declare void @writesMem(ptr) #1
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
index 8a29229c152fe..174435795c5ef 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 %s -o - | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa %s -o - | FileCheck -check-prefix=GCN %s
; The si-mode-register pass is changing the default mode for FP constrained operations.
; It must ignore for strictfp functions.
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
index b3a4aa7b6c19a..a29e48af36d0a 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus-fake16.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -passes si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
+# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
+# RUN: llc -mtriple=amdgpu11.00 -mattr=-real-true16 -passes si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
---
name: ftrunc_tonearest
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
index 9b439af4bf7b4..752ae87f7738d 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.gfx11plus.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
+# RUN: llc -mtriple=amdgpu11.00 -mattr=+real-true16 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=GFX11
---
name: ftrunc_tonearest
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
index a28f347603ab7..f64a2a3c5fb7c 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register-fptrunc.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=CHECK
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -mtriple=amdgpu9.00 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=CHECK
+# RUN: llc -mtriple=amdgpu10.10 -run-pass si-mode-register %s -o - | FileCheck %s --check-prefixes=CHECK
---
name: ftrunc_tonearest
diff --git a/llvm/test/CodeGen/AMDGPU/mode-register.mir b/llvm/test/CodeGen/AMDGPU/mode-register.mir
index aac6dcb01f3d9..1dd6499ca2733 100644
--- a/llvm/test/CodeGen/AMDGPU/mode-register.mir
+++ b/llvm/test/CodeGen/AMDGPU/mode-register.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass si-mode-register %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-mode-register %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass si-mode-register %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.00 -passes=si-mode-register %s -o - | FileCheck %s
---
# check that the mode is changed to rtz from default rtn for interp f16
diff --git a/llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll b/llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
index a801ff73286a7..799e88c5b3714 100644
--- a/llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
+++ b/llvm/test/CodeGen/AMDGPU/modf-constant-fold.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck %s
declare { float, float } @llvm.modf.f32(float)
declare { <2 x float>, <2 x float> } @llvm.modf.v2f32(<2 x float>)
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index 8adfed45e2514..87c12e9942e55 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s
+; RUN: llc -mtriple=amdgpu9.00 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX9 %s
+; RUN: llc -mtriple=amdgpu10.10 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10 < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s
; Test case looks at the allocated offset of @used_by_both. It's at zero when
; allocated by itself, but at 8 when allocated in combination with the double.
diff --git a/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll b/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
index b38388d748f21..48b09f400b2e0 100644
--- a/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu7.00-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCN %s
; Check that when mubuf addr64 instruction is handled in moveToVALU
; from the pointer, dead register writes are not emitted.
diff --git a/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir b/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
index 95ccf6c0a4a33..9d6c0d0a32b54 100644
--- a/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
+++ b/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu-flat.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GCN %s
---
name: flat_load_saddr_to_valu
diff --git a/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir b/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
index c1c5afcd3e96d..d2187f49e8027 100644
--- a/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
+++ b/llvm/test/CodeGen/AMDGPU/move-load-addr-to-valu.mir
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
+# RUN: llc -mtriple=amdgpu9.00 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
---
name: global_load_saddr_to_valu
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir b/llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
index 267543800bf68..a73d3a2c2d1e2 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-absdiff.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GFX12 %s
---
name: absdiff_i32
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
index b524a1ddeffe9..b557bc6d29a7e 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-addsubu64.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu12.00 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
define amdgpu_kernel void @add_reg_imm(ptr addrspace(1) %ptr) {
; CHECK-LABEL: name: add_reg_imm
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
index 60f77bda6d50e..9fa2d47d78821 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw-system.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
-; XUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefixes=GCN,VI %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
+; XUN: llc -mtriple=amdgpu8.03 < %s | FileCheck --check-prefixes=GCN,VI %s
; FIXME: broken on VI because flat instructions need to be emitted
; instead of addr64 equivalent of the _OFFSET variants.
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
index 2d73a6b015295..a21659a033255 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
-; XUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefixes=GCN,VI %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
+; XUN: llc -mtriple=amdgpu8.03 < %s | FileCheck --check-prefixes=GCN,VI %s
; FIXME: broken on VI because flat instructions need to be emitted
; instead of addr64 equivalent of the _OFFSET variants.
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
index 30ad3be46053c..d416048942304 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefixes=GCN,GFX9 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck --check-prefixes=GCN,GFX9 %s
+; RUN: llc -mtriple=amdgpu10.10 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
index 7ce3586fd442c..3ad12595fd3e6 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-lshl_add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck %s
define amdgpu_kernel void @lshl1_add(ptr addrspace(1) %in, ptr addrspace(7) %in2) {
; CHECK-LABEL: lshl1_add:
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir b/llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
index 11de739f09f93..10fd4dd429652 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-lshlrev.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX8 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgpu8.03 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX8 %s
+# RUN: llc -mtriple=amdgpu12.00 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GFX12 %s
---
name: lshlrev_b64
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
index 6c18400b66a94..deac7333d85e3 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-fake16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=-real-true16 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
define amdgpu_kernel void @exp_f16(ptr addrspace(1) %ptr) {
; CHECK-LABEL: name: exp_f16
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
index 3768634c1691c..99b77b1517bd2 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu12.00 -mattr=+real-true16 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
define amdgpu_kernel void @exp_f16(ptr addrspace(1) %ptr) {
; CHECK-LABEL: name: exp_f16
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
index 6e8cbc38656a7..17e5bfc3e5b84 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu12.00 -stop-after=si-fix-sgpr-copies < %s | FileCheck %s
define amdgpu_kernel void @exp_f32(ptr addrspace(1) %ptr) {
; CHECK-LABEL: name: exp_f32
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
index e29dab04ed0b1..ed8fef40547d9 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -stop-after=si-fix-sgpr-copies < %s | FileCheck --check-prefix=GFX11 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -stop-after=si-fix-sgpr-copies < %s | FileCheck --check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgpu11.00 -stop-after=si-fix-sgpr-copies < %s | FileCheck --check-prefix=GFX11 %s
+; RUN: llc -mtriple=amdgpu12.00 -stop-after=si-fix-sgpr-copies < %s | FileCheck --check-prefix=GFX12 %s
define amdgpu_ps float @vimage_move_to_valu(<8 x i32> %rsrc) {
; GFX11-LABEL: name: vimage_move_to_valu
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
index 9377387245dcd..d4be3d57133e6 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-worklist.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu8.03 < %s | FileCheck --check-prefix=GCN %s
; In moveToVALU(), move to vector ALU is performed, all instrs in
; the use chain will be visited. We do not want the same node to be
diff --git a/llvm/test/CodeGen/AMDGPU/movreld-bug.ll b/llvm/test/CodeGen/AMDGPU/movreld-bug.ll
index 5bb9f2bac1182..acb61ba7729d0 100644
--- a/llvm/test/CodeGen/AMDGPU/movreld-bug.ll
+++ b/llvm/test/CodeGen/AMDGPU/movreld-bug.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefixes=GCN,MOVREL %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,MOVREL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
+; RUN: llc -mtriple=amdgpu6.01 < %s | FileCheck -check-prefixes=GCN,MOVREL %s
+; RUN: llc -mtriple=amdgpu8.02 < %s | FileCheck -check-prefixes=GCN,MOVREL %s
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck -check-prefixes=GCN,GPRIDX %s
; GCN-LABEL: {{^}}main:
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
index 04d763f0ea6ea..610d80e9bba09 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX9_W64
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W32
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W64
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W32
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W64
-; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx900 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0
+; RUN: llc -mtriple=amdgpu9.00 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX9_W64
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W32
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W64
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W32
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W64
+; RUN: llc -O0 -mtriple=amdgpu9.00 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0
; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
; Uses the old forms of the buffer intrinsics that don't take pointer arguments.
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
index 7a60a79f90a90..6911408544888 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX9_W64
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W32
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W64
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W32
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W64
-; RUN: llc -O0 -mtriple=amdgcn -mcpu=gfx900 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0
+; RUN: llc -mtriple=amdgpu9.00 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX9_W64
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W32
+; RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1010_W64
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize32 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W32
+; RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=GFX1100_W64
+; RUN: llc -O0 -mtriple=amdgpu9.00 -verify-machine-dom-info -o - %s | FileCheck %s --check-prefix=W64-O0
; Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
index e1b31c4ec1a70..37d73ddd1b3d7 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
@@ -1,10 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx700 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64-PRE-GFX10,W64-PRE-GFX10-ADDR64
-# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64-PRE-GFX10,W64-PRE-GFX10-NO-ADDR64
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W32
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W32
+# RUN: llc -mtriple=amdgpu7.00 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64-PRE-GFX10,W64-PRE-GFX10-ADDR64
+# RUN: llc -mtriple=amdgpu9.00 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64-PRE-GFX10,W64-PRE-GFX10-NO-ADDR64
+# RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64
+# RUN: llc -mtriple=amdgpu10.10 -mattr=+wavefrontsize32 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W32
+# RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize64 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W64
+# RUN: llc -mtriple=amdgpu11.00 -mattr=+wavefrontsize32 -verify-machineinstrs -verify-machine-dom-info --run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s --check-prefixes=W32
# Test that we correctly legalize VGPR Rsrc operands in MUBUF instructions.
#
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
index e4e037a17a57b..262f1d11fdf8b 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
-; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
+; RUN: llc -mtriple=amdgpu6.00 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
+; RUN: llc -mtriple=amdgpu8.03 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
+; RUN: llc -mtriple=amdgpu9.00 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; Test addressing modes when the scratch base is not a frame index.
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
index 3acd1b0ef4a92..9993de1d68c93 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s -check-prefix=CHECK
+; RUN: llc < %s -mtriple=amdgpu8.02 | FileCheck %s -check-prefix=CHECK
; Test that buffer_load_format with VGPR resource descriptor is properly
; legalized.
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll b/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
index a5483533fbfe4..835fae79cd727 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s -check-prefix=CHECK
+; RUN: llc < %s -mtriple=amdgpu8.02 | FileCheck %s -check-prefix=CHECK
; Test that buffer_load_format with VGPR resource descriptor is properly
; legalized.
diff --git a/llvm/test/CodeGen/AMDGPU/mubuf.ll b/llvm/test/CodeGen/AMDGPU/mubuf.ll
index 438b63b559de9..74796b29d00a8 100644
--- a/llvm/test/CodeGen/AMDGPU/mubuf.ll
+++ b/llvm/test/CodeGen/AMDGPU/mubuf.ll
@@ -1,4 +1,4 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -show-mc-encoding < %s | FileCheck %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 -show-mc-encoding < %s | FileCheck %s
;;;==========================================================================;;;
;;; MUBUF LOAD TESTS
diff --git a/llvm/test/CodeGen/AMDGPU/mul.i16.ll b/llvm/test/CodeGen/AMDGPU/mul.i16.ll
index f8cce6edd78d1..d615a75fcb52e 100644
--- a/llvm/test/CodeGen/AMDGPU/mul.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul.i16.ll
@@ -1,8 +1,8 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11-TRUE16 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11-FAKE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu8.03 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,GFX89 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX89 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -mattr=-flat-for-global,+real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11-TRUE16 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -mattr=-flat-for-global,-real-true16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX11-FAKE16 %s
; GCN-LABEL: {{^}}v_mul_i16:
; SI: v_and_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
diff --git a/llvm/test/CodeGen/AMDGPU/mul.ll b/llvm/test/CodeGen/AMDGPU/mul.ll
index 4c16159273930..0f6a9317aa9d6 100644
--- a/llvm/test/CodeGen/AMDGPU/mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefixes=SI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX9 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1200 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX12 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1250 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX1250 %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=gfx1310 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX13 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu6.01 < %s | FileCheck -check-prefixes=SI %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu10.10 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu11.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX12 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu12.50 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX1250 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgpu13.10 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX13 %s
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefixes=EG %s
; mul24 and mad24 are affected
diff --git a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
index 57981d1763959..a5af4851b2dc5 100644
--- a/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefix=GFX9 %s
; Make sure that AMDGPUCodeGenPrepare introduces mul24 intrinsics
; after SLSR, as the intrinsics would interfere. It's unclear if these
diff --git a/llvm/test/CodeGen/AMDGPU/mul_int24.ll b/llvm/test/CodeGen/AMDGPU/mul_int24.ll
index c89279d3bf81c..46455fc709275 100644
--- a/llvm/test/CodeGen/AMDGPU/mul_int24.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul_int24.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefixes=SI %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefixes=SI %s
+; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=VI %s
+; RUN: llc -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
diff --git a/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll b/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
index d7d78b8450053..2e24bec6bb5b1 100644
--- a/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
+++ b/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
+; RUN: llc -mtriple=amdgpu8.02 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
+; RUN: llc -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone
diff --git a/llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll b/llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
index 4c6a6ae95c5ba..db9f57b9061c6 100644
--- a/llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/multi-call-resource-usage-mcexpr.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.0a-amd-amdhsa < %s | FileCheck %s
; CHECK-LABEL: {{^}}qux
; CHECK: .set .Lqux.num_vgpr, 13
diff --git a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
index 7abd2c29016e2..f72cb2327af4c 100644
--- a/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
+++ b/llvm/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
@@ -1,6 +1,6 @@
-; RUN: opt -mtriple=amdgcn-- -mcpu=gfx600 -S -lowerswitch -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
-; RUN: opt -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+wavefrontsize64 -S -lowerswitch -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
+; RUN: opt -mtriple=amdgpu6.00-- -S -lowerswitch -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
+; RUN: opt -mtriple=amdgpu11.00-- -mattr=+wavefrontsize64 -S -lowerswitch -amdgpu-unify-divergent-exit-nodes -verify -structurizecfg -verify -si-annotate-control-flow -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
+; RUN: llc -mtriple=amdgpu6.00 -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; Add an extra verifier runs. There were some cases where invalid IR
; was produced but happened to be fixed by the later passes.
diff --git a/llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll b/llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
index f9ff3dd281290..8afdf1c582ca3 100644
--- a/llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/multi-dword-vgpr-spill.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck %s -check-prefixes=GCN,MUBUF
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 -mattr=+enable-flat-scratch < %s | FileCheck %s -check-prefixes=GCN,FLATSCR
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck %s -check-prefixes=GCN,MUBUF
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -enable-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 -mattr=+enable-flat-scratch < %s | FileCheck %s -check-prefixes=GCN,FLATSCR
; GCN-LABEL: spill_v2i32:
; MUBUF-DAG: buffer_store_dword v{{.*}} offset:16 ; 4-byte Folded Spill
diff --git a/llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
index 788065fd1391d..99d42708a3cd2 100644
--- a/llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/multi-use-implicit-def.mir
@@ -4,7 +4,7 @@
# before removing the IMPLICIT_DEF. -verify-machineinstrs will
# fail otherwise.
-# RUN: llc -mtriple=amdgcn -mcpu=gfx802 -run-pass processimpdefs -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu8.02 -run-pass processimpdefs -asm-verbose=0 -verify-machineinstrs %s -o - | FileCheck %s
---
diff --git a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
index da012e6ff907d..0c5b90d9c2ae0 100644
--- a/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
+++ b/llvm/test/CodeGen/AMDGPU/multilevel-break.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -S -mtriple=amdgcn-- -lowerswitch -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GCN %s
+; RUN: opt -S -mtriple=amdgpu-- -lowerswitch -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck -check-prefix=GCN %s
; Ensure two if.break calls, for both the inner and outer loops
; FIXME: duplicate comparison
diff --git a/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll b/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
index 7ca5e648714d8..6dccbed72ac48 100644
--- a/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/naked-fn-with-frame-pointer.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx600 | FileCheck %s -check-prefixes=CHECK
+; RUN: llc < %s -mtriple=amdgpu6.00 | FileCheck %s -check-prefixes=CHECK
declare dso_local void @main()
diff --git a/llvm/test/CodeGen/AMDGPU/nand.ll b/llvm/test/CodeGen/AMDGPU/nand.ll
index 781ce34ec8362..1defcbe8b182a 100644
--- a/llvm/test/CodeGen/AMDGPU/nand.ll
+++ b/llvm/test/CodeGen/AMDGPU/nand.ll
@@ -1,7 +1,7 @@
-; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck --check-prefix=GCN %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu6.00 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu7.00 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu8.01 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple=amdgpu9.00 < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: {{^}}scalar_nand_i32_one_use
; GCN: s_nand_b32
diff --git a/llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll b/llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
index efc7dec0297f9..ac3883659f84a 100644
--- a/llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
+++ b/llvm/test/CodeGen/AMDGPU/narrow_math_for_and.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu11.00 < %s | FileCheck %s
define i64 @narrow_add(i64 %a, i64 %b) {
; CHECK-LABEL: narrow_add:
diff --git a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
index ccc1ce5316ce7..cffd63a2a4e55 100644
--- a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
+++ b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -O0 < %s | FileCheck %s
; FP is in CSR range, modified.
define hidden fastcc void @callee_has_fp() #1 {
diff --git a/llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll b/llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
index db82530f66aa4..9ba4b39c9573c 100644
--- a/llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
+++ b/llvm/test/CodeGen/AMDGPU/neg_ashr64_reduce.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdpal < %s | FileCheck %s
; Test that negative 64-bit values shifted by [32-63] bits have
; a hi-result created by moving an all-ones constant.
diff --git a/llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir b/llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
index 4d1a663aace42..702257251228a 100644
--- a/llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
+++ b/llvm/test/CodeGen/AMDGPU/neighboring-mfma-padding.mir
@@ -1,17 +1,17 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-DEFAULT %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -amdgpu-mfma-padding-ratio=25 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD25 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -amdgpu-mfma-padding-ratio=50 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD50 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -amdgpu-mfma-padding-ratio=75 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD75 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -amdgpu-mfma-padding-ratio=100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD100 %s
+# RUN: llc -mtriple=amdgpu9.08 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-DEFAULT %s
+# RUN: llc -mtriple=amdgpu9.08 -amdgpu-mfma-padding-ratio=25 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD25 %s
+# RUN: llc -mtriple=amdgpu9.08 -amdgpu-mfma-padding-ratio=50 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD50 %s
+# RUN: llc -mtriple=amdgpu9.08 -amdgpu-mfma-padding-ratio=75 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD75 %s
+# RUN: llc -mtriple=amdgpu9.08 -amdgpu-mfma-padding-ratio=100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx908-PAD100 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx90a-DEFAULT %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-padding-ratio=50 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx90a-PAD50 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -amdgpu-mfma-padding-ratio=100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx90a-PAD100 %s
+# RUN: llc -mtriple=amdgpu9.0a -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx90a-DEFAULT %s
+# RUN: llc -mtriple=amdgpu9.0a -amdgpu-mfma-padding-ratio=50 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx90a-PAD50 %s
+# RUN: llc -mtriple=amdgpu9.0a -amdgpu-mfma-padding-ratio=100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx90a-PAD100 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx942-DEFAULT %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -amdgpu-mfma-padding-ratio=50 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx942-PAD50 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -amdgpu-mfma-padding-ratio=100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx942-PAD100 %s
+# RUN: llc -mtriple=amdgpu9.42 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx942-DEFAULT %s
+# RUN: llc -mtriple=amdgpu9.42 -amdgpu-mfma-padding-ratio=50 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx942-PAD50 %s
+# RUN: llc -mtriple=amdgpu9.42 -amdgpu-mfma-padding-ratio=100 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=gfx942-PAD100 %s
---
name: mfma_padding_2_pass
diff --git a/llvm/test/CodeGen/AMDGPU/nested-calls.ll b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
index da9463b1329c7..1e05c5e31af9e 100644
--- a/llvm/test/CodeGen/AMDGPU/nested-calls.ll
+++ b/llvm/test/CodeGen/AMDGPU/nested-calls.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,FIJI %s
-; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -enable-var-scope -check-prefixes=GCN,HAWAII %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
+; RUN: llc -mtriple=amdgpu8.03 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,FIJI %s
+; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,HAWAII %s
+; RUN: llc -mtriple=amdgpu9.00 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; Test calls when called by other callable functions rather than
; kernels.
diff --git a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
index 9e88a62925e50..911dbaa154a8f 100644
--- a/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
+++ b/llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s
-; RUN: llc -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefix=GCN %s
+; RUN: opt -mtriple=amdgpu-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=IR %s
+; RUN: llc -mtriple=amdgpu7.01 < %s | FileCheck -check-prefix=GCN %s
; After structurizing, there are 3 levels of loops. The i1 phi
; conditions mutually depend on each other, so it isn't safe to delete
diff --git a/llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll b/llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
index 8e68c462960eb..218c42fe3167c 100644
--- a/llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-bundle-asm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa < %s | FileCheck %s
; SIPostRABundler used to incorrectly try to form a bundle containing
; inline asm.
diff --git a/llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll b/llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
index df717d0ae497d..aced83a9016cb 100644
--- a/llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-corresponding-integer-type.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 %s -o - | FileCheck %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx9-4-generic --amdhsa-code-object-version=6 %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.42-amd-amdhsa %s -o - | FileCheck %s
+; RUN: llc -mtriple=amdgpu9.4-amd-amdhsa --amdhsa-code-object-version=6 %s -o - | FileCheck %s
define void @no_corresponding_integer_type(i8 %arg, ptr addrspace(1) %ptr) {
; CHECK-LABEL: no_corresponding_integer_type:
diff --git a/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll b/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
index 306703bd61806..22f17fa4a6dc9 100644
--- a/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s
+; RUN: llc -mtriple=amdgpu10.30 < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgpu12.00 < %s | FileCheck --check-prefix=GFX12 %s
define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {
; GFX10-LABEL: _amdgpu_cs_main:
diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
index 92e6d985062bd..dec44a092485f 100644
--- a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
+++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 %s -o - | FileCheck %s --check-prefixes=GFX942
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 %s -o - | FileCheck %s --check-prefixes=GFX908
+; RUN: llc -mtriple=amdgpu9.42--amdhsa %s -o - | FileCheck %s --check-prefixes=GFX942
+; RUN: llc -mtriple=amdgpu9.08--amdhsa %s -o - | FileCheck %s --check-prefixes=GFX908
define amdgpu_kernel void @matmul_kernel(i32 %a0, i32 %a1) {
; GFX942-LABEL: matmul_kernel:
diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
index 01506d0af1913..6b46a7817e1c8 100644
--- a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
+++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
+# RUN: llc -mtriple=amdgpu9.42--amdhsa -run-pass si-fold-operands %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42--amdhsa -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
+# RUN: llc -mtriple=amdgpu9.08--amdhsa -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
...
---
diff --git a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
index a9207de317ea1..f1db16419bfd7 100644
--- a/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
+++ b/llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-read.mir
@@ -1,7 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
+# RUN: llc -mtriple=amdgpu9.42--amdhsa -run-pass si-fold-operands %s -o - | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42--amdhsa -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE
+# RUN: llc -mtriple=amdgpu9.08--amdhsa -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE
...
---
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