[llvm-branch-commits] [clang] [llvm] [X86][ACE] Add x86_bsr type and Block Scale Register support (PR #208706)

[Renato Golin via llvm-branch-commits]

rengolin wrote:

> @mahesh-attarde @rengolin @RKSimon 
> 
> This is an implementation which takes inspiration from x86_amx. I think with this, MLIR passes can reason about BSR lifetimes, insert spills, and optimize scale factor reuse all at the type level for BSRs. Making BSR explicit also helps in SSA tracking. Had thoughts against this idea as at present BSR is a single register. Nevertheless would like to take your suggestions/comments. At present it supports both no_bsr and bsr. If we decide to have this implementation, we can safely drop the no_bsr path.

MLIR doesn't have a register allocator, we cannot insert spills from this high level. We need that logic to be in LLVM similar to AMX. 

https://github.com/llvm/llvm-project/pull/208706