[llvm-branch-commits] [llvm] AMDGPU/GlobalISel: Handle G_BITCAST for 16 bit extendedLLTs (PR #208750)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Jul 10 08:14:34 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
@llvm/pr-subscribers-llvm-globalisel
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
Handle bitcast between i16 and f16/bf16.
For true16 this was already legal, make it legal in regbanklegalize as well.
For non-true16 custom lower it to G_ANYEXT to i32 and G_TRUNC to dst.
The "i32 G_ANYEXT f16/bf16" and "f16/bf16 G_TRUNC i32" are already legal,
for example these are generated by common CallLowering argument lowering.
---
Patch is 3.01 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/208750.diff
188 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (+16)
- (modified) llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h (+2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll (+14-46)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll (+7-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll (+2-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll (+9-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-binop-s64-with-s32-mask.mir (+30-30)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll (+8-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fabs.ll (+35-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fadd.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fcmp.ll (+158-76)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll (+361-171)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmamix-constant-bus-violation.ll (+19-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll (+6-8)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll (+7-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmin3-fmax3-combine.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fneg.ll (+35-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll (+1673-1376)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll (+2828-2555)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll (+2884-2376)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fsub.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir (+59-60)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll (+511-530)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll (+656-996)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll (+31-49)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll (+175-237)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll (+37-63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fract.ll (+6-3)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.frexp.mant.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll (+766-675)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll (+36-12)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll (+168-68)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll (+18-18)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll (+199-103)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll (+119-122)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll (+35-51)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll (+10-14)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll (+34-58)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll (+9-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll (+390-266)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll (+366-232)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll (+23-25)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll (+127-122)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll (+189-91)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll (+22-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll (+142-86)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.powi.ll (+29-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.ll (+19-10)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll (+33-26)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/select-to-fmin-fmax.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/smed3.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+33-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll (+24-24)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/sub.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll (+11-7)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll (+10-8)
- (modified) llvm/test/CodeGen/AMDGPU/add-max.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/atomicrmw_usub_sat.ll (+258-224)
- (modified) llvm/test/CodeGen/AMDGPU/bfi_int.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/bitop3.ll (+45-47)
- (modified) llvm/test/CodeGen/AMDGPU/bitreverse.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll (+279-111)
- (modified) llvm/test/CodeGen/AMDGPU/call-args-inreg.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/call-return-types.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/commute-compares-scalar-float.ll (+25-17)
- (modified) llvm/test/CodeGen/AMDGPU/ctlz.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/ctpop64.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/cttz.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll (+148-82)
- (modified) llvm/test/CodeGen/AMDGPU/diverge-interp-mov-lower.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fadd.f16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll (+11-2)
- (modified) llvm/test/CodeGen/AMDGPU/float-sopc-vopc.ll (+86-58)
- (modified) llvm/test/CodeGen/AMDGPU/fma.f16.ll (+91-54)
- (modified) llvm/test/CodeGen/AMDGPU/fmaximum.ll (+23-12)
- (modified) llvm/test/CodeGen/AMDGPU/fmaxnum.ll (+89-42)
- (modified) llvm/test/CodeGen/AMDGPU/fmed3-cast-combine.ll (+117-62)
- (modified) llvm/test/CodeGen/AMDGPU/fmed3.ll (+8-4)
- (modified) llvm/test/CodeGen/AMDGPU/fminimum.ll (+24-13)
- (modified) llvm/test/CodeGen/AMDGPU/fminnum.ll (+90-43)
- (modified) llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll (+349-179)
- (modified) llvm/test/CodeGen/AMDGPU/fold-gep-offset.ll (+7-7)
- (modified) llvm/test/CodeGen/AMDGPU/fptoi.i128.ll (+116-57)
- (modified) llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll (+51-22)
- (modified) llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll (+14-6)
- (modified) llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll (+242-318)
- (modified) llvm/test/CodeGen/AMDGPU/freeze.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll (+156-70)
- (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll (+44-40)
- (modified) llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll (+22-19)
- (modified) llvm/test/CodeGen/AMDGPU/itofp.i128.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/literal64.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll (+112-53)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll (+208-100)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll (+16-16)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dead.ll (+87-67)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp2.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll (+106-82)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll (+168-119)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.flat.prefetch.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.f16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.async.to.lds.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.prefetch.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.async.from.lds.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll (+178-113)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.noret.ll (+34-14)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.f16.ll (+9-9)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll (+98-189)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.monitor.gfx1250.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.log.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll (+3629-3802)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll (+101-148)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll (+56-157)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll (+56-157)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll (+103-148)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sqrt.f16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.gfx90a.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll (+10-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp.ll (+359-175)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp10.ll (+365-178)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.exp2.ll (+21-10)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll (+21-24)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.get.rounding.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll (+1242-555)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.ldexp.ll (+72-36)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log.ll (+148-79)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log10.ll (+148-79)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.log2.ll (+21-12)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.modf.ll (+48-22)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.set.rounding.ll (+6-6)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/lround.ll (+11-6)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll (+220-103)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll (+15-8)
- (modified) llvm/test/CodeGen/AMDGPU/mad-mix.ll (+613-291)
- (modified) llvm/test/CodeGen/AMDGPU/memset-pattern.ll (+622-300)
- (modified) llvm/test/CodeGen/AMDGPU/minimummaximum.ll (+54-37)
- (modified) llvm/test/CodeGen/AMDGPU/minmax.ll (+61-52)
- (modified) llvm/test/CodeGen/AMDGPU/pseudo-scalar-transcendental.ll (+68-35)
- (modified) llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll (+16-6)
- (modified) llvm/test/CodeGen/AMDGPU/scalar-float-sop2.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/scale-offset-flat.ll (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/scale-offset-global.ll (+4-4)
- (modified) llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll (+5-5)
- (modified) llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll (+76-46)
- (modified) llvm/test/CodeGen/AMDGPU/v_pack.ll (+3-3)
- (modified) llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll (+2-2)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 2180ce67d576f..0718fb5a1314a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -293,6 +293,10 @@ static LegalityPredicate elementTypeIsLegal(unsigned TypeIdx) {
};
}
+const LLT I16 = LLT::integer(16);
+constexpr LLT F16 = LLT::float16();
+constexpr LLT BF16 = LLT::bfloat16();
+
constexpr LLT S1 = LLT::scalar(1);
constexpr LLT S8 = LLT::scalar(8);
constexpr LLT S16 = LLT::scalar(16);
@@ -926,6 +930,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
getActionDefinitionsBuilder(G_BITCAST)
// Don't worry about the size constraint.
.legalIf(all(isRegisterClassType(ST, 0), isRegisterClassType(ST, 1)))
+ .customFor({{I16, F16}, {F16, I16}, {I16, BF16}, {BF16, I16}})
.lower();
getActionDefinitionsBuilder(G_CONSTANT)
@@ -2314,6 +2319,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(
switch (MI.getOpcode()) {
case TargetOpcode::G_ADDRSPACE_CAST:
return legalizeAddrSpaceCast(MI, MRI, B);
+ case TargetOpcode::G_BITCAST:
+ return legalizeBitcast(MI, MRI, B);
case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
return legalizeFroundeven(MI, MRI, B);
case TargetOpcode::G_FCEIL:
@@ -2704,6 +2711,15 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
return true;
}
+bool AMDGPULegalizerInfo::legalizeBitcast(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const {
+ B.buildTrunc(MI.getOperand(0).getReg(),
+ B.buildAnyExt(LLT::integer(32), MI.getOperand(1).getReg()));
+ MI.eraseFromParent();
+ return true;
+}
+
bool AMDGPULegalizerInfo::legalizeFroundeven(MachineInstr &MI,
MachineRegisterInfo &MRI,
MachineIRBuilder &B) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
index 89819fe990f5a..512160857f91d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
@@ -43,6 +43,8 @@ class AMDGPULegalizerInfo final : public LegalizerInfo {
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
+ bool legalizeBitcast(MachineInstr &MI, MachineRegisterInfo &MRI,
+ MachineIRBuilder &B) const;
bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineIRBuilder &B) const;
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 7f7225ad6d311..df5b5719afd05 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -753,6 +753,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{DivBRC}, {{VgprBRC}, {VgprBRC}}});
addRulesForGOpcs({G_BITCAST})
+ .Any({{UniS16}, {{Sgpr16}, {Sgpr16}}})
+ .Any({{DivS16}, {{Vgpr16}, {Vgpr16}}})
.Any({{UniBRC}, {{SgprBRC}, {SgprBRC}}})
.Any({{DivBRC}, {{VgprBRC}, {VgprBRC}}});
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index 7471343b3a9a3..245225d204c94 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -731,6 +731,7 @@ define amdgpu_ps i16 @s_ashr_i16_15(i16 inreg %value) {
define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
; GFX6-LABEL: ashr_i16_sv:
; GFX6: ; %bb.0:
+; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX6-NEXT: s_sext_i32_i16 s0, s0
; GFX6-NEXT: v_ashr_i32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
@@ -767,6 +768,7 @@ define amdgpu_ps half @ashr_i16_sv(i16 inreg %value, i16 %amount) {
define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) {
; GFX6-LABEL: ashr_i16_vs:
; GFX6: ; %bb.0:
+; GFX6-NEXT: s_and_b32 s0, s0, 0xffff
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX6-NEXT: v_ashrrev_i32_e32 v0, s0, v0
; GFX6-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
index 68a966816a9e1..18e03a19d5acf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
@@ -121,28 +121,12 @@ define bfloat @atomic_load_flat_monotonic_bf16(ptr %ptr) {
}
define i32 @atomic_load_flat_monotonic_f16_zext_to_i32(ptr %ptr) {
-; GFX7-LABEL: atomic_load_flat_monotonic_f16_zext_to_i32:
-; GFX7: ; %bb.0:
-; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: flat_load_ushort v0, v[0:1] glc
-; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: atomic_load_flat_monotonic_f16_zext_to_i32:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
-; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: atomic_load_flat_monotonic_f16_zext_to_i32:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: flat_load_ushort v0, v[0:1] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: atomic_load_flat_monotonic_f16_zext_to_i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: flat_load_ushort v0, v[0:1] glc
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
%load = load atomic half, ptr %ptr monotonic, align 2
%cast = bitcast half %load to i16
%ext = zext i16 %cast to i32
@@ -150,28 +134,12 @@ define i32 @atomic_load_flat_monotonic_f16_zext_to_i32(ptr %ptr) {
}
define i32 @atomic_load_flat_monotonic_bf16_zext_to_i32(ptr %ptr) {
-; GFX7-LABEL: atomic_load_flat_monotonic_bf16_zext_to_i32:
-; GFX7: ; %bb.0:
-; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT: flat_load_ushort v0, v[0:1] glc
-; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: atomic_load_flat_monotonic_bf16_zext_to_i32:
-; GFX8: ; %bb.0:
-; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
-; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: atomic_load_flat_monotonic_bf16_zext_to_i32:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: flat_load_ushort v0, v[0:1] glc
-; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: atomic_load_flat_monotonic_bf16_zext_to_i32:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: flat_load_ushort v0, v[0:1] glc
+; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT: s_setpc_b64 s[30:31]
%load = load atomic bfloat, ptr %ptr monotonic, align 2
%cast = bitcast bfloat %load to i16
%ext = zext i16 %cast to i32
@@ -270,7 +238,7 @@ define <2 x i16> @atomic_load_flat_monotonic_i16_d16_lo_vector_insert(ptr %ptr,
; GFX7-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: atomic_load_flat_monotonic_i16_d16_lo_vector_insert:
@@ -279,7 +247,7 @@ define <2 x i16> @atomic_load_flat_monotonic_i16_d16_lo_vector_insert(ptr %ptr,
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_flat_monotonic_i16_d16_lo_vector_insert:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
index d0715b1270d49..8c78297da1fdd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
@@ -367,8 +367,7 @@ define i32 @atomic_load_global_monotonic_f16_zext_to_i32(ptr addrspace(1) %ptr)
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0x100f000
-; GFX6-NEXT: s_mov_b32 s4, s6
-; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -385,7 +384,6 @@ define i32 @atomic_load_global_monotonic_f16_zext_to_i32(ptr addrspace(1) %ptr)
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_global_monotonic_f16_zext_to_i32:
@@ -393,7 +391,6 @@ define i32 @atomic_load_global_monotonic_f16_zext_to_i32(ptr addrspace(1) %ptr)
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
%load = load atomic half, ptr addrspace(1) %ptr monotonic, align 2
%cast = bitcast half %load to i16
@@ -407,8 +404,7 @@ define i32 @atomic_load_global_monotonic_bf16_zext_to_i32(ptr addrspace(1) %ptr)
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0x100f000
-; GFX6-NEXT: s_mov_b32 s4, s6
-; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_setpc_b64 s[30:31]
@@ -425,7 +421,6 @@ define i32 @atomic_load_global_monotonic_bf16_zext_to_i32(ptr addrspace(1) %ptr)
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_global_monotonic_bf16_zext_to_i32:
@@ -433,7 +428,6 @@ define i32 @atomic_load_global_monotonic_bf16_zext_to_i32(ptr addrspace(1) %ptr)
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
%load = load atomic bfloat, ptr addrspace(1) %ptr monotonic, align 2
%cast = bitcast bfloat %load to i16
@@ -488,8 +482,7 @@ define <2 x i16> @atomic_load_global_monotonic_i16_d16_hi_vector_insert(ptr addr
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0x100f000
-; GFX6-NEXT: s_mov_b32 s4, s6
-; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 glc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2
; GFX6-NEXT: s_waitcnt vmcnt(0)
@@ -586,12 +579,11 @@ define <2 x i16> @atomic_load_global_monotonic_i16_d16_lo_vector_insert(ptr addr
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0x100f000
-; GFX6-NEXT: s_mov_b32 s4, s6
-; GFX6-NEXT: s_mov_b32 s5, s6
+; GFX6-NEXT: s_mov_b64 s[4:5], 0
; GFX6-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 glc
; GFX6-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX6-NEXT: s_waitcnt vmcnt(0)
-; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX7-LABEL: atomic_load_global_monotonic_i16_d16_lo_vector_insert:
@@ -600,7 +592,7 @@ define <2 x i16> @atomic_load_global_monotonic_i16_d16_lo_vector_insert(ptr addr
; GFX7-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: atomic_load_global_monotonic_i16_d16_lo_vector_insert:
@@ -609,7 +601,7 @@ define <2 x i16> @atomic_load_global_monotonic_i16_d16_lo_vector_insert(ptr addr
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_global_monotonic_i16_d16_lo_vector_insert:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
index 6119e1a9bf796..a374e66fb971b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
@@ -297,7 +297,6 @@ define i32 @atomic_load_local_monotonic_f16_zext_to_i32(ptr addrspace(3) %ptr) {
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_read_u16 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_local_monotonic_f16_zext_to_i32:
@@ -305,7 +304,6 @@ define i32 @atomic_load_local_monotonic_f16_zext_to_i32(ptr addrspace(3) %ptr) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ds_read_u16 v0, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
%load = load atomic half, ptr addrspace(3) %ptr monotonic, align 2
%cast = bitcast half %load to i16
@@ -328,7 +326,6 @@ define i32 @atomic_load_local_monotonic_bf16_zext_to_i32(ptr addrspace(3) %ptr)
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_read_u16 v0, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_local_monotonic_bf16_zext_to_i32:
@@ -336,7 +333,6 @@ define i32 @atomic_load_local_monotonic_bf16_zext_to_i32(ptr addrspace(3) %ptr)
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: ds_read_u16 v0, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
%load = load atomic bfloat, ptr addrspace(3) %ptr monotonic, align 2
%cast = bitcast bfloat %load to i16
@@ -458,7 +454,7 @@ define <2 x i16> @atomic_load_local_monotonic_i16_d16_lo_vector_insert(ptr addrs
; GFX7-NEXT: ds_read_u16 v0, v0
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX7-NEXT: v_or_b32_e32 v0, v1, v0
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: atomic_load_local_monotonic_i16_d16_lo_vector_insert:
@@ -468,7 +464,7 @@ define <2 x i16> @atomic_load_local_monotonic_i16_d16_lo_vector_insert(ptr addrs
; GFX8-NEXT: ds_read_u16 v0, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_local_monotonic_i16_d16_lo_vector_insert:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
index 84da2f2007d85..d00c4169fd6e7 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
define float @test_fmed3_f32_known_nnan_ieee_true(float %a) #0 {
; GFX10-LABEL: test_fmed3_f32_known_nnan_ieee_true:
@@ -35,13 +35,13 @@ define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 {
; GFX10-LABEL: test_fmed3_f16_known_nnan_ieee_false:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_add_f16_e64 v0, v0, v0 clamp
+; GFX10-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX1170-LABEL: test_fmed3_f16_known_nnan_ieee_false:
; GFX1170: ; %bb.0:
; GFX1170-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1170-NEXT: v_add_f16_e64 v0, v0, v0 clamp
+; GFX1170-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
; GFX1170-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_fmed3_f16_known_nnan_ieee_false:
@@ -61,7 +61,7 @@ define half @test_fmed3_f16_known_nnan_ieee_false(half %a) #1 {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_add_f16_e64 v0, v0, v0 clamp
+; GFX12-FAKE16-NEXT: v_mul_f16_e64 v0, v0, 2.0 clamp
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
%fmul = fmul half %a, 2.0
%fmed = call nnan half @llvm.amdgcn.fmed3.f16(half %fmul, half 0.0, half 1.0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
index d46d658e8a6b0..75be830fc8a77 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1170 -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX1170 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
-; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12,GFX12-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/208750
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