[llvm-branch-commits] [clang] [llvm] [X86][ACE] Add x86_bsr type and Block Scale Register support (PR #208706)

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ganeshgit wrote:

@mahesh-attarde @rengolin @RKSimon 

This is an implementation which takes inspiration from x86_amx. I think MLIR passes can reason about BSR lifetimes, insert spills, and optimize scale factor reuse all at the type level for BSRs. Making BSR explicit also helps in SSA tracking. Had thoughts to against this idea nevertheless would like to take your suggestions/comments. At present it supports both no_bsr and bsr. If we decide to have this implementation, we can safely drop the no_bsr path.

https://github.com/llvm/llvm-project/pull/208706